BCM8727MCIFBG

BCM8727 Brief ® DUAL-CHANNEL 10-GBE SFI-TO-XAUI™ TRANSCEIVER WITH EDC SUMMARY OF BENEFITS FEATURES • Dual-channel SFI-to-XAUI™ transceiver • Single-reference clock input enables use of low-cost 156.25 MHz oscillator. • Integrated microcontroller and AGC with a wide dynamic • Supports low-cost SFP+ copper twin-ax up to 15m range • Supports SFP+ SR, LR, and LRM optical interfaces and up to • LRM mode supports 300m of Multimode Fiber (MMF), 15m of direct attached copper exceeding the IEEE 802.3aq standard. • Programmable amplitude control on 10G serial transmitter • PMD transmit preemphasis for flexible placement of Physical interface Layer (PHY) • Standard two-wire Broadcom Serial Interface (BSC) support • Support for module present detection and configuring of for external E2, XFP, SFP, SFP+ BCM8727 accordingly • MDIO interface compliant to IEEE802.3ae Clause 45 with • Multirate 10 GbE and 1 GbE support for legacy interfaces extended indirect address register access • Support for XFP/XFI interfaces APPLICATIONS • Physical Medium Dependent (PMD) interface: serial 10.3125 Gbps CML • PCS 64B/66B scrambler/descrambler • High-density Ethernet Switching and Routing Platforms • XGXS 8B/10B error detection ENDEC • Next-generation Blade Servers • XAUI link synchronization/deskew • SFP+ optical SR, LR, and LRM modules • 4-lane XAUI interface (3.125 Gbps) • SFP+ copper twin-ax • Built-In Self-Test (BIST) on 10G serial and XAUI interfaces • Power dissipation: 2.4W • Core supply—1.0V, I/O—3.3V • Small 19 mm x 19 mm BGA package, 1-mm ball pitch BCM8727 Functional Block Diagram BCM8727 XGXS PCS/PMA MAC/ Switch XGXS RS XAUI Interface 1 Management Interface SFP+ 10.3125 Gbps SFI 2 SFP+ 10.3125 Gbps LRMEDC XAUI Interface 2 MDC MDIO SFI 1 LRMEDC XDON 8B/10B Encoder Serializer 8B/10B Encoder 64/66B Synchronizer Descrambler Decoder Gearbox XDOP Serializer Randomizer MMF EDC DSP Core CDR and Deserializer PDIP AGC PDIN 322.26M 312.5M CMU 156.25M 10.3125 Gbps 3.125 Gbps XAOP XAON Elastic FIFO OVERVIEW 156.25 MHz REFCK REFCLKP REFCLKN RefClk Block 32K ROM 312.5M XDIP XDIN XDOP XDON Serializer 8B/10B Encoder Serializer 8B/10B Encoder REFCK 64/66B Synchronizer Descrambler Decoder Gearbox PDOP CMU and Serializer PDON MMF EDC DSP Core CDR and Deserializer PDIP AGC PDIN 156.25M RefClk Block 32K ROM 312.5M Lane Alignment FIFO DLL and Deserializer Sync. Detect Lane Sync 8B/10B Decoder Lane Alignment FIFO uC SPI SPI 322.26M 64/66B Encoder Scrambler Gearbox DLL and Deserializer 3.125 Gbps XDIP XDIN 16K RAM 312.5M Sync. Detect Lane Sync 8B/10B Decoder Elastic FIFO XAIP XAIN SDA SCL SPI 322.26M 312.5M CMU MDIO MDC PRTAD[4:1] RSTB LASI SPI 10.3125 Gbps 3.125 Gbps XAOP XAON 64/66B Encoder Scrambler Gearbox Lane Alignment FIFO uC 322.26M Elastic FIFO DLL and Deserializer Sync. Detect Lane Sync 8B/10B Decoder Elastic FIFO Lane Alignment FIFO 3.125 Gbps DLL and Deserializer Randomizer XAIP XAIN 16K RAM 312.5M Sync. Detect Lane Sync 8B/10B Decoder PDOP CMU and Serializer PDON Management and Control Interface BSC Serial Interface Optics Control and Status JTAG OPRXLOS MOD_ABS OPTXENB OPRSTB BCM8727 Block Diagram The BCM8727 is a dual-channel 10-GbE SFI-to-XAUI transceiver that incorporates an Electronic Dispersion Compensation (EDC) equalizer supporting SFP+ line-card applications. The BCM8727 is a multirate PHY targeted for SMF, MMF, or copper twin-ax applications interfacing to both limiting-based and linear-based SFP+ and SFP modules. The BCM8727 is fully compliant to the 10-GbE IEEE 802.3aq standard and also supports 1000BASE-X for 1-GbE operation. The BCM8727 is developed using an all-DSP high-speed front-end providing the highest performance and most flexibility for line-card designers. An on-chip microcontroller implements the control algorithm for the DSP core. On-chip clock synthesis is performed by the high-frequency, low-jitter, Phase-Locked Loops (PLLs) for the PMD and XAUI output retimers. Individual PMD and XAUI clock recovery is performed on the device by synchronizing directly to the respective incoming data streams. An external 156.25 MHz reference clock input is required for each port. The BCM8727 Ethernet LRM PHY device is a fully integrated SerDes (10.3125 Gbps) interface device performing the extension functions for a 10-Gigabit serial Ethernet Reconciliation Sublayer (RS) interface. The XGXS, PCS, and PMA functions include 8B/10B coding, 64B/66B coding, SerDes, Clock Multiplication Unit (CMU), and Clock and Data Recovery (CDR). The BCM8727 is available in a 19 mm x 19 mm, 1 mm pitch, 324-pin BGA, RoHS-compliant package. The BCM8727 supports a footprintcompatible layout with the BCM8726 dual LRM PHY. Broadcom®, the pulse logo, Connecting everything®, and the Connecting everything logo are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. ® BROADCOM CORPORATION 5300 California Avenue Irvine, California 92617 © 2009 by BROADCOM CORPORATION. All rights reserved. 8727-PB00-R 03/16/09 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: info@broadcom.com Web: www.broadcom.com