HCPL-0738-000E

HCPL-0738 High Speed CMOS Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description The HCPL-0738 is a dual-channel 15 MBd CMOS optocoupler in SOIC-8 package. The HCPL-0738 optocoupler utilizes the latest CMOS IC technology to achieve out-standing performance with very low power consumption. Basic building blocks of HCPL-0738 are high speed LEDs and CMOS detector ICs. Avago also offers the same performance in the single channel version, HCPL-0708. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Functional Diagram ANODE 1 1 8 VDD CATHODE 1 2 7 VO 1 CATHODE 2 3 6 VO 2 ANODE 2 4 5 GND Features • 15 ns typical pulse width distortion • 40 ns maximum propagation delay skew • 20 ns typical propagation delay • High speed: 15 MBd • + 5 V CMOS compatibility • 10 kV/µS minimum common mode rejection • –40 to 100˚C temperature range • Safety and regulatory approvals – UL recognized (3750 V rms for 1 minute per UL 1577) – CSA component acceptance notice #5. – IEC/EN/DIN EN 60747-5-2 approved for HCPL-0738 Option 060 Applications • PDP (plasma display panel) • Digital field bus isolation: DeviceNet, SDS, Profibus • Multiplexed data transmission • Computer peripheral interface • Microprocessor system interface • DC/DC converter Truth Table LED OFF ON TRUTH TABLE LED OFF ON VO, OUTPUT VO,HOutput H L L Note: A 0.1 µF bypass capacitor must be connected between pins 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Ordering Information HCPL-0738 is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number RoHS Compliant Non RoHS Compliant -000E No option -500E -500 -060E -060 HCPL-0738 Surface Gull Tape UL 5000 Vrms/ Package Mount Wing & Reel 1 Minute rating IEC/EN/DIN EN 60747-5-2 Quantity X SO-8 100 per tube X X 1500 per reel X X 100 per tube To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-0738-500E to order product of Small Outline SO-8 package in Tape and Reel packaging in RoHS compliant. Example 2: HCPL-0738 to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Selection Guide Small Outline SO-8 HCPL-0738 Package Outline Drawing HCPL-0738 Outline Drawing (Small Outline SO-8 Package) LAND PATTERN RECOMMENDATION 8 7 6 5 XXX YWW 3.937 ± 0.127 (0.155 ± 0.005) PIN 1 ONE 2 3 0.405 ± 0.076 (0.015 ± 0.003) 5.994 ± 0.203 (0.236 ± 0.008) DATE CODE 4 1.9 (0.075) 1.270 BSC (0.050) 0.64 (0.025) *5.080 ± 0.127 (0.205 ± 0.005) 3.175 ± 0.127 (0.125 ± 0.005) 7.49 (0.295) TYPE NUMBER (LAST 3 DIGITS) 7° 1.524 (0.060) 45° x 0.432 (0.017) 0.228 ± 0.025 (0.009 ± 0.001) 0 - 7° 0.202 ± 0.102 (0.008 ± 0.004) 0.305 MIN. (0.012) *TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 ± 0.254 (0.205 ± 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.  Solder Reflow Temperature Profile 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. 200 PEAK TEMP. 245°C PEAK TEMP. 240°C 2.5°C ± 0.5°C/SEC. 30 SEC. 160°C 150°C 140°C SOLDERING TIME 200°C 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax 260 +0/-5 °C TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 217 °C RAMP-UP 3 °C/SEC. MAX. 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C Note: Non-halide flux should be used.  PEAK TEMP. 230°C 200 250 Regulatory Information The HCPL-0738 has been approved by the following organizations: CSA Approved under CSA Component Acceptance Notice #5, File CA88324. UL Recognized under UL 1577, component recognition program, File E55361. IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 (Option 060 only) Insulation and Safety Related Specifications (approval pending) Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) L(I01) 4.9 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(I02) 4.8 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 mm Insulation thickness between emitter and detector; also known as distance through insulation. Tracking Resistance (Comparative Tracking Index) CTI ≥ 175 Volts DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Storage Temperature TS –55 125 ˚C Ambient Operating Temperature TA –40 100 ˚C Supply Voltage VDD 0 6.0 Volts Output Voltage VO –0.5 VDD + 0.5 Volts Average Forward Input Current IF — 20 mA Average Output Current IO — 2 mA Lead Solder Temperature 260˚C for 10 seconds, 1.6 mm below seating plane Solder Reflow Temperature Profile Recommended Operating Conditions See Solder Reflow Thermal Profile section Parameter Ambient Operating Temperature Symbol TA Minimum –40 Maximum 100 Units ˚C Supply Voltages VDD 4.5 5.5 V Input Current (ON)  IF 10 16 mA Electrical Specifications Over recommended temperature (TA = –40˚C to +100˚C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25˚C, VDD = +5 V. Parameter Symbol Min. Typ. Max. Input Forward Voltage VF 1.3 1.5 1.8 Units V Test Conditions IF = 12 mA Fig. 1 Input Reverse Breakdown Voltage BVR 5 V IR = 10 µA Logic High Output Voltage VOH 4.0 5 V IF = 0, IO = –20 µA Logic Low Output Voltage VOL 0.01 0.1 V IF = 12 mA, IO = 20 µA Input Threshold Current ITH 4.5 8.2 mA IOL = 20 µA 2 Logic Low Output Supply Current IDDL 10 18.0 mA IF = 12 mA 4 Logic High Output Supply Current IDDH 8 15.0 mA IF = 0 mA 3 Notes Switching Specifications Over recommended temperature (TA = –40˚C to +100˚C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25˚C, VDD = +5 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Notes Propagation Delay Time to Logic Low Output tPHL 20 35 60 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels 5 1 Propagation Delay Time to Logic High Output tPLH 11 20 60 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels 5 1 Pulse Width PW 100 ns Pulse Width Distortion |PWD| 0 15 30 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels 5 2 Propagation Delay Skew tPSK 40 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels 3 Output Rise Time (10% – 90%) tR 20 ns IF = 0 mA, CL = 15 pF CMOS Signal Levels Output Fall Time (90% – 10%) tF 25 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Common Mode Transient Immunity at Logic High Output |CMH| 10 15 kV/µS VCM = 1000 V, TA = 25˚C, IF = 0 mA 4 Common Mode Transient Immunity at Logic Low Output |CML| 10 15 kV/µS VCM = 1000 V, TA = 25˚C, IF = 12 mA 5  Package Characteristics All typicals at TA = 25˚C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation II-O 1 µA 45% RH, t = 5 s VI-O = 3 kV DC, TA = 25˚C Input-Output Momentary Withstand Voltage VISO 3750 V rms RH ≤ 50%, t = 1 min., TA = 25˚C Input-Output Resistance RI-O 1012 Ω VI-O = 500 V DC Input-Output Capacitance Notes: CI-O 0.6 pF f = 1 MHz, TA = 25˚C TA = 25°C 100 IF + VF – 10 1.0 0.1 0.01 0.001 1.1 1.2 1.3 1.4 1.5 1.6 10.0 8 VDD = 5.0 V IOL = 20 µA 7 6 5 Ith1 Ith2 4 3 2 1 0 -40 -20 VF – FORWARD VOLTAGE – V VDD = 5.0 V 11.0 10.8 10.6 Iddl 10.4 10.2 10.0 9.8 9.6 -40 -20 0 20 40 60 80 TA – TEMPERATURE – °C Figure 4. Typical logic low O/P supply current vs. temperature.  40 60 80 100 50 tp – PROPAGATION DELAY – ns IDDL – LOGIC LOW SUPPLY CURRENT – mA 11.2 20 Figure 2. Typical input threshold current vs. temperature. 11.6 11.4 0 TA – TEMPERATURE – °C Figure 1. Typical input diode forward characteristic. 100 45 40 35 Tphl CH 2 Tphl CH 1 30 Tplh CH 2 25 Tplh CH 1 20 15 PWD CH 1 10 5 0 IDDH – LOGIC HIGH OUTPUT SUPPLY CURRENT – mA IF – FORWARD CURRENT – mA 1000 Ith – INPUT THRESHOLD CURRENT – mA 1. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 2.5 V level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the VO signal. 2. PWD is defined as |tPHL - tPLH|. 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. PWD CH 2 VDD = 5.0 V TA = 25 °C 5 6 7 8 9 10 11 12 13 14 IF – PULSE INPUT CURRENT – mA Figure 5. Typical switching speed vs. pulse input current. HCPL-0738 fig 5 9.5 VDD = 5.0 V 9.0 8.5 Iddh 8.0 7.5 7.0 6.5 6.0 -40 -20 0 20 40 60 80 TA – TEMPERATURE – °C Figure 3. Typical logic high O/P supply current vs. temperature. 100 Application Information Bypassing and PC Board Layout The HCPL-0738 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL0738 uses high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. IF1 VDD 8 1 As shown in Figure 6, the only external component required for proper operation is the bypass capacitor. Capacitor values should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. C 2 GND 1 3 IF2 4 XXX YWW GND 1 7 VO 1 6 VO 2 5 GND 2 Figure 6. Recommended printed circuit board layout. Propagation Delay, Pulse-Width Distortion, and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD  can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to con-sider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure 8, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either t PLH or tPHL, and the longest propagation delay, either tPLH or tPHL. Propagation delay skew repre-sents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 7 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 8 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. IF VO 50% DATA INPUTS 2.5 V, CMOS CLOCK tPSK IF The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges. 50% DATA OUTPUTS VO 2.5 V, CMOS tPSK CLOCK tPSK Figure 7. Propagation delay skew waveform. Figure 8. Parallel data transmission example. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. AV02-0878EN January 8, 2008 8