HCPL-090J-500E

Data Sheet HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J High Speed Digital Isolators Description Features The HCPL-90xx and HCPL-09xx CMOS digital isolators feature high speed performance and excellent transient immunity specifications. The symmetric magnetic coupling barrier gives these devices a typical pulse width distortion of 2 ns, a typical propagation delay skew of 4 ns and 100 Mbaud data rate, making them the industry’s fastest digital isolators.  The single channel digital isolators (HCPL-9000/-0900) feature an active-low logic output enable. The dual channel digital isolators are configured as unidirectional (HCPL9030/-0930) and bidirectional (HCPL-9031/-0931), operating in full-duplex mode, making them ideal for digital fieldbus applications.  The quad channel digital isolators are configured as unidirectional (HCPL-900J/-090J), two channels in one direction and two channels in opposite direction (HCPL901J/-091J), and one channel in one direction and three channels in opposite direction (HCPL-902J/-092J). This high channel density makes them ideally suited to isolating data conversion devices, parallel buses, and peripheral interfaces. They are available in 8-pin PDIP, 8-pin Gull Wing, 8-pin SOIC packages, and 16-pin SOIC narrow-body and widebody packages. They are specified over the temperature range of –40°C to +100°C. Broadcom        +3.3V and +5V TTL/CMOS compatible 3 ns max. pulse width distortion 6 ns max. propagation delay skew 15 ns max. propagation delay High speed: 100 MBd 15 kV/µs min. common mode rejection Tri-state output (HCPL-9000/-0900) 2500V RMS isolation UL1577 and IEC 61010-1 approved Applications       Digital fieldbus isolation Multiplexed data transmission Computer peripheral interface High speed digital systems Isolated data interfaces Logic level shifting CAUTION! Take normal static precautions in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this data sheet are not to be used in military or aerospace applications or environments. AV02-0137EN April 16, 2020 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators Selection Guide Device Number Channel Configuration Package HCPL-9000 Single 8-pin DIP (300 Mil) HCPL-0900 Single 8-pin Small Outline HCPL-9030 Dual 8-pin DIP (300 Mil) HCPL-0930 Dual 8-pin Small Outline HCPL-9031 Dual, Bidirectional 8-pin DIP (300 Mil) HCPL-0931 Dual, Bidirectional 8-pin Small Outline HCPL-900J Quad 16-pin Small Outline, Wide Body HCPL-090J Quad 16-pin Small Outline, Narrow Body HCPL-901J Quad, 2/2, Bidirectional 16-pin Small Outline, Wide Body HCPL-091J Quad, 2/2, Bidirectional 16-pin Small Outline, Narrow Body HCPL-902J Quad, 1/3, Bidirectional 16-pin Small Outline, Wide Body HCPL-092J Quad, 1/3, Bidirectional 16-pin Small Outline, Narrow Body Ordering Information HCPL-09xx and HCPL-90xx are UL Recognized with 2500 Vrms for 1 minute per UL1577. Option Part Number RoHS Compliant Package HCPL-9000 HCPL-9030 HCPL-9031 -000E 300 mil DIP-8 HCPL-0900 HCPL-0930 HCPL-0931 -000E HCPL-900J HCPL-901J HCPL-902J -000E HCPL-900J HCPL-901J HCPL-902J -000E -300E -500E SO-8 -500E Gull Wing X X X X Wide Body SO-16 Quantity 50 per tube X X X 1500 per reel 50 per tube X X X 1000 per reel 100 per tube X X Narrow Body SO-16 Tape and Reel 50 per tube X -500E -500E Surface Mount 1000 per reel 50 per tube X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-9031-500E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel in RoHS compliant. Option data sheets are available. Contact your Broadcom sales representative or authorized distributor for information. Broadcom AV02-0137EN 2 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators Pin Descriptions Symbol Description VDD1 Power Supply 1 VDD2 Power Supply 2 INX Logic Input Signal OUTX Logic Output Signal GND1 Power Supply Ground 1 GND2 Power Supply Ground 2 VOE Logic Output Enable (Single Channel), Active Low NC Not Connected Functional Diagrams Truth Table Single Channel IN1 8 1 IN1 2 NC 3 GND1 4 Galvanic Isolation VDD1 VDD2 7 VOE 6 OUT1 5 GND2 VOE OUT1 L L L H L H L H Z H H Z HCPL-9000/0900 1 IN1 2 IN2 3 GND1 4 HCPL-9030/0930 Broadcom 8 VDD2 7 OUT1 6 OUT2 5 GND2 VDD1 1 IN1 2 OUT2 GND1 Galvanic Isolation VDD1 Galvanic Isolation Dual Channel 4 8 VDD2 7 OUT1 6 IN2 5 GND2 HCPL-9031/0931 AV02-0137EN 3 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators Quad Channel VDD2 VDD1 1 16 VDD2 VDD1 1 16 VDD2 GND1 2 15 GND2 GND1 2 15 GND2 GND1 2 15 GND2 IN1 3 14 OUT1 IN1 3 14 OUT1 IN1 3 14 OUT1 IN2 4 13 OUT2 IN2 4 13 OUT2 IN2 4 13 OUT2 IN3 5 12 OUT3 OUT3 5 12 IN3 IN3 5 12 OUT3 IN4 6 11 OUT4 OUT4 6 11 IN4 OUT4 6 11 IN4 NC 7 10 NC NC 7 10 NC NC 7 10 NC GND1 8 9 GND2 GND1 8 9 GND2 GND1 8 9 GND2 HCPL-900J/-090J Galvanic Isolation 16 Galvanic Isolation 1 Galvanic Isolation VDD1 HCPL-902J/-092J HCPL-901J/-091J Package Outline Drawings HCPL-9000, HCPL-9030, and HCPL-9031 Standard DIP Packages 0.28 (7.1) 0.33 (8.4) 0.24 (6.1) 0.27 (6.9) 0.30 (7.6) 0.38 (9.7) 0 10 0.345 (8.76) 0.40 (10.2) 0.055 (1.40) 0.065 (1.65) 0.008 (0.2) 0.015 (0.4) 0.13 (3.30) 0.17 (4.32) NOTE: Pin spacing is a basic dimension; tolerances do not accumulate 0.015 (0.38) 0.040 (1.02) 0.030 (0.76) 0.045 (1.14) 0.09 (2.3) 0.11 (2.8) 0.045 (1.14) 0.070 (1.78) 0.014 (0.36) 0.023 (0.58) Dimensions: inches (mm); scale = approx. 2.5X Broadcom AV02-0137EN 4 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300 PAD LOCATION (for reference only) 0.040 (1.016) 0.047 (1.194) 0.345 (8.76) 0.400 (10.160) 8 7 6 5 0.190 TYP. (4.826) 0.240 (6.096) 0.27 (6.9) 1 2 3 0.370 (9.398) 0.390 (9.906) 4 0.047 (1.194) 0.070 (1.778) 0.045 (1.143) 0.070 (1.78) 0.030 (0.762) 0.045 (1.143) 0.370 (9.400) 0.390 (9.900) 0.290 (7.370) 0.310 (7.870) 0.120 (3.048) 0.150 (3.810) 0.030 (0.760) 0.056 (1.400) 0.09 (2.3) 0.11 (2.8) 0.025 (0.632) 0.035 (0.892) 0.015 (0.385) 0.035 (0.885) 0.015 (0.381) 0.025 (0.635) 0.008 (0.203) 0.015 (0.4) 12° NOM. MIN MAX LEAD COPLANARITY = 0.004 INCHES (0.10 mm) DIMENSIONS INCHES (MILLIMETERS) Broadcom AV02-0137EN 5 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package 0.188 (4.77) 0.197 (5.00) 0.016 (0.4) 0.050 (1.3) 0.052 (1.32) 0.062 (1.57) 0.054 (1.37) 0.072 (1.83) 0.150 (3.8) 0.157 (4.0) 0.228 (5.8) 0.244 (6.2) 0.050 (1.27) NOM 0.013 (0.3) 0.020 (0.5) Dimensions: inches (mm); scale = approx. 5X 0.007 (0.2) 0.013 (0.3) 0.004 (0.1) 0.012 (0.3) NOTE: Pin spacing is a basic dimension; tolerances do not accumulate Pad Layout 0.160 (4.05) 0.050 (1.27) 0.020 (0.51) 8 PLCS 0.275 (6.99) Dimensions: inches (mm); scale = approx. 5X Broadcom AV02-0137EN 6 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package 0.033 (0.85) 0.043 (1.10) 0.260 (6.60) 0.280 (7.11) 0.013 (0.3) 0.020 (0.5) 0.007 (0.2) 0.013 (0.3) 0.397 (10.08) 0.413 (10.49) 0.017 (0.43) 0.022 (0.56) 0.016 (0.4) 0.050 (1.3) 0.007 (0.18) 0.010 (0.25) 0.092 (2.34) 0.105 (2.67) Pin 1 identified by either an indent or a marked dot 0.08 (2.0) 0.10 (2.5) 0.292 (7.42) 0.299 (7.59) 0.004 (0.1) 0.012 (0.3) 0.049 (1.24) 0.051 (1.30) 0.394 (10.00) 0.419 (10.64) NOTE: Pin spacing is a basic dimension; tolerances do not accumulate Dimensions: inches (mm); scale = approx. 5X Pad Layout 0.317 (8.05) 0.050 (1.27) 0.020 (0.51) 16 PLCS 0.449 (11.40) Dimensions: inches (mm); scale = approx. 5X Broadcom AV02-0137EN 7 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package 0.013 (0.3) 0.020 (0.5) NOM 0.007 (0.2) 0.013 (0.3) 0.386 (9.8) 0.394 (10.0) Pin 1 identified by either an indent or a marked dot 0.016 (0.4) 0.050 (1.3) 0.055 (1.40) 0.062 (1.58) 0.054 (1.4) 0.072 (1.8) 0.150 (3.81) 0.157 (3.99) 0.049 (1.24) 0.051 (1.30) 0.228 (5.8) 0.244 (6.2) NOTE: Pin spacing is a basic dimension; tolerances do not accumulate 0.004 (0.1) 0.012 (0.3) Dimensions: inches (mm); scale = approx. 5X Pad Layout 0.160 (4.05) 0.050 (1.27) 0.020 (0.51) 16 PLCS 0.275 (6.99) Dimensions: inches (mm); scale = approx. 5X Broadcom AV02-0137EN 8 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators Package Characteristics Parameter Capacitance (Input-Output)a Symbol Min. Typ. Max. CI-O pF Single Channel — 1.1 — Dual Channel — 2.0 — — 4.0 — Quad Channel Thermal Resistance θJCT 8-Pin PDIP °C/W — 54 8-Pin SOIC — 144 — 16-Pin SOIC Narrow Body — 41 — — 28 — 16-Pin SOIC Wide Body Package Power Dissipation Unit — PPD Test Conditions f = 1 MHz. Thermocouple located at center underside of package. mW 8-Pin PDIP — — 150 8-Pin SOIC — — 150 16-Pin SOIC Narrow Body — — 150 16-Pin SOIC Wide Body — — 150 a. Single and dual channels device are considered two-terminal devices: pins 1 to 4 shorted and pins 5 to 8 shorted. Quad channel devices are considered two-terminal devices: pins 1 to 8 shorted and pins 9 to 16 shorted. Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Insulation and Safety Related Specifications Parameter Condition Min. Typ. Max. Barrier Resistance || Capacitance Ω || pF Single Channel — >1014 || 3 — Dual Channel — >1014 || 3 — Quad Channel — >1014 || 7 — Creepage Distance (External) mm 8-Pin PDIP 7.04 — — 8-Pin SOIC 4.04 — — 16-Pin SOIC Narrow Body 4.03 — — 16-Pin SOIC Wide Body Leakage Current Broadcom Unit 240 Vrms, 60 Hz 8.08 — — — 0.2 — μA AV02-0137EN 9 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators IEC61010-1 Insulation Characteristics Description Symbol HCPL-0900 HCPL-0930 HCPL-090J HCPL-091J HCPL-092J HCPL-9000 HCPL-9030 HCPL-900J HCPL-901J HCPL-902J I – III I – IV Unit Installation classification per DIN VDE 0110/1.89, Table 1 For Rated Mains Voltage ≤ 150 Vrms For Rated Mains Voltage ≤ 300 Vrms I – III Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage VIORM 2 2 150 300 Vrms Soldering Profile The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision). Absolute Maximum Ratings Parameter Symbol Min. Max. Unit TS –55 150 °C TA –55 125 °C VDD1, VDD2 –0.5 7 V Input Voltage VIN –0.5 VDD1 + 0.5 V Voltage Output Enable (HCPL-9000/-0900) VOE –0.5 VDD2 + 0.5 V Output Voltage VOUT –0.5 VDD2 + 0.5 V Output Current Drive IOUT — 10 mA — 260 °C Storage Temperature Ambient Operating Temperature a Supply Voltage Lead Solder Temperature (10s) ESD 2 kV Human Body Model a. Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee performance. Recommended Operating Conditions Parameter Symbol Min. Max. Unit TA –40 100 °C VDD1, VDD2 3.0 5.5 V Logic High Input Voltage VIH 2.4 VDD1 V Logic Low Input Voltage VIL 0 0.8 V tIR, tIF — 1 μs Ambient Operating Temperature Supply Voltage Input Signal Rise and Fall Times Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Broadcom AV02-0137EN 10 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators 3.3V Operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C, VDD1 = VDD2 = +3.3V. Parameter Quiescent Supply Current 1 Symbol Min. Typ. Max. IDD1 HCPL-9000/-0900 — 0.008 0.01 HCPL-9030/-0930 — 0.008 0.01 HCPL-9031/-0931 — 1.5 2.0 HCPL-900J/-090J — 0.018 0.02 HCPL-901J/-091J — 3.3 4.0 — 1.5 2.0 HCPL-902J/-092J Quiescent Supply Current 2 IDD2 HCPL-9000/-0900 — 3.3 4.0 HCPL-9030/-0930 — 3.3 4.0 HCPL-9031/-0931 — 1.5 2.0 HCPL-900J/-090J — 5.5 8.0 HCPL-901J/-091J — 3.3 4.0 HCPL-902J/-092J Logic Input Current Logic High Output Voltage Test Conditions mA VIN = 0V mA VIN = 0V — 3.0 6.0 IIN –10 — 10 µA VOH VDD2 – 0.1 VDD2 — V IOUT = –20 µA, VIN = VIH — V IOUT = –4 mA, VIN = VIH 0.8 * VDD2 VDD2 – 0.5 Logic Low Output Voltage Unit VOL — 0 0.1 V IOUT = 20 µA, VIN = VIL — 0.5 0.8 V IOUT = 4 mA, VIN = VIL Switching Specifications Maximum Data Rate 100 110 — MBd Clock Frequency fmax — — 50 MHz Propagation Delay Time to Logic Low Output tPHL — 12 18 ns Propagation Delay Time to Logic High Output tPLH — 12 18 ns Pulse Width tPW 10 — — ns |PWD| — 2 3 ns tPSK — 4 6 ns Output Rise Time (10% to 90%) tR — 2 4 ns Output Fall Time (10% to 90%) tF — 2 4 ns High to High Impedance tPHZ — 3 5 ns Low to High Impedance tPLZ — 3 5 ns High Impedance to High tPZH — 3 5 ns High Impedance to Low tPZL — 3 5 ns tCSK — 2 3 ns a Pulse Width Distortion |tPHL – tPLH| Propagation Delay Skewb CL = 15 pF Propagation Delay Enable to Output (Single Channel) Channel-to-Channel Skew (Dual and Quad Channels) Broadcom AV02-0137EN 11 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet Parameter Common Mode Transient Immunity (Output Logic High or Logic Low)c High Speed Digital Isolators Symbol Min. Typ. Max. Unit |CMH|, |CML| 15 18 — kV/µs Test Conditions Vcm = 1000V a. PWD is defined as |tPHL – tPLH|. %PWD is equal to the PWD divided by the pulse width. b. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that will be seen between units at 25°C. c. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. 5V Operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5.0V. Parameter Quiescent Supply Current 1 Symbol Min. Typ. Max. IDD1 HCPL-9000/-0900 — 0.012 0.018 HCPL-9030/-0930 — 0.012 0.018 HCPL-9031/-0931 — 2.5 3.0 HCPL-900J/-090J — 0.024 0.036 HCPL-901J/-091J — 5.0 6.0 — 2.5 3.0 HCPL-902J/-092J Quiescent Supply Current 2 IDD2 Unit Test Conditions mA VIN = 0V mA VIN = 0V HCPL-9000/-0900 — 5.0 6.0 HCPL-9030/-0930 — 5.0 6.0 HCPL-9031/-0931 — 2.5 3.0 HCPL-900J/-090J — 8.0 12.0 HCPL-901J/-091J — 5.0 6.0 HCPL-902J/-092J — 6.0 9.0 IIN –10 — 10 µA VOH VDD2 – 0.1 VDD2 — V IOUT = –20 µA, VIN = VIH 0.8 * VDD2 VDD2 – 0.5 — V IOUT = –4 mA, VIN = VIH — 0 0.1 V IOUT = 20 µA, VIN = VIL — 0.5 0.8 V IOUT = 4 mA, VIN = VIL Logic Input Current Logic High Output Voltage Logic Low Output Voltage Broadcom VOL AV02-0137EN 12 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet Parameter High Speed Digital Isolators Symbol Min. Typ. Max. Unit 100 110 — MBd Test Conditions Switching Specifications Maximum Data Rate Clock Frequency fmax — — 50 MHz Propagation Delay Time to Logic Low Output tPHL — 10 15 ns Propagation Delay Time to Logic High Output tPLH — 10 15 ns Pulse Width tPW 10 — — ns |PWD| — 2 3 ns tPSK — 4 6 ns Output Rise Time (10% to 90%) tR — 1 3 ns Output Fall Time (10% to 90%) tF — 1 3 ns High to High Impedance tPHZ — 3 5 ns Low to High Impedance tPLZ — 3 5 ns High Impedance to High tPZH — 3 5 ns High Impedance to Low tPZL — 3 5 ns tCSK — 2 3 ns |CMH|, |CML| 15 18 — kV/µs Pulse Width Distortiona |tPHL – tPLH| Propagation Delay Skewb CL = 15 pF Propagation Delay Enable to Output (Single Channel) Channel-to-Channel Skew (Dual and Quad Channels) Common Mode Transient Immunity (Output Logic High or Logic Low)c Vcm = 1000V a. PWD is defined as |tPHL – tPLH|. %PWD is equal to the PWD divided by the pulse width. b. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that will be seen between units at 25°C. c. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Mixed 5V/3.3V or 3.3V/5V Operation: Electrical Specifications Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25°C, VDD1 = +5.0V, VDD2 = +3.3V. Parameter Quiescent Supply Current 1 Symbol Min. Typ. Max. IDD1 mA HCPL-9000/-0900 — 0.012 0.018 HCPL-9030/-0930 — 0.012 0.018 HCPL-9031/-0931 — 2.5 3.0 HCPL-900J/-090J — 0.024 0.036 HCPL-901J/-091J — 5.0 6.0 HCPL-902J/-092J — 2.5 3.0 Broadcom Unit Test Conditions VIN = 0V AV02-0137EN 13 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet Parameter Quiescent Supply Current 2 High Speed Digital Isolators Symbol Min. Typ. Max. IDD2 Unit mA HCPL-9000/-0900 — 5.0 6.0 HCPL-9030/-0930 — 5.0 6.0 HCPL-9031/-0931 — 2.5 3.0 Test Conditions VIN = 0V HCPL-900J/-090J — 8.0 12.0 HCPL-901J/-091J — 5.0 6.0 HCPL-902J/-092J — 6.0 9.0 IIN –10 — 10 µA VOH VDD2 – 0.1 VDD2 — V IOUT = –20 µA, VIN = VIH 0.8 * VDD2 VDD2 – 0.5 — V IOUT = –4 mA, VIN = VIH — 0 0.1 V IOUT = 20 µA, VIN = VIL — 0.5 0.8 V IOUT = 4 mA, VIN = VIL Logic Input Current Logic High Output Voltage Logic Low Output Voltage VOL Switching Specifications Maximum Data Rate 100 110 — MBd Clock Frequency fmax — — 50 MHz Propagation Delay Time to Logic Low Output tPHL — 12 18 ns Propagation Delay Time to Logic High Output tPLH — 12 18 ns Pulse Width tPW 10 — — ns |PWD| — 2 3 ns tPSK — 4 6 ns Output Rise Time (10% to 90%) tR — 2 4 ns Output Fall Time (10% to 90%) tF — 2 4 ns High to High Impedance tPHZ — 3 5 ns Low to High Impedance tPLZ — 3 5 ns High Impedance to High tPZH — 3 5 ns High Impedance to Low tPZL — 3 5 ns tCSK — 2 3 ns |CMH|, |CML| 15 18 a Pulse Width Distortion |tPHL – tPLH| Propagation Delay Skewb CL = 15 pF Propagation Delay Enable to Output (Single Channel) Channel-to-Channel Skew (Dual and Quad Channels) Common Mode Transient Immunity (Output Logic High or Logic Low)c kV/µs Vcm = 1000V a. PWD is defined as |tPHL – tPLH|. %PWD is equal to the PWD divided by the pulse width. b. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that will be seen between units at 25°C. c. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. Note: This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Broadcom recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Broadcom AV02-0137EN 14 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet Application Information Power Consumption The HCPL-90xx and HCPL-09xx CMOS digital isolators achieves low power consumption from the manner by which they transmit data across isolation barrier. By detecting the edge transitions of the input logic signal and converting this to a narrow current pulse, which drives the isolation barrier, the isolator then latches the input logic state in the output latch. Since the current pulses are narrow, about 2.5 ns wide, the power consumption is independent of mark-tospace ratio and solely dependent on frequency. The approximate power supply current per channel is: I(Input) = 40(f/fmax)(1/4) mA where f = operating frequency, fmax = 50 MHz. High Speed Digital Isolators Bypassing and PC Board Layout The HCPL-90xx and HCPL-09xx digital isolators are extremely easy to use. No external interface circuitry is required because the isolators use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 1, the only external components required for proper operation are low ESR 47 nF ceramic capacitors for decoupling the power supplies. Ground planes for both GND1 and GND2 are highly recommended for data rates above 10 Mb/s. Capacitors must be located as close as possible to the VDD pins. Figure 1: Functional Diagram of Single Channel HCPL-0900 or HCPL-0900 VDD1 To minimize power dissipation, the input signals to the channels of HCPL-90xx and HCPL-09xx digital isolators are differentiated and then latched on the output side of the isolation barrier to reconstruct the signal. This could result in an ambiguous output state depending on power up, shutdown, and power loss sequencing. Therefore, the designer should consider the inclusion of an initialization signal in this start-up circuit. Initialization consists of toggling the input either high then low or low then high. Broadcom IN1 2 NC 3 GND1 HCPL-9000 or HCPL-0900 Signal Status on Start-up and Shut Down VDD2 8 1 C1 4 C2 7 VOE OUT1 6 5 GND2 Note: C1, C2 = 47 nF ceramic capacitors. AV02-0137EN 15 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators Propagation Delay, Pulse Width Distortion and Propagation Delay Skew Propagation Delay is a figure of merit, which describes how quickly a logic signal propagates through a system as illustrated in Figure 2. Figure 2: Timing Diagram to Illustrate Propagation Delay, tPLH and tPHL 5 V CMOS INPUT VIN 50% As illustrated in Figure 3, if the inputs of two or more devices are switched either ON or OFF at the same time, tPSK is the difference between the minimum propagation delay, either tPLH or tPHL, and the maximum propagation delay, either tPLH or tPHL. Figure 3: Timing Diagram to Illustrate Propagation Delay Skew 0V tPLH OUTPUT VOUT propagation delays, either tPLH or tPHL, among two or more channels within a single device (applicable to dual and quad channel devices) that are operating under the same conditions. 90% 10% VIN tPHL 90% 10% VOH 2.5 V CMOS VOL 50% 2.5 V CMOS VOUT tPSK The propagation delay from low to high, tPLH, is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low, tPHL, is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. Pulse Width Distortion, PWD, is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20% to 30% of the minimum pulse width is tolerable. Propagation Delay Skew, tPSK, and Channel-to-Channel Skew, tCSK, are critical parameters to consider in parallel data transmission applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through channels of the digital isolators, differences in propagation delays will cause the data to arrive at the outputs of the digital isolators at different times. If this difference in propagation delay is large enough, it will limit the maximum transmission rate at which parallel data can be sent through the digital isolators. tPSK is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, among two or more devices that are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). tCSK is defined as the difference between the minimum and maximum Broadcom 50% VIN 2.5 V CMOS VOUT As mentioned previously, tPSK, can determine the maximum parallel data transmission rate. Figure 4 shows the timing diagram of a typical parallel data transmission application with both the clock and data lines being sent through the digital isolators. The figure shows data and clock signals at the inputs and outputs of the digital isolators. In this case, the data is clocked off the rising edge of the clock. Figure 4: Parallel Data Transmission DATA INPUTS CLOCK DATA OUTPUTS tPSK CLOCK tPSK AV02-0137EN 16 HCPL-9000/-0900, -9030/-0930, HCPL-9031/-0931, -900J/-090J, HCPL-901J/-091J, -902J/-092J Data Sheet High Speed Digital Isolators Propagation delay skew represents the uncertainty of where an edge might be after being sent through a digital isolator. Figure 4 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap. Otherwise, the clock signal might arrive before all of the data outputs have settled, or some of the data outputs might start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through digital isolators in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. Figure 5 shows the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for HCPL-9000 or HCPL-0900. Figure 5: Timing Diagram to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to Output Waveforms for HCPL9000 or HCPL-0900 50% VIN 90% tPZL 90% tPLZ 50% VOUT tPZH tPW 10% tPHZ 10% tF tR VOE tPW tPLZ tPZH Broadcom Minimum Pulse Width Propagation Delay, Low to High Impedance Propagation Delay, High Impedance to High tPHZ tPZL tR tF Propagation Delay, High to High Impedance Propagation Delay, High Impedance to Low Rise Time Fall Time AV02-0137EN 17 Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries, and/or the EU. Copyright © 2018–2020 Broadcom. All Rights Reserved. The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. 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