HCPL-3120/J312, HCNW3120
2.5 Amp Output Current IGBT Gate Drive Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-3120 contains a GaAsP LED while the HCPLJ312 and the HCNW3120 contain an AlGaAs LED. The LED
is optically coupled to an integrated circuit with a power
output stage. These optocouplers are ideally suited for
driving power IGBTs and MOSFETs used in motor control
inverter applications. The high operating voltage range
of the output stage provides the drive voltages required
by gate controlled devices. The voltage and current
supplied by these optocouplers make them ideally
suited for directly driving IGBTs with ratings up to 1200
V/100 A. For IGBTs with higher ratings, the HCPL-3120
series can be used to drive a discrete power stage which
drives the IGBT gate. The HCNW3120 has the highest insulation voltage of VIORM = 1414 Vpeak in the IEC/EN/DIN
EN 60747-5-5. The HCPL-J312 has an insulation voltage
of VIORM = 1230 Vpeak and the VIORM = 630 Vpeak is also
available with the HCPL-3120 (Option 060).
• 2.5 A maximum peak output current
• 2.0 A minimum peak output current
• 25 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1500 V
• 0.5 V maximum low level output voltage (VOL)
Eliminates need for negative gate drive
• ICC = 5 mA maximum supply current
• Under Voltage Lock-Out protection (UVLO) with
hysteresis
• Wide operating VCC range: 15 to 30 Volts
• 500 ns maximum switching speeds
• Industrial temperature range: ‑40°C to 100°C
• SafetyApproval:
UL Recognized
3750 Vrms for 1 min. for HCPL‑3120/J312
Functional Diagram
5000 Vrms for 1 min. for HCNW3120
HCNW3120
HCPL-3120/J312
N/C 1
8 VCC
N/C 1
8 VCC
CSA Approval
ANODE 2
7 VO
ANODE 2
7 VO
IEC/EN/DIN EN 60747-5-5 Approved:
CATHODE 3
6 VO
CATHODE 3
N/C 4
5 VEE
SHIELD
N/C 4
SHIELD
6 N/C
VIORM = 630 Vpeak for HCPL‑3120 (Option 060)
5 VEE
VIORM = 1230 Vpeak for HCPL‑J312
VIORM = 1414 Vpeak for HCNW3120
TRUTH TABLE
Applications
LED
VCC - VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC - VEE
“NEGATIVE GOING”
(i.e., TURN-OFF)
VO
OFF
0 - 30 V
0 - 30 V
LOW
• Industrial inverters
ON
0 - 11 V
0 - 9.5 V
LOW
• Switch mode power supplies
ON
11 - 13.5 V
9.5 - 12 V
TRANSITION
ON
13.5 - 30 V
12 - 30 V
HIGH
• IGBT/MOSFET gate drive
• AC/Brushless DC motor drives
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
Part Number
HCPL-3120
HCPL-J312
HCNW3120
HCPL-3150*
Output Peak Current ( IO)
2.5 A
2.5 A
2.5 A
0.6 A
IEC/EN/DIN EN
60747-5-5 Approval
VIORM = 630 Vpeak VIORM = 1230 Vpeak VIORM = 1414 Vpeak VIORM = 630 Vpeak
(Option 060)
(Option 060)
* The HCPL-3150 Data sheet available. Contact Avago sales representative or authorized distributor.
Ordering Information
HCPL-3120 and HCPL-J312 are UL recognized with 3750 Vrms for 1 minute per UL1577. HCNW3120 is UL Recognized
with 5000 Vrms for 1 minute per UL1577.
Option
Part
Number
RoHS
Compliant
Non RoHS
Compliant Package
Surface
Mount
-000E
No option
50 per tube
-300E
#300
50 per tube
HCPL-3120
-500E
-060E
X
X
300mil
#500
X
X
X
DIP-8
#060
X
-360E
#360
X
X
X
50 per tube
-560E
#560
X
X
X
1000 per tube
-000E
X
50 per tube
HCPL-J312
-300E
No option
300mil
#300 DIP-8
X
X
X
50 per tube
-500E
#500
X
1000 per reel
-000E
X
42 per tube
HCNW3120
-300E
No option
400mil
#300 DIP-8
X
X
X
42 per tube
-500E
#500
X
750 per reel
X
X
Gull
Wing
X
X
Tape
& Reel
X
X
X
IEC/EN/DIN
EN 60747-5-5
Quantity
1000 per reel
50 per tube
Remarks: The notation ‘#XXX’ is used for older products, while products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE’.
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-3120-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging
with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant.
Example 2:
HCPL-3120 to order product of 300 mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
HCPL-3120 Outline Drawing (Standard DIP Package)
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
Device Part Number
8
Avago
7
•
Lead Free
Pin 1 Dot
6
5
A NNNN Z
YYWW
EEE P
1
2
Date Code
3
6.35 ± 0.25
(0.250 ± 0.010)
Test Rating Code
UL Logo
4
Special Program
Code
Lot ID
1.19 (0.047) MAX.
1.78 (0.070) MAX.
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
0.51 (0.020) MIN.
2.92 (0.115) MIN.
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCPL-3120 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3
2.0 (0.080)
0.635 ± 0.130
(0.025 ± 0.005)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
HCPL-J312 Outline Drawing (Standard DIP Package)
9.80 ± 0.25
(0.386 ± 0.010)
Device Part Number
8
Avago
•
Lead Free
Pin 1 Dot
7
6
A NNNN Z
YYWW
EEE P
1
2
Date Code
7.62 ± 0.25
(0.300 ± 0.010)
5
3
Test Rating Code
6.35 ± 0.25
(0.250 ± 0.010)
UL Logo
4
Special Program
Code
Lot ID
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
HCPL-J312 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.80 ± 0.25
(0.386 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 ± 0.130
(0.025 ± 0.005)
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
4
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
HCNW3120 Outline Drawing (8-Pin Wide Body Package)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
7
8
5
A
NNNNNNNN Z
YYWW
EEE
Device Part
Number
•
Lead Free
Pin 1 Dot
6
1
2
3
9.00 ± 0.15
(0.354 ± 0.006)
Avago
Test Rating
Code
Date Code
Lot ID
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
0.40 (0.016)
0.56 (0.022)
1.78 ± 0.15
(0.070 ± 0.006)
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCNW3120 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
5
13.56
(0.534)
9.00 ± 0.15
(0.354 ± 0.006)
1
2
3
1.3
(0.051)
4
2.29
(0.09)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
2.54
(0.100)
BSC
0.75 ± 0.25
(0.030 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
5
1.00 ± 0.15
(0.039 ± 0.006)
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
7° NOM.
Solder Reflow Temperature Profile
300
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC.
200
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
TEMPERATURE (°C)
2.5 C ± 0.5 °C/SEC.
30
SEC.
160 °C
150 °C
140 °C
PEAK
TEMP.
230 °C
SOLDERING
TIME
200 °C
30
SEC.
3 °C + 1 °C/–0.5 °C
100
PREHEATING TIME
150 °C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
NOTE: NON-HALIDE FLUX SHOULD BE USED.
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
* 260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
15 SEC.
217 °C
150 - 200 °C
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
NOTE: NON-HALIDE FLUX SHOULD BE USED.
* RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE IS 245 °C
6
200
250
Regulatory Information
Agency/Standard
HCPL-3120 HCPL-J312 HCNW3120
Underwriters Laboratory (UL)
Recognized under UL 1577, Component Recognition Program,
Category, File E55361
Compliant
Compliant
Compliant
Canadian Standards Association (CSA) File CA88324,
per Component Acceptance Notice #5
Compliant
Compliant
Compliant
IEC/EN/DIN EN 60747-5-5
Compliant
Option 060
Compliant
Compliant
Insulation and Safety Related Specifications
Parameter
Symbol
HCPL-
3120
Value
HCPL-
J312
HCNW
3120
Units Conditions
Minimum External
L(101)
7.1
7.4
9.6
mm
Air Gap (Clearance)
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
L(102)
7.4
8.0
10.0
mm
Measured from input terminals to output
Tracking (Creepage)
terminals, shortest distance path along
body.
Minimum Internal
0.08
0.5
1.0
mm
Plastic Gap
(Internal Clearance)
Insulation thickness between emitter
and detector; also known as distance
through insulation.
Tracking Resistance
(Comparative
Tracking Index)
DIN IEC 112/VDE 0303 Part 1
CTI
>175
>175
>200
Volts
Isolation Group
IIIa
IIIa
IIIa
Material Group (DIN VDE 0110, 1/89,
Table 1)
7
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the
equipment designer when determining the circuit insulation requirements. However, once mounted on a printed
circuit board, minimum creep-age and clearance requirements must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs which may be used on a printed circuit board
to achieve desired creepage and clearances. Creepage
and clearance distances will also change depending on
factors such as pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics
Description
Symbol
HCPL-3120
Option 060
HCPL-J312
HCNW3120
Unit
Installation classification per DIN VDE 0110/1.89,
Table 1
for rated mains voltage ≤150 V rms
I-IV
I-IV
I-IV
for rated mains voltage ≤300 V rms
I-IV
I-IV
I-IV
for rated mains voltage ≤450 V rms
I-III
I-III
I-IV
for rated mains voltage ≤600 V rms
I-III
I-IV
for rated mains voltage ≤1000 V rms
I-III
Climatic Classification
55/100/21
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
2
2
1230
1414
Maximum Working Insulation Voltage
VIORM 630
Vpeak
Input to Output Test Voltage, Method b*
VPR 1181 1670 2652 Vpeak
VIORM x 1.875 = VPR, 100% Production Test,
tm = 1 sec, Partial Discharge < 5pC
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test,
tm = 10 sec, Partial Discharge < 5pC
VPR
1008 1968 2262 Vpeak
Highest Allowable Overvoltage*
VIOTM 6000 8000
8000 Vpeak
(Transient Overvoltage, tini = 60 sec)
Safety Limiting Values – maximum values allowed
in the event of a failure, also see Figure 37.
Case Temperature
TS 175 175 150 °C
Input Current
IS INPUT 230
400
400
mA
Output Power
PS OUTPUT 600
600
700
mW
Insulation Resistance at TS, VIO = 500 V
RS ≥109 ≥109 ≥109 Ω
*Refer to the IEC/EN/DIN EN 60747-5-5 section (page 1-6/8) of the Isolation Control Component Designer’s Catalog for a detailed description of
Method a/b partial discharge test profiles.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802.
8
Absolute Maximum Ratings
Parameter Symbol
Min.
Storage Temperature
TS
-55 125 °C
Operating Temperature
TA
-40 100 °C
Average Input Current
IF(AVG)
25 mA 1
Peak Transient Input Current
( 5 V
High
HCNW3120
2.3
Threshold Input
Voltage High to
Low
IFLH
VFHL
Input Forward
VF
Voltage
5.0 mA IO = 0 mA,
8.0
0.8 V
1.5
1.8 V
HCPL-J312
HCNW3120
1.6
1.95
Temperature ∆VF/∆TA HCPL-3120
-1.6
Coefficient of
Forward Voltage
HCPL-J312
HCNW3120
-1.3
Input Reverse
HCPL-3120 5
BVR
9, 15,
21
HCPL-3120 1.2
IF = 10 mA
16
mV/°C IF = 10 mA
V
IR = 10 µA
Breakdown HCPL-J312
3 IR = 100 µA
Voltage HCNW3120
Input Capacitance
CIN
HCPL-3120
HCPL-J312
HCNW3120
60
pF
70
f = 1 MHz,
VF = 0 V
UVLO Threshold
VUVLO+
11.0 12.3 13.5 V VO > 5 V,
IF = 10 mA
VUVLO–
UVLO Hysteresis
9.5
UVLOHYS
10.7 12.0
1.6
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
10
22,
34
5
6, 7
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, for HCPL-3120,HCPL-J312 IF(ON) = 7 to 16mA, for
HCNW3120 IF(ON) = 10 to 16mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified.
Parameter Symbol
Min.
Typ.*
Max. Units Test Conditions Fig. Note
Propagation Delay Time
tPLH
0.10
0.30
0.50
µs
to High Output Level
Rg = 10 Ω,
Cg = 10 nF,
10, 11, 16
12, 13,
Propagation Delay Time
tPHL
0.10 0.30 0.50 µs
to Low Output Level
f = 10 kHz,
Duty Cycle = 50%
14, 23
Pulse Width Distortion
PWD
0.3
µs
17
Propagation Delay
Difference Between Any
Two Parts
PDD
(tPHL - tPLH)
0.35
µs
35, 36
12
Rise Time
tr
0.1
µs
23
Fall Time
tf
0.1
µs
UVLO Turn On Delay
tUVLO ON
0.8
µs VO > 5 V, IF = 10 mA
UVLO Turn Off Delay
tUVLO OFF 0.6 VO < 5 V, IF = 10 mA
-0.35
Output High Level Common |CMH|
25 35
kV/µs TA = 25°C,
Mode Transient Immunity IF = 10 to 16 mA,
VCM = 1500 V,
VCC = 30 V
22
24
Output Low Level Common
|CML|
25 35
kV/µs TA = 25°C,
Mode Transient Immunity VCM = 1500 V,
VF = 0 V, VCC = 30 V
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
11
13, 14
13, 15
Package Characteristics
Over recommended temperature (TA = -40 to 100°C) unless otherwise specified.
Parameter
Symbol
Device
Min.
Typ.
Max.
Units Test Conditions
Input-Output Momentary
VISO
HCPL-3120
3750 VRMS
Fig. Note
RH < 50%,
8, 11
Withstand Voltage** HCPL-J312
3750 t = 1 min.,
HCNW3120
5000 TA = 25°C
9, 11
Resistance RI-O HCPL-3120
(Input-Output) HCPL-J312
1012
Ω
HCNW3120 1012 1013
1011
10, 11
VI-O = 500 VDC 11
TA = 25°C
TA = 100°C
Capacitance CI-O
HCPL-3120
0.6
(Input-Output)
HCPL-J312
0.8
HCNW3120
0.5 0.6
pF
f = 1 MHz
LED-to-Case Thermal
qLC
467
°C/W Thermocouple 28
Resistance
located at center
LED-to-Detector Thermal
qLD
442
°C/W
underside of
Resistance package
Detector-to-Case
Thermal Resistance
qDC
126
°C/W
*All typicals at TA = 25°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 2.0 A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 70°C free-air temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 5.4 mW/°C. The maximum LED junction tem-perature should not exceed 125°C.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA).
9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA).
10. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second (leakage detection current limit, II-O ≤ 5 µA).
11. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
12. The difference between tPHL and tPLH between any two HCPL-3120 parts under the same test condition.
13. Pins 1 and 4 need to be connected to LED common.
14. Common mode transient immunity in the high state is the maximum tolerable dVCM /dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15.0 V ).
15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO 5 V
+
–
VCC
VO > 5 V
+ VCC = 15
– to 30 V
1
8
0.1 µF
IF = 7 to 16 mA
+
10 KHz –
500 Ω
50% DUTY
CYCLE
2
+
–
7
IF
VCC = 15
to 30 V
tr
tf
VO
3
6
90%
10 Ω
50%
VOUT
10 nF
4
10%
5
tPLH
tPHL
Figure 23. tPLH, tPHL, tr, and tf test circuit and waveforms.
HCPL-3120 fig 23
VCM
IF
5V
+
–
1
δt
0.1 µF
A
B
δV
8
2
VO
6
4
5
VCC = 30 V
VO
–
Figure 24. CMR test circuit and waveforms.
17
VOH
SWITCH AT A: IF = 10 mA
SWITCH AT B: IF = 0 mA
VCM = 1500 V
∆t
∆t
+
–
VO
+
VCM
0V
7
3
=
VOL
Applications Information
Eliminating Negative IGBT Gate Drive (Discussion applies
to HCPL-3120, HCPL-J312, and HCNW3120)
need for negative IGBT gate drive in many applications
as shown in Figure 25. Care should be taken with such
a PC board design to avoid routing the IGBT collector or
emitter traces close to the HCPL-3120 input as this can
result in unwanted coupling of transient signals into
the HCPL-3120 and degrade performance. (If the IGBT
drain must be routed near the HCPL-3120 input, then
the LED should be reverse-biased when in the off state,
to prevent the transient signals coupled from the IGBT
drain from turning on the HCPL‑3120.)
To keep the IGBT firmly off, the HCPL-3120 has a very
low maximum VOL specification of 0.5 V. The HCPL-3120
realizes this very low VOL by using a DMOS transistor
with 1 Ω (typical) on resistance in its pull down circuit.
When the HCPL-3120 is in the low state, the IGBT gate is
shorted to the emitter by Rg + 1 Ω. Minimizing Rg and
the lead inductance from the HCPL-3120 to the IGBT gate
and emitter (possibly by mounting the HCPL-3120 on a
small PC board directly above the IGBT) can eliminate the
HCPL-3120
+5 V
1
270 Ω
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
0.1 µF
2
7
3
6
4
5
Figure 25. Recommended LED drive and application circuit.
18
8
+
–
VCC = 18 V
+ HVDC
Rg
Q1
3-PHASE
AC
Q2
- HVDC
Selecting the Gate Resistor (Rg) to Minimize IGBT
Switching Losses. (Discussion applies to HCPL-3120,
HCPL-J312 and HCNW3120)
For the circuit in Figure 26 with IF (worst case) =
16 mA, Rg = 8 Ω, Max Duty Cycle = 80%, Qg = 500 nC,
f = 20 kHz and TA max = 85 °C:
Step 1: Calculate Rg Minimum from the IOL Peak Specifica
tion. The IGBT and Rg in Figure 26 can be analyzed as a
PE = 16 mA • 1.8 V • 0.8 = 23 mW
simple RC circuit with a voltage supplied by the HCPL- P = 4.25 mA • 20 V + 5.2 µ J • 20 kHz
O
3120.
= 85 mW + 104 mW
(VCC – VEE - VOL)
Rg
≥
———————
IOLPEAK
= 189 mW > 178 mW (PO(MAX) @ 85°C
(VCC – VEE - 2 V)
= 250 mW-15C*4.8 mW/C)
=
———————
IOLPEAK
The value of 4.25 mA for ICC in the previous equation was
(15 V + 5 V - 2 V)
=
——————— obtained by derating the ICC max of 5 mA (which occurs
2.5 A
at -40°C) to ICC max at 85C (see Figure 7).
= 7.2 Ω @ 8 Ω
The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see
Figure 6). At lower Rg values the voltage supplied by
the HCPL-3120 is not an ideal voltage step. This results
in lower peak currents (more margin) than predicted by
this analysis. When negative gate drive is not used VEE in
the previous equation is equal to zero volts.
Since PO for this case is greater than PO(MAX), Rg must be
increased to reduce the HCPL-3120 power dissipation.
PO(SWITCHING MAX)
= PO(MAX) - PO(BIAS)
= 178 mW - 85 mW
= 93 mW
PO(SWITCHINGMAX)
ESW(MAX)
= ———————
f
Step 2: Check the HCPL-3120 Power Dissipation and
Increase Rg if Necessary. The HCPL-3120 total power
dissipation (PT ) is equal to the sum of the emitter power
(PE) and the output power (PO):
93 mW
= ———— = 4.65 µJ
20 kHz
PT = PE + PO
PE = IF • VF · Duty Cycle
For Qg = 500 nC, from Figure 27, a value of ESW = 4.65 µJ
gives a Rg = 10.3 Ω.
PO = PO(BIAS) + PO (SWITCHING)
= ICC • (VCC - VEE)+ ESW(RG, QG) • f
HCPL-3120
+5 V
1
270 Ω
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
8
0.1 µF
2
7
3
6
+
–
Q1
VEE = -5 V
3-PHASE
AC
5
Q2
Figure 26. HCPL-3120 typical application circuit with negative IGBT gate drive.
19
+ HVDC
Rg
+
–
4
VCC = 15 V
- HVDC
Thermal Model (Discussion applies to HCPL-3120, HCPLJ312 and HCNW3120)
The steady state thermal model for the HCPL-3120 is
shown in Figure 28. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through qCA which
raises the case temperature TC accordingly. The value
of qCA depends on the conditions of the board design
and is, therefore, determined by the designer. The value
of qCA = 83°C/W was obtained from thermal measure
ments using a 2.5 x 2.5 inch PC board, with small traces
(no ground plane), a single HCPL-3120 soldered into the
center of the board and still air. The absolute maximum
power dissipation derating specifica
tions assume a
qCAvalue of 83°C/W.
From the thermal mode in Figure 28 the LED and detector
IC junction temperatures can be expressed as:
PE Parameter Description
IF
LED Current
VF
LED On Voltage
Duty Cycle
Maximum LED Duty Cycle
PO Parameter
Description
ICC
Supply Current
VCC
Positive Supply Voltage
VEE
Negative Supply Voltage
ESW(Rg,Qg)
Energy Dissipated in the HCPL-3120
for each IGBT Switching Cycle
(See Figure 27)
f
Switching Frequency
qLC * qDC
+ PD •(——————— + qCA) + TA
qLC + qDC + qLD
qLC • qDC
TJD = PE (——————— + qCA)
qLC + qDC + qLD
+ PD • (qDC||(qLD + qLC) + qCA) + TA
Inserting the values for qLC and qDC shown in Figure 28
gives:
TJE = PE • (256°C/W + qCA)
+ PD • (57°C/W + qCA) + TA
TJD = PE • (57°C/W + qCA)
+ PD • (111°C/W + qCA) + TA
For example, given PE = 45 mW, PO = 250 mW, TA = 70°C
and qCA = 83°C/W:
TJE = PE • 339°C/W + PD • 140°C/W + TA
= 45 mW • 339°C/W + 250 mW
• 140°C/W + 70°C = 120°C
TJD = PE • 140°C/W + PD • 194°C/W + TA
= 45 mW • 140°C/W + 250 mW • 194°C/W + 70°C = 125°C
TJE and TJD should be limited to 125°C based on the
board layout and part placement (qCA) specific to the application.
20
Esw – ENERGY PER SWITCHING CYCLE – µJ
TJE = PE @ (qLC||(qLD + qDC) + qCA)
14
Qg = 100 nC
Qg = 500 nC
Qg = 1000 nC
12
10
VCC = 19 V
VEE = -9 V
8
6
4
2
0
0
10
20
30
40
50
Rg – GATE RESISTANCE – Ω
Figure 27. Energy dissipated in the HCPL-3120 for each IGBT switching
cycle.
θLD = 442 °C/W
TJE
TJD
θLC = 467 °C/W
θDC = 126 °C/W
TC
θCA = 83 °C/W*
TA
TJE = LED junction temperature
= LED JUNCTION
TEMPERATURE
TJD T=
IC junction
temperature
JE detector
JD = DETECTOR IC JUNCTION TEMPERATURE
TC TT=
case
temperature
measured
at the center of the package bottom
C = CASE TEMPERATURE MEASURED AT THE
CENTER OF THE
PACKAGE
BOTTOM
qLC = LED-to-case
thermal
resistance
= LED-TO-CASE THERMAL RESISTANCE
LC LED-to-detector
qLD θθ=
thermal resistance
LD = LED-TO-DETECTOR THERMAL RESISTANCE
= DETECTOR-TO-CASEthermal
THERMALresistance
RESISTANCE
qDC θ=
DC detector-to-case
= CASE-TO-AMBIENT THERMAL RESISTANCE
CA case-to-ambient
qCA*θ
θ=
thermal
resistance
CA WILL DEPEND ON THE BOARD DESIGN AND
*qCA will
depend
on the
board
THE
PLACEMENT
OF THE
PART.design and the placement of the part.
Figure 28. Thermal model.
LED Drive Circuit Considerations for Ultra High CMR Performance. (Discussion applies to HCPL-3120, HCPL-J312,
and HCNW3120)
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 29. The HCPL-3120
improves CMR perform-ance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 30. This capacitive coupling causes
1
2
CLEDP
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED
in the proper state (on or off ) during common mode
transients. For example, the recommended application
circuit (Figure 25), can achieve 25 kV/µs CMR while minimizing component complexity.
Techniques to keep the LED in the proper state are
discussed in the next two sections.
8
1
7
2
6
3
5
4
CLEDO1
8
CLEDP
7
CLEDO2
3
4
CLEDN
Figure 29. Optocoupler input to output capacitance model for unshielded
optocouplers.
21
CLEDN
SHIELD
6
5
Figure 30. Optocoupler input to output capacitance model for shielded
optocouplers.
CMR with the LED On (CMRH).
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient.
A minimum LED current of 10 mA provides adequate
margin over the maximum IFLH of 5 mA to achieve 25 kV/
µs CMR.
RSAT and VSAT of the logic gate. As long as the low state
voltage developed across the logic gate is less than
VF(OFF), the LED will remain off and no common mode
failure will occur.
The open collector drive circuit, shown in Figure 32,
cannot keep the LED off during a +dVcm/dt transient,
since all the current flowing through CLEDN must be
supplied by the LED, and it is not recommended for
applica-tions requiring ultra high CMRL performance.
Figure 33 is an alternative drive circuit which, like the recommended applica-tion circuit (Figure 25), does achieve
ultra high CMR performance by shunting the LED in the
off state.
CMR with the LED Off (CMRL).
A high CMR LED drive circuit must keep the LED off
(VF ≤ VF(OFF)) during common mode transients. For
example, during a -dVcm/dt transient in Figure 31, the
current flowing through CLEDP also flows through the
+5 V
1
8
2
+
VSAT
–
0.1
µF
CLEDP
7
+
–
VCC = 18 V
1
ILEDP
3
6
CLEDN
4
8
+5 V
5
SHIELD
Rg
•••
CLEDP
2
•••
3
Q1
7
6
CLEDN
ILEDN
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dVCM/dt.
4
5
SHIELD
+ –
VCM
Figure 31. Equivalent circuit for figure 25 during common mode transient.
Figure 32. Not recommended open collector drive circuit.
HCPL-3120 fig 31
HCPL-3120 fig 32
1
8
+5 V
2
3
4
CLEDP
CLEDN
SHIELD
7
6
5
VO – OUTPUT VOLTAGE – V
14
12
(12.3, 10.8)
10
(10.7, 9.2)
8
6
4
2
0
(10.7, 0.1)
0
5
10
(12.3, 0.1)
15
20
(VCC - VEE ) – SUPPLY VOLTAGE – V
Figure 33. Recommended LED drive circuit for ultra-high CMR.
22
Figure 34. Under voltage lock out.
Under Voltage Lockout Feature. (Discussion applies to
HCPL-3120, HCPL-J312, and HCNW3120)
The HCPL-3120 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the HCPL-3120 supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3120 output is in the high
state and the supply voltage drops below the HCPL3120 VUVLO– threshold (9.5
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