HCPL-3120-560E

HCPL-3120/J312, HCNW3120 2.5 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Description Features The HCPL-3120 contains a GaAsP LED while the HCPL-J312 and the HCNW3120 contain an AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 1200 V/100 A. For IGBTs with higher ratings, the HCPL-3120 series can be used to drive a discrete power stage which drives the IGBT gate. The HCNW3120 has the highest insulation voltage of VIORM=1414Vpeak in the IEC/EN/DIN EN 60747-5-5. The HCPL-J312 has an insulation voltage of VIORM = 1230Vpeak and the VIORM = 630Vpeak is also available with the HCPL-3120 (Option 060).           2.5 A maximum peak output current 2.0 A minimum peak output current 25 kV/μs minimum Common Mode Rejection (CMR) at VCM = 1500 V 0.5 V maximum low level output voltage (VOL) Eliminates need for negative gate drive ICC = 5 mA maximum supply current Under Voltage Lock-Out protection (UVLO) with hysteresis Wide operating VCC range: 15 to 30 Volts 500 ns maximum switching speeds Industrial temperature range: –40 °C to 100 °C Safety Approval: UL Recognized — — CAUTION It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 3750 Vrms for 1 min. for HCPL-3120/J312 5000 Vrms for 1 min. for HCNW3120 CSA Approval IEC/EN/DIN EN 60747-5-5 Approved: VIORM= 630 Vpeak for HCPL-3120 (Option 060) VIORM= 1230 Vpeak for HCPL-J312 — VIORM= 1414 Vpeak for HCNW3120 — — Applications     Avago Technologies -1- IGBT/MOSFET gate drive AC/Brushless DC motor drives Industrial inverters Switch mode power supplies HCPL-3120/J312, HCNW3120 Data Sheet Functional Diagram Functional Diagram HCNW3120 HCPL-3120/J312 N/C 1 8 VCC N/C 1 8 VCC ANODE 2 7 VO ANODE 2 7 VO CATHODE 3 6 VO CATHODE 3 N/C 4 SHIELD N/C 4 5 VEE 6 N/C 5 VEE SHIELD Truth Table LED VCC - VEE “POSITIVE GOING” (i.e., TURN-ON) VCC - VEE “NEGATIVE GOING” (i.e., TURN-OFF) V0 OFF 0–30 V 0–30 V LOW ON 0–11 V 0–9.5 V LOW ON 11 –13.5 V 9.5–12 V TRANSITION ON 13.5–30 V 12–30 V HIGH A 0.1 μF bypass capacitor must be connected between pins 5 and 8. Selection Guide Part Number HCPL-3120 HCPL-J312 HCPL-3150a HCNW3120 Output Peak Current (IO) 2.5 A 2.5 A 2.5 A 0.6 A IEC/EN/DIN EN 60747-5-5 Approval VIORM=630 Vpeak (Option 060) VIORM=1230 Vpeak VIORM=1414 Vpeak VIORM=630 Vpeak (Option 060) a. The HCPL-3150 Data sheet available. Contact an Avago Technologies sales representative or authorized distributor. Avago Technologies -2- HCPL-3120/J312, HCNW3120 Data Sheet Ordering Information Ordering Information HCPL-3120 and HCPL-J312 are UL recognized with 3750 Vrms for 1 minute per UL1577. HCNW3120 is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part HCPL-3120 HCPL-J312 HCNW3120 NOTE RoHS Compliant Non RoHS Compliant -000E No option -300E #300 -500E #500 -060E #060 -360E Surface Mount Package 300-mil, DIP-8 X X X #360 X X -560E/PE #560 X X -000E No option -300E #300 -500E #500 -000E No option -300E #300 -500E #500 400-mil, DIP-8 IEC/EN/DIN Number Quantity 50 per tube X 300-mil, DIP-8 Tape and Reel Gull Wing X X X X X X X X 50 per tube X X X X 1000 per reel X 50 per tube X 50 per tube X 1000 per tube X 50 per tube X 50 per tube X 1000 per reel X 42 per tube X 42 per tube X 750 per reel The notation ‘#XXX’ is used for older products, while products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE’. To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-3120-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: HCPL-3120 to order product of 300 mil DIP package in tube packaging and non RoHS compliant. Option data sheets are available. Contact your Avago Technologies sales representative or authorized distributor for information. Avago Technologies -3- HCPL-3120/J312, HCNW3120 Data Sheet Package Outline Drawings Package Outline Drawings HCPL-3120 Outline Drawing (Standard DIP Package) 9.65 ± 0.25 (0.380 ± 0.010) 7.62 ± 0.25 (0.300 ± 0.010) Device Part Number 8 Avago Lead Free Pin 1 Dot • 7 5 A NNNN Z YYWW EEE P 1 Date Code 1.19 (0.047) MAX. 6 2 3 Test Rating Code 6.35 ± 0.25 (0.250 ± 0.010) UL Logo Special Program Code 4 Lot ID 1.78 (0.070) MAX. 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. 2.54 ± 0.25 (0.100 ± 0.010) DIMENSIONS IN MILLIMETERS AND (INCHES). * MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Avago Technologies -4- HCPL-3120/J312, HCNW3120 Data Sheet Package Outline Drawings HCPL-3120 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 9.65 ± 0.25 (0.380 ± 0.010) 8 7 6 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 2.54 (0.100) BSC 2.0 (0.080) 0.635 ± 0.130 (0.025 ± 0.005) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Avago Technologies -5- + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12° NOM. HCPL-3120/J312, HCNW3120 Data Sheet Package Outline Drawings HCPL-J312 Outline Drawing (Standard DIP Package) 9.80 ± 0.25 (0.386 ± 0.010) Device Part Number 8 Avago • Lead Free Pin 1 Dot 7 1 2 3 7.62 ± 0.25 (0.300 ± 0.010) 5 A NNNN Z YYWW EEE P Date Code 1.19 (0.047) MAX. 6 Test Rating Code UL Logo 6.35 ± 0.25 (0.250 ± 0.010) Special Program Code 4 Lot ID 1.78 (0.070) MAX. 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. 2.54 ± 0.25 (0.100 ± 0.010) + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) DIMENSIONS IN MILLIMETERS AND (INCHES). OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Avago Technologies -6- HCPL-3120/J312, HCNW3120 Data Sheet Package Outline Drawings HCPL-J312 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 9.80 ± 0.25 (0.386 ± 0.010) 8 7 6 1.016 (0.040) 5 6.350 ± 0.25 (0.250 ± 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 1.19 (0.047) MAX. 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 2.54 (0.100) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). 2.0 (0.080) 0.635 ± 0.130 (0.025 ± 0.005) NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX. Avago Technologies -7- + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 12° NOM. HCPL-3120/J312, HCNW3120 Data Sheet Package Outline Drawings HCNW3120 Outline Drawing (8-Pin Wide Body Package) 11.00 MAX. (0.433) 11.15 ± 0.15 (0.442 ± 0.006) 7 8 5 A NNNNNNNN Z YYWW EEE Device Part Number • Lead Free Pin 1 Dot 6 9.00 ± 0.15 (0.354 ± 0.006) 1 2 3 Avago Test Rating Code Date Code Lot ID 4 10.16 (0.400) TYP. 1.55 (0.061) MAX. 7° TYP. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 5.10 MAX. (0.201) 3.10 (0.122) 3.90 (0.154) 0.51 (0.021) MIN. 2.54 (0.100) TYP. 1.78 ± 0.15 (0.070 ± 0.006) 0.40 (0.016) 0.56 (0.022) DIMENSIONS IN MILLIMETERS (INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Avago Technologies -8- HCPL-3120/J312, HCNW3120 Data Sheet Package Outline Drawings HCNW3120 Gull Wing Surface Mount Option 300 Outline Drawing LAND PATTERN RECOMMENDATION 11.15 ± 0.15 (0.442 ± 0.006) 8 7 6 5 13.56 (0.534) 9.00 ± 0.15 (0.354 ± 0.006) 1 2 3 1.3 (0.051) 4 2.29 (0.09) 12.30 ± 0.30 (0.484 ± 0.012) 1.55 (0.061) MAX. 11.00 MAX. (0.433) 4.00 MAX. (0.158) 1.78 ± 0.15 (0.070 ± 0.006) 2.54 (0.100) BSC 0.75 ± 0.25 (0.030 ± 0.010) 1.00 ± 0.15 (0.039 ± 0.006) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES). NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. + 0.076 0.254 - 0.0051 + 0.003) (0.010 - 0.002) 7° NOM. Avago Technologies -9- HCPL-3120/J312, HCNW3120 Data Sheet Solder Reflow Temperature Profile Solder Reflow Temperature Profile tp 217 °C TL TEMPERATURE 15 SEC. * 260 +0/-5 °C Tp TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 150 - 200 °C Tsmax RAMP-UP 3 °C/SEC. MAX. RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 60 to 150 SEC. 25 t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C NOTE: NON-HALIDE FLUX SHOULD BE USED. * RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE IS 245 °C Recommended Pb-Free IR Profile 300 PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC. REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC. 200 PEAK TEMP. 245 °C PEAK TEMP. 240 °C TEMPERATURE (°C) 2.5 C ± 0.5 °C/SEC. 30 SEC. 160 °C 150 °C 140 °C PEAK TEMP. 230 °C SOLDERING TIME 200 °C 30 SEC. 3 °C + 1 °C/–0.5 °C 100 PREHEATING TIME 150 °C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 TIME (SECONDS) NOTE: NON-HALIDE FLUX SHOULD BE USED. Avago Technologies - 10 - 200 250 HCPL-3120/J312, HCNW3120 Data Sheet Regulatory Information Regulatory Information Agency/Standard HCPL-3120 HCPL-J312 HCNW3120 Underwriters Laboratory (UL) Recognized under UL 1577, Component Recognition Program, Category, File E55361 Compliant Compliant Compliant Canadian Standards Association (CSA) File CA88324, per Component Acceptance Notice #5 Compliant Compliant Compliant IEC/EN/DIN EN 60747-5-5 Compliant Option 060 Compliant Compliant Insulation and Safety Related Specifications Value Parameter Minimum External Air Gap (Clearance) Symbol Units HCPL-3120 HCPL-J312 Conditions HCNW3120 L(101) 7.1 7.4 9.6 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking L(102) (Creepage) 7.4 8.0 10.0 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.08 0.5 1.0 mm Insulation thickness between emitter and detector; also known as distance through insulation. >175 >175 >200 Volts DIN IEC 112/VDE 0303 Part 1 IIIa IIIa IIIa Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Avago Technologies - 11 - Material Group (DIN VDE 0110, 1/89, Table 1) HCPL-3120/J312, HCNW3120 Data Sheet IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics Description HCPL-3120 Option 060 Symbol HCPL-J312 HCNW3120 Unit Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 V rms for rated mains voltage 300 V rms for rated mains voltage 450 V rms for rated mains voltage 600 V rms for rated mains voltage 1000 V rms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) I-IV I-IV I-III I-IV I-IV I-III I-III I-IV I-IV I-IV I-IV I-III 55/100/21 55/100/21 55/100/21 2 2 2 Maximum Working Insulation Voltage VIORM 630 1230 1414 Vpeak Input to Output Test Voltage, Method ba VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5pC VPR 1181 1670 2652 Vpeak Input to Output Test Voltage, Method aa VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial Discharge < 5pC VPR 1008 1968 2262 Vpeak Highest Allowable Overvoltagea (Transient Overvoltage, tini = 60 sec) VIOTM 6000 8000 8000 Vpeak TS IS INPUT PS OUTPUT 175 230 600 175 400 600 150 400 700 °C mA mW RS ≥109 ≥ 109 ≥ 109  Safety Limiting Values – maximum values allowed in the event of a failure, also see Figure 37. Case Temperature Input Current Output Power Insulation Resistance at TS, VIO = 500 V a. Refer to the IEC/EN/DIN EN 60747-5-5 section (page 1-6/8) of the Isolation Control Component Designer’s Catalog for a detailed description of Method a/b partial discharge test profiles. NOTE These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802. Avago Technologies - 12 - HCPL-3120/J312, HCNW3120 Data Sheet Absolute Maximum Ratings Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current ( 5 V HCNW3120 2.3 V IF = 10 mA 16 mV/°C IF = 10 mA V IR = 10 μA Input Forward Voltage VF 1.8 HCPL-J312 HCNW3120 1.6 1.95 Temperature Coefficient of VF/TA Forward Voltage HCPL-3120 –1.6 HCPL-J312 HCNW3120 –1.3 Input Reverse Breakdown Voltage BVR HCPL-3120 5 HCPL-J312 HCNW3120 3 Input Capacitance CIN UVLO Hysteresis 21 V 1.5 UVLO Threshold , 8.0 0.8 HCPL-3120 Note A VOH VFHL (VCC – 3) Test Conditions High Level Output Voltage Threshold Input Voltage High to Low (VCC – 4) Units 1.2 IR = 100 μA HCPL-3120 60 HCPL-J312 HCNW3120 70 VUVLO+ 11.0 12.3 13.5 VUVLO– 9.5 10.7 12.0 UVLOHYS pF f = 1 MHz, VF = 0 V V VO > 5 V, IF = 10 mA 22, 34 1.6 a. All typical values at TA = 25 °C and VCC – VEE = 30 V, unless otherwise notes. b. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%. c. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on limiting IOH peak. d. In this test, VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. e. Maximum pulse width = 1 ms, maximum duty cycle = 20%. Avago Technologies - 14 - HCPL-3120/J312, HCNW3120 Data Sheet Switching Specifications (AC) Switching Specifications (AC) Over recommended operating conditions (TA = –40 to 100 °C, for HCPL-3120, HCPL-J312 IF(ON) = 7 to 16mA, for HCNW3120 IF(ON) = 10 to 16 mA, VF(OFF) = –3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground) unless otherwise specified. Parameter Symbol Typ.a Min. Max. Units Test Conditions Rg = 10 , Cg = 10 nF, f = 10 kHz, Duty Cycle = 50% Fig. Propagation Delay Time to High Output Level tPLH 0.10 0.30 0.50 μs Propagation Delay Time to Low Output Level tPHL 0.10 0.30 0.50 μs Pulse Width Distortion PWD 0.3 μs Propagation Delay Difference Between Any Two Parts PDD (tPHL – tPLH) 0.35 μs 35, 36 Rise Time tr 0.1 μs 23 Fall Time tf 0.1 μs UVLO Turn On Delay tUVLO ON 0.8 μs UVLO Turn Off Delay tUVLO OFF 0.6 Output High Level Common Mode Transient Immunity |CMH| 25 35 kV/μs TA = 25°C, IF = 10 to 16 mA, VCM = 1500 V, VCC = 30 V Output Low Level Common Mode Transient Immunity |CML| 25 35 kV/μs TA = 25°C, VCM = 1500 V, VF = 0 V, VCC = 30 V –0.35 a. All typical values at TA = 25 °C and VCC – VEE = 30 V, unless otherwise noted. b. This load condition approximates the gate load of a 1200 V/75A IGBT. 10, 11, 12, 13, 14, 23 Note b c VO > 5 V, IF = 10 mA d 22 VO < 5 V, IF = 10 mA 24 e, f e, g c. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device. d. The difference between tPHL and tPLH between any two HCPL-3120 parts under the same test condition. e. Pins 1 and 4 need to be connected to LED common. f. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO>15.0V). g. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO 5 V 3 6 4 5 V OL Figure 22 UVLO Test Circuit 1 7 IF + V CC = 15 – to 30 V 3 8 7 I F = 10 mA VO > 5 V 3 6 4 5 + – V CC Avago Technologies - 20 - + V CC = 15 – to 30 V HCPL-3120/J312, HCNW3120 Data Sheet Package Characteristics Figure 23 tPLH, tPHL, tr, and tf Test Circuit Waveforms 1 8 0.1 μF I F = 7 to 16 mA + 10 KH z – 500 Ω 2 + – 7 IF V CC = 15 to 30 V tr tf VO 50% DUT Y CYCLE 3 6 90% 10 Ω 50% V OUT 10 nF 4 10% 5 tPLH tPHL Figure 24 CMR Test Circuit and Waveforms V CM 1 2 + – VO 3 6 4 5 V CM Δt Δt + – V CC = 30 V V OH VO SWITCH AT A: I F = 10 mA VO SWITCH AT B: + = 0V 7 – 5V δt 0.1 μF A B δV 8 IF V CM = 1500 V Avago Technologies - 21 - V OL I F = 0 mA HCPL-3120/J312, HCNW3120 Data Sheet Application Information Application Information Eliminating Negative IGBT Gate Drive (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) To keep the IGBT firmly off, the HCPL-3120 has a very low maximum VOL specification of 0.5V. The HCPL-3120 realizes this very low VOL by using a DMOS transistor with 1 (typical) on resistance in its pull down circuit. When the HCPL-3120 is in the low state, the IGBT gate is shorted to the emitter by Rg + 1. Minimizing Rg and the lead inductance from the HCPL-3120 to the IGBT gate and emitter (possibly by mounting the HCPL-3120 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3120 input as this can result in unwanted coupling of transient signals into the HCPL-3120 and degrade performance. (If the IGBT drain must be routed near the HCPL-3120 input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3120.) Figure 25 Recommended LED Drive and Application Circuit HCPL-3120 +5 V 1 8 270 W 0.1 μF 2 + – VCC = 18 V + HVDC 7 Rg CONTROL INPUT 74XXX OPEN COLLECTOR 3 6 4 5 Avago Technologies - 22 - Q1 3-PHASE AC Q2 - HVDC HCPL-3120/J312, HCNW3120 Data Sheet Application Information Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) For the circuit in Figure 26 with IF (worst case) = 16mA, Rg = 8 , Max Duty Cycle = 80%, Qg = 500 nC, f=20 kHz and TA max = 85 °C: Step 1: Calculate Rg Minimum from the IOL Peak Specifica­tion. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3120. PE = 16 mA × 1.8 V × 0.8 = 23 mW PO = 4.25 mA × 20 V + 5.2 μJ × 20 kHz = 85 mW + 104 mW = 189 mW > 178 mW (PO(MAX) @ 85 °C = 250 mW-15C*4.8 mW/C) Rg ≥ (VCC – VEE – VOL) / IOLPEAK = (VCC – VEE – 2V) / IOLPEAK = (15V + 5V –2V) / 2.5A The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at – 40 °C) to ICC max at 85C (see Figure 7). = 7.2  ≈ 8  The VOL value of 2V in the previous equation is a conservative value of VOL at the peak current of 2.5A (see Figure 6). At lower Rg values the voltage supplied by the HCPL-3120 is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts. Since PO for this case is greater than PO(MAX), Rg must be increased to reduce the HCPL-3120 power dissipation. PO(SWITCHING MAX) Step 2: Check the HCPL-3120 Power Dissipation and Increase Rg if Necessary. The HCPL-3120 total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO): PT = PE + PO PE = IF × VF × Duty Cycle PO = PO(BIAS) + PO (SWITCHING) = ICC × (VCC – VEE) + ESW(RG, QG) × f = PO(MAX) – PO(BIAS) = 178 mW – 85 mW = 93 mW ESW(MAX) = (PO(SWITCHINGMAX)) / f = 93 mW / 20 kHz = 4.65 μJ For Qg = 500 nC, from Figure 27, a value of ESW = 4.65 μJ gives an Rg = 10.3 . Figure 26 HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive HCPL-3120 +5 V 1 8 270 W 0.1 μF 2 + – VCC = 15 V + HVDC 7 Rg CONTROL INPUT 74XXX OPEN COLLECTOR 3 6 + – 4 Q1 3-PHASE AC Q2 - HVDC VEE = -5 V 5 Avago Technologies - 23 - HCPL-3120/J312, HCNW3120 Data Sheet Application Information Thermal Model (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) The steady state thermal model for the HCPL-3120 is shown in Figure 28. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through CA which raises the case temperature TC accordingly. The value of CA depends on the conditions of the board design and is, therefore, determined by the designer. The value of CA = 83 °C/W was obtained from thermal measurements using a 2.5 × 2.5 inch PC board, with small traces (no ground plane), a single HCPL-3120 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a CAvalue of 83 °C/W. From the thermal mode in Figure 28, the LED and detector IC junction temperatures can be expressed as: TJE = PE ≈ (LC||(LD + DC) + CA) + PD × (((LC × DC) /( LC + DC + LD)) + CA) + TA PE Parameter Description IF LED Current VF LED On Voltage Duty Cycle Maximum LED Duty Cycle PO Parameter Description ICC Supply Current VCC Positive Supply Voltage VEE Negative Supply Voltage ESW(Rg,Qg) Energy Dissipated in the HCPL-3120 for each IGBT Switching Cycle (see Figure 27) f Switching Frequency Figure 27 Energy Dissipated in the HCPL-3120 for Each IGBT Switching Cycle + PD × (DC||(LD + LC) + CA) + TA Inserting the values for LC and DC shown in Figure 28 gives: TJE = PE × (256 °C/W + CA) + PD • (57 °C/W + CA) + TA TJD = PE × (57 °C/W + CA) Esw – ENERGY PER SWITCHING CYCLE – μJ 14 TJD = PE ((LC × DC) /(LC + DC + LD)) + CA Qg = 100 nC Qg = 500 nC Qg = 1000 nC 12 10 VCC = 19 V VEE = -9 V 8 6 4 2 0 0 10 20 30 40 Rg – GATE RESISTANCE – W + PD × (111 °C/W +CA) + TA For example, given PE = 45 mW, PO = 250 mW, TA = 70 °C, and CA= 83 °C/W: TJE = PE × 339 °C/W + PD × 140 °C/W + TA = 45 mW × 339 °C/W + 250 mW × 140 °C/W + 70 °C = 120 °C TJD = PE × 140 °C/W + PD ×194 °C/W + TA = 45 mW × 140 °C/W + 250 mW × 194 °C/W + 70 °C = 125 °C TJE and TJD should be limited to 125 °C based on the board layout and part placement (CA) specific to the application. Avago Technologies - 24 - 50 HCPL-3120/J312, HCNW3120 Data Sheet LED Drive Circuit Considerations for Ultra High CMR Performance Figure 28 Thermal Model TLD = 442 °C/W TJE TJD TLC = 467 °C/W TDC = 126 °C/W TC TCA = 83 °C/W* TA TJE = LED JUNCTION TEMPERATURE TJD = DETECTOR IC JUNCTION TEMPERATURE TC = CASE TEMPERATURE MEASURED AT THE CENTER OF THE PACKAGE BOTTOM TLC = LED-TO-CASE THERMAL RESISTANCE TLD = LED-TO-DETECTOR THERMAL RESISTANCE TDC = DETECTOR-TO-CASE THERMAL RESISTANCE TCA = CASE-TO-AMBIENT THERMAL RESISTANCE *TCA WILL DEPEND ON THE BOARD DESIGN AND THE PLACEMENT OF THE PART. LED Drive Circuit Considerations for Ultra High CMR Performance (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The HCPL-3120 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5–8 as shown in Figure 30. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 25kV/μs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. Figure 29 Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers 1 8 C LEDP 2 3 7 6 C LEDN 4 5 Figure 30 Optocoupler Input to Output Capacitance Model for Shielded Optocouplers 1 C LEDO1 8 C LEDP 2 7 C LEDO2 3 4 C LEDN SHIELD 6 5 Avago Technologies - 25 - HCPL-3120/J312, HCNW3120 Data Sheet CMR with the LED On (CMRH) CMR with the LED On (CMRH) Figure 32 Not Recommended Open Collector Drive Circuit A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 25 kV/μs CMR. 1 8 +5 V C LEDP 2 7 3 6 C LEDN Q1 I LEDN CMR with the LED Off (CMRL) 4 A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a –dVcm/dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. Figure 33 Recommended LED Drive Circuit for Ultra-High CMR 1 8 +5 V The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVcm/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which, like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. Figure 31 Equivalent Circuit for Figure 25 During Common Mode Transient 5 SHIELD C LEDP 2 7 3 6 C LEDN 4 5 SHIELD Figure 34 Under Voltage Lock Out 1 8 0.1 μF C LEDP + V SAT – 2 7 + – V CC = 18 V I LEDP 3 4 •• • 6 C LEDN Rg SHIELD 5 •• • V +5 V 12 V O – OUTPUT VOLTAGE – 14 10 8 6 4 2 0 * THE ARROWS INDICATE THE DIRECTIO N OF CURRENT FLOW DURING –d V CM /dt. (12.3, 10.8) (10.7, 9.2) (10.7, 0.1) 0 5 10 (12.3, 0.1) 15 (V CC - V EE ) – SUPPLY VOLTAGE – + – V CM Avago Technologies - 26 - 20 V HCPL-3120/J312, HCNW3120 Data Sheet Under Voltage Lockout Feature Under Voltage Lockout Feature Figure 36 Waveforms for Dead Time (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3120 supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3120 output is in the high state and the supply voltage drops below the HCPL-3120 VUVLO– threshold (9.5