HCPL-3150 (Single Channel), HCPL-315J (Dual Channel)
0.5 Amp Output Current IGBT Gate Drive Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-315X consists of an LED optically coupled
to an integrated circuit with a power output stage. This
optocoupler is ideally suited for driving power IGBTs and
MOSFETs used in motor control inverter applications.
The high operating voltage range of the output stage
provides the drive voltages required by gate controlled
devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs
with ratings up to 1200 V/50 A. For IGBTs with higher ratings, the HCPL-3150/315J can be used to drive a discrete
power stage which drives the IGBT gate.
• 0.6A maximum peak output current
Applications
• Wide operating VCC range: 15 to 30 volts
• Industrial inverters
• Safety and regulatory approval:
UL recognized (UL1577), 3750 Vrms/1 min.
IEC/EN/DIN EN 60747-5-2 approved
VIORM = 630 Vpeak (HCPL-3150 option 060 only)
VIORM = 891 Vpeak (HCPL-315J) CSA certified
Functional Diagram
8
7
VCC
VO
CATHODE
3
6
VO
N/C
4
5
VEE
SHIELD
HCPL-3150
• Under Voltage Lock-Out protection (UVLO) with
hysteresis
• HCPL-315J: channel one to channel two output
isolation = 1500 Vrms/1 min.
• Uninterruptable Power Supplies (UPS)
2
• ICC = 5 mA maximum supply current
• Industrial temperature range: -40°C to 100°C
• Switch Mode Power Supplies (SMPS)
ANODE
• 1.0 V maximum low level output voltage (VOL)
eliminates need for negative gate drive
• +/– 0.35 µs maximum delay between
devices/channels
• AC and brushless dc motor drives
1
• 15 kV/µs minimum Common Mode Rejection (CMR)
at VCM = 1500 V
• 0.5 µs maximum propagation delay
• Isolated IGBT/MOSFET gate drive
N/C
• 0.5 A minimum peak output current
N/C
1
16 VCC
ANODE
2
15 VO
CATHODE
3
ANODE
6
11 VCC
CATHODE
7
10 VO
N/C
8
SHIELD
SHIELD
14 VEE
9
TRUTH TABLE
VCC - VEE
“Positive Going”
LED
(i.e., Turn-On)
OFF
0 - 30 V
ON
0 - 11 V
ON
11 - 13.5 V
ON
13.5 - 30 V
VCC - VEE
“Negative-Going”
(i.e., Turn-Off)
0 - 30 V
0 - 9.5 V
9.5 - 12 V
12 - 30 V
VEE
HCPL-315J
A 0.1 µF bypass capacitor must be connected between the VCC and VEE pins for each channel.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
VO
LOW
LOW
TRANSITION
HIGH
Selection Guide: Invertor Gate Drive Optoisolators
Package Type
Part Number
Number of
Channels
Widebody
(400 mil)
8-Pin DIP (300 mil)
Small Outline SO-16
HCPL-3150
HCPL-3120
HCPL-J312
HCPL-J314
HCNW-3120
HCPL-315J
HCPL-316J
HCPL-314J
1
1
1
1
1
2
1
2
IEC/EN/DIN EN
60747-5-2
Approvals
VIORM
630 Vpeak
Option 060
VIORM
891Vpeak
VIORM
1414 Vpeak
VIORM
891 Vpeak
UL
Approval
3750
Vrms/1 min.
3750
Vrms/1 min.
5000
Vrms/1min.
3750
Vrms/1 min.
Output Peak
Current
0.5A
2A
CMR
(minimum)
UVLO
2A
0.4A
2A
0.5A
2A
0.4A
15 kV/µs
10 kV/µs
15 kV/µs
10 kV/µs
Yes
No
Yes
No
Fault Status
No
Yes
No
Ordering Information
HCPL-3150 and HCPL-315J are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
HCPL-3150
HCPL-315J
RoHS
Compliant
Non RoHS
Compliant
-000E
No option
-300E
#300
-500E
#500
-060E
#060
-360E
#360
x
x
-560E
#560
x
x
-000E
No option
-500E
#500
Package
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN
EN 60747-5-2
Quantity
50 per tube
300 mil
DIP-8
SO-16
x
x
x
x
50 per tube
x
x
x
x
x
1000 per reel
x
50 per tube
x
50 per tube
x
1000 per reel
x
45 per tube
x
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-3150-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging
with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-3150 to order product of 300 mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE’.
Package Outline Drawings
Standard DIP Package
9.40 (0.370)
9.90 (0.390)
8
7
6
5
OPTION CODE*
A 3150 Z
YYWW
PIN ONE
1
2
3
0.20 (0.008)
0.33 (0.013)
6.10 (0.240)
6.60 (0.260)
DATE CODE
7.36 (0.290)
7.88 (0.310)
5° TYP.
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
DIMENSIONS PIN
IN MILLIMETERS
AND (INCHES).
DIAGRAM
PIN ONE
0.51 (0.020) MIN.
2.92 (0.115) MIN.
0.76 (0.030)
1.40 (0.055)
0.65 (0.025) MAX.
* MARKING1 CODE
VDD1LETTER
VDD2FOR
8 OPTION NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS
AND 500
2 VIN+ 300
VOUT+
7 NOT MARKED.
NOTE: FLOATING
IS 0.25 mm (10 mils) MAX.
3 V LEAD
V PROTRUSION
6
IN–
2.28 (0.090)
2.80 (0.110)
4
OUT–
GND1 GND2 5
Package Outline Drawings
Gull-Wing Surface-Mount Option 300
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
OPTION
CODE*
5
A 3150 Z
6.350 ± 0.25
(0.250 ± 0.010)
YYWW
MOLDED
1
2
3
1.016 (0.040)
10.9 (0.430)
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
2.540
(0.100)
BSC
0.635 ± 0.130
(0.025 ± 0.005)
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
2.0 (0.080)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
*MARKING CODE LETTER FOR OPTION
NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS 300 AND 500 NOT MARKED.
16 - Lead Surface Mount
11 10
9
VO2
VCC2
VO1
10.36 ± 0.20
(0.408 ± 0.008)
GND1
VCC1
16 15 14
GND2
LAND PATTERN RECOMMENDATION
(0.295 ± 0.004)
7.49 ± 0.10
NC
VIN1
V1
VIN2
V2
NC
HCPL-315J
1
2
3
6
7
8
(0.458) 11.63
(0.085) 2.16
(0.025) 0.64
(0.004 – 0.011)
0.10 – 0.30
STANDOFF
VIEW
FROM
PIN 16
0 - 8°
9°
(0.025 MIN.)
0.64
VIEW
FROM
PIN 1
(0.138 ± 0.005)
3.51 ± 0.13
(0.018)
(0.050)
0.457
1.27
(0.406 ± 0.007)
10.31 ± 0.18
(0.345 ± 0.008)
8.76 ± 0.20
(0.0091 – 0.0125)
0.23 – 0.32
(0.408 ± 0.008)
10.36 ± 0.20
ALL LEADS TO BE COPLANAR ± (0.002 INCHES) 0.05 mm.
DIMENSIONS IN (INCHES) AND MILLIMETERS.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Solder Reflow Thermal Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
200
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
SEC.
160°C
150°C
140°C
PEAK
TEMP.
230°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-3150 and HCPL-315J have been approved by the following organizations:
UL
Recognized under UL 1577, Component Recognition
Program, File E55361.
CSA
Approved under CSA Component Acceptance Notice
#5, File CA 88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
(Option 060 and HCPL-315J only)
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Description
Symbol
HCPL-3150#060
HCPL-315J
I - IV
I - III
I - IV
I - IV
I - III
55/100/21
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
2
Maximum Working Insulation Voltage
VIORM
630
891
Vpeak
Vpeak
Installation classification per DIN VDE
0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
Climatic Classification
Unit
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec,
Partial discharge < 5 pC
VPR
1181
1670
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample
Test, tm = 60 sec, VPR
Partial discharge < 5 pC
945
1336
Vpeak
VIOTM
6000
6000
Vpeak
175
IS, INPUT
PS, OUTPUT
175
230
600
°C
400
1200
mA
mW
RS
≥ 109
≥ 109
Ω
Highest Allowable Overvoltage*
(Transient Overvoltage tini = 10 sec)
Safety-Limiting Values – Maximum Values
Allowed in the Event of a Failure, Also
See Figure 37, Thermal Derating Curve.
Case Temperature TS
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Insulation and Safety Related Specifications
Parameter Symbol
HCPL-3150
HCPL-315J
Units
Conditions
Minimum External
Air Gap
(External Clearance)
L(101)
7.1
8.3
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External
Tracking
(External Creepage)
L(102)
7.4
8.3
mm
Measured from input terminals
to output erminals, shortest
distance path along body.
Minimum Internal
Plastic Gap
(Internal Clearance)
0.08
≥0.5
mm
Through insulation distance
conductor to conductor.
CTI
≥175
≥175
Volts
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
Tracking Resistance
(Comparative Tracking
Index)
Isolation Group
Material Group (DIN VDE 0110,
1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
100
°C
Average Input Current
IF(AVG)
25
mA
Peak Transient Input Current
( 5 V
21
VFHL
0.8
V
VF
1.2
1.5
1.8
V
HCPL-3150
IF = 10 mA
16
1.6
1.95
HCPL-315J
∆VF/∆TA
-1.6
Current Low to High
Threshold Input
VF = -3.0 to +0.8 V
9, 15,
Voltage High to Low
Input Forward Voltage
Temperature
mV/°C IF = 10 mA
Coefficient of
Forward Voltage
Input Reverse
BVR
5
V
HCPL-3150
IR = 10 µA
Breakdown Voltage
3
HCPL-315J
IR = 10 µA
Input Capacitance
CIN
70
pF
f = 1 MHz, VF = 0 V
UVLO Threshold
VUVLO+
11.0
12.3
13.5
V
VO > 5 V,
22,
VUVLO-
9.5
10.7
12.0
IF = 10 mA
36
UVLOHYS
1.6
V
UVLO Hysteresis
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Note
6, 7
Switching Specifications (AC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V,
VEE = Ground, each channel) unless otherwise specified.
Parameter
Symbol
Min.
Typ.*
Max.
Units
tPLH
0.10
0.30
0.50
µs
Time to High
Output Level
tPHL
0.10
PWD
Propagation Delay
PDD
Difference Between
(tPHL - tPLH)
Propagation Delay
Propagation Delay
Test Conditions
Fig.
Note
Rg = 47 Ω,
10, 11,
14
Cg = 3 nF,
12, 13,
f = 10 kHz,
14, 23
Duty Cycle = 50%
0.3
0.50
µs
0.3
µs
15
-0.35
0.35
µs
34, 36
10
23
VO > 5 V,
22
Time to Low
Output Level
Pulse Width
Distortion
Any Two Parts
or Channels
Rise Time
t r
0.1
µs
Fall Time
tf
0.1
µs
tUVLO ON
0.8
µs
tUVLO OFF
0.6
µs
IF = 10 mA
TA = 25°C,
UVLO Turn On
Delay
UVLO Turn Off
Delay
Output High Level
IF = 10 mA
VO < 5 V,
|CMH|
15
30
kV/µs
Common Mode
IF = 10 to 16 mA,
Transient
VCM = 1500 V,
Immunity
VCC = 30 V
TA = 25°C,
Output Low Level
|CML|
15
30
kV/µs
Common Mode
VCM = 1500 V,
Transient
VF = 0 V,
Immunity
VCC = 30 V
24
11, 12
11, 13
Package Characteristics (each channel, unless otherwise specified)
Parameter
Symbol
Device
Min.
Typ.*
Max.
Units
Test Conditions
Input-Output
Momentary
Withstand Voltage**
VISO
HCPL-3150
HCPL-315J
3750
3750
Vrms
RH < 50%,
t = 1 min.,
TA = 25°C
8, 9
Output-Output
Momentary
Withstand Voltage**
VO-O
HCPL-315J
1500
Vrms
RH < 50%
t = 1 min.,
TA = 25°C
17
Resistance
(Input - Output)
RI-O
1012
Ω
VI-O = 500 VDC
9
Capacitance CI-O
(Input - Output)
HCPL-3150
HCPL-315J
0.6
1.3
pF
f = 1 MHz
LED-to-Case θLC
Thermal Resistance
HCPL-3150
391
°C/W
28
18
LED-to-Detector
Thermal Resistance
θLD
HCPL-3150
439
°C/W
Detector-to-Case
Thermal Resistance
θDC
HCPL-3150
119
°C/W
Thermocouple
located at center
underside of
package
Fig. Note
*All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
**The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output/output-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 0.5 A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 70°C free-air temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed 125°C.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL1577, each HCPL-3150 optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms (≥ 5000 Vrms for
the HCPL-315J) for 1 second (leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial
discharge (method b) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. The difference between tPHL and tPLH between any two parts or channels under the same test condition.
11. Pins 1 and 4 (HCPL-3150) and pins 3 and 4 (HCPL-315J) need to be connected to LED common.
12. Common mode transient immunity in the high state is the maximum tolerable |dVCM /dt| of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15.0 V ).
13. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO 5 V
+ VCC = 15
– to 30 V
IF = 10 mA
Figure 22. UVLO Test Circuit.
HCPL-3150 fig 22
HCPL-3150 fig 21
13
IOL
VO > 5 V
+
–
VCC
1
8
0.1 µF
IF = 7 to 16 mA
+
10 KHz –
500 Ω
50% DUTY
CYCLE
2
+
–
7
IF
VCC = 15
to 30 V
tr
tf
VO
3
90%
47 Ω
6
50%
VOUT
3 nF
4
10%
5
tPLH
tPHL
Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
VCM
IF
5V
1
0.1 µF
HCPL-3150 fig 23
A
B
+
–
δV
8
2
7
VO
3
6
4
5
δt
=
VCM
∆t
0V
∆t
+
–
VCC = 30 V
VOH
VO
SWITCH AT A: IF = 10 mA
VO
VOL
+
–
SWITCH AT B: IF = 0 mA
VCM = 1500 V
Figure 24. CMR Test Circuit and Waveforms.
Applications Information
HCPL-3150 fig 24
Eliminating Negative IGBT Gate Drive
in many applications as shown in Figure 25. Care should
be taken with such a PC board design to avoid routing
the IGBT collector or emitter traces close to the HCPL3150/315J input as this can result in unwanted coupling
of transient signals into the HCPL-3150/315J and degrade performance. (If the IGBT drain must be routed
near the HCPL-3150/315J input, then the LED should be
reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning
on the HCPL-3150/315J.)
To keep the IGBT firmly off, the HCPL-3150/315J has a
very low maximum VOL specification of 1.0 V. The HCPL3150/315J realizes this very low VOL by using a DMOS
transistor with 4 Ω (typical) on resistance in its pull down
circuit. When the HCPL‑3150/315J is in the low state, the
IGBT gate is shorted to the emitter by Rg + 4 Ω. Minimizing Rg and the lead inductance from the HCPL-3150/315J
to the IGBT gate and emitter (possibly by mounting the
HCPL-3150/315J on a small PC board directly above the
IGBT) can eliminate the need for negative IGBT gate drive
HCPL-3150
+5 V
1
8
270 Ω
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
0.1 µF
2
7
3
6
4
5
Figure 25a. Recommended LED Drive and Application Circuit.
14
HCPL-3150 fig 25
+
–
VCC = 18 V
+ HVDC
Rg
Q1
3-PHASE
AC
Q2
- HVDC
HCPL-315J
+5 V
CONTROL
INPUT
270 Ω
74XX
OPEN
COLLECTOR
1
16
0.1 µF
2
15
3
14
+
–
FLOATING
SUPPLY
VCC = 18 V
Rg
GND 1
+5 V
CONTROL
INPUT
3-PHASE
AC
6
11
270 Ω
74XX
OPEN
COLLECTOR
+ HVDC
0.1 µF
7
10
8
9
+
–
VCC = 18 V
Rg
GND 1
- HVDC
Figure 25b. Recommended LED Drive and Application Circuit (HCPL-315J).
HCPL-3150 fig 25b
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses.
Step 1: Calculate Rg Minimum From the IOL Peak Specification. The
IGBT and Rg in Figure 26 can be analyzed as a simple RC
circuit with a voltage supplied by the HCPL-3150/315J.
(VCC – VEE - VOL)
Rg ≥
IOLPEAK
Step 2: Check the HCPL-3150/315J Power Dissipation and Increase Rg
if Necessary. The HCPL-3150/315J total power dissipation
(PT ) is equal to the sum of the emitter power (PE) and the
output power (PO):
PT = PE + PO
PE = IF • VF • Duty Cycle
(VCC – VEE - 1.7 V)
=
IOLPEAK
PO = PO(BIAS) + PO (SWITCHING)
(15 V + 5 V - 1.7 V)
=
0.6 A
For the circuit in Figure 26 with IF (worst case) = 16 mA,
Rg = 30.5 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20
kHz and TAmax = 90°C:
= 30.5 Ω
The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 0.6 A (see
Figure 6). At lower Rg values the voltage supplied by the
HCPL-3150/315J is not an ideal voltage step. This results
in lower peak currents (more margin) than predicted by
this analysis. When negative gate drive is not used VEE in
the previous equation is equal to zero volts.
15
= ICC•(VCC - VEE) + ESW(RG, QG) •f
PE = 16 mA • 1.8 V • 0.8 = 23 mW
PO = 4.25 mA • 20 V + 4.0 µJ•20 kHz
= 85 mW + 80 mW
= 165 mW > 154 mW (PO(MAX) @ 90°C
= 250 mW−20C• 4.8 mW/C)
HCPL-3150
+5 V
1
8
270 Ω
0.1 µF
CONTROL
INPUT
2
7
3
6
+
–
4
+ HVDC
Rg
Q1
–
+
74XXX
OPEN
COLLECTOR
VCC = 15 V
VEE = -5 V
3-PHASE
AC
5
Q2
- HVDC
Figure 26a. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
HCPL-315J
+5 V
1
CONTROL
INPUT
16
270 Ω
74XX
OPEN
COLLECTOR
HCPL-3150 fig 26
0.1 µF
2
15
3
14
+
–
–
+
VEE = -5 V
6
CONTROL
INPUT
11
270 Ω
74XX
OPEN
COLLECTOR
0.1 µF
7
10
8
9
+
–
3-PHASE
AC
VCC = 15 V
Rg
–
+
VCC = -5 V
GND 1
+ HVDC
Rg
GND 1
+5 V
FLOATING
SUPPLY
VCC = 15 V
- HVDC
Figure 26b. HCPL-315J Typical Application Circuit with Negative IGBT Gate Drive.
HCPL-3150 fig 26b
PE
Parameter
Description
IF
LED Current
VF
LED On Voltage
Duty Cycle
16
Maximum LED
Duty Cycle
PO Parameter
ICC
VCC
VEE
ESW(Rg,Qg)
f
Description
Supply Current
Positive Supply Voltage
Negative Supply Voltage
Energy Dissipated in the HCPL-3150/315J for
each IGBT Switching Cycle (See Figure 27)
Switching Frequency
The value of 4.25 mA for ICC in the previous equation was
obtained by derating the ICC max of 5 mA (which occurs
at -40°C) to ICC max at 90°C (see Figure 7).
From the thermal mode in Figure 28a the LED and detector IC junction temperatures can be expressed as:
Since PO for this case is greater than PO(MAX), Rg must be
increased to reduce the HCPL-3150 power dissipation.
TJE = PE • (θLC||(θLD + θDC) + θCA)
θLC • θDC
+ PD •
+ θCA + TA
θLC + θDC + θLD
(
PO(SWITCHING MAX) = PO(MAX) - PO(BIAS)
(
)
)
= 154 mW - 85 mW
θLC • θDC
TJD = PE
+ θCA
θLC + θDC + θLD
= 69 mW
+ PD• (θDC||(θLD + θLC) + θCA) + TA
PO(SWITCHINGMAX)
ESW(MAX) =
f
Inserting the values for θLC and θDC shown in Figure 28
gives:
69 mW
=
20 kHz
TJE = PE • (230°C/W + θCA) + PD• (49°C/W + θCA) + TA
= 3.45 µJ
TJD = PE • (49°C/W + θCA) + PD• (104°C/W + θCA) + TA
For Qg = 500 nC, from Figure 27, a value of ESW = 3.45 µJ
gives a Rg = 41 Ω.
Thermal Model (HCPL-3150)
TJE = PE• 313°C/W + PD• 132°C/W + TA
The steady state thermal model for the HCPL-3150 is
shown in Figure 28a. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated flows through θCA which
raises the case temperature TC accordingly. The value of
θCA depends on the conditions of the board design and
is, therefore, determined by the designer. The value of
θCA = 83°C/W was obtained from thermal measurements
using a 2.5 x 2.5 inch PC board, with small traces (no
ground plane), a single HCPL-3150 soldered into the
center of the board and still air. The absolute maximum
power dissipation derating specifications assume a
θCAvalue of 83°C/W.
θLD = 439°C/W
TJE
TJD
θLC = 391°C/W
θDC = 119°C/W
TC
θCA = 83°C/W*
TA
= 45 mW• 313°C/W + 250 mW • 132°C/W + 70°C = 117°C
TJD = PE• 132°C/W + PD• 187°C/W + TA
= 45 mW• 132C/W + 250 mW • 187°C/W + 70°C = 123°C
TJE and TJD should be limited to 125°C based on the board
layout and part placement (θCA) specific to the application.
TJE = LED junction temperature
JUNCTION
TEMPERATURE
TTJDJE = = LED
detector
IC junction
temperature
= DETECTOR IC JUNCTION TEMPERATURE
TTTCJD
=
case
temperature
measured
at the center of the package bottom
C = CASE TEMPERATURE MEASURED AT THE
θLC = CENTER
LED-to-case
thermal BOTTOM
resistance
OF THE PACKAGE
THERMAL RESISTANCE
θθθLDLC = == LED-TO-CASE
LED-to-detector
thermal resistance
LD LED-TO-DETECTOR THERMAL RESISTANCE
θDC
= = DETECTOR-TO-CASE
detector-to-caseTHERMAL
thermalRESISTANCE
resistance
θDC
θCA
THERMAL
RESISTANCE
θCA
= = CASE-TO-AMBIENT
case-to-ambient
thermal
resistance
*θ
WILL DEPEND ON THE BOARD DESIGN AND
∗θCACA
will
depend
on the
board
design and the placement of the part.
THE
PLACEMENT
OF THE
PART.
Figure 28a. Thermal Model.
HCPL-3150 fig 28
17
For example, given PE = 45 mW, PO = 250 mW, TA = 70°C
and θCA = 83°C/W:
Thermal Model Dual-Channel (SOIC-16) HCPL-315J Optoisolator
θ1
LED 1
θ3
θ2
Definitions
θ1, θ2, θ3, θ4, θ5, θ6, θ7, θ8, θ9, θ10: Thermal impedances between nodes as shown in Figure 28b. Ambient Temperature: Measured approximately 1.25 cm above the optocoupler with no forced air.
Description
This thermal model assumes that a 16-pin dual-channel
(SOIC-16) optocoupler is soldered into an 8.5 cm x 8.1
cm printed circuit board (PCB). These optocouplers are
hybrid devices with four die: two LEDs and two detectors. The temperature at the LED and the detector of the
optocoupler can be calculated by using the equations
below.
LED 2
θ4
θ5
DETECTOR 1
θ7
DETECTOR 2
θ10
θ8
θ6
θ9
AMBIENT
∆TE1A = A11PE1 + A12PE2+A13PD1+A14PD2
Figure 28b. Thermal Impedance Model for HCPL-315J.
∆TE2A = A21PE1 + A22PE2+A23PD1+A24PD2
HCPL-3150 fig 28b
∆TD1A = A31PE1 + A32PE2+A33PD1+A34PD2
∆TD2A = A41PE1 + A42PE2+A43PD1+A44PD2
where:
∆TE1A = Temperature difference between ambient and LED 1
∆TE2A = Temperature difference between ambient and LED 2
∆TD1A = Temperature difference between ambient and detector 1
∆TD2A = Temperature difference between ambient and detector 2
PE1 = Power dissipation from LED 1;
PE2 = Power dissipation from LED 2;
PD1 = Power dissipation from detector 1;
PD2 = Power dissipation from detector 2
Axy thermal coefficient (units in °C/W) is a function of thermal impedances θ1 through θ10.
PE1
PD1
PE2
PD2
HCPL-3150 fig 28b
Thermal Coefficient Data (units in °C/W)
Part Number
HCPL-315J
A11, A22
198
A12, A21
64
A13, A31
62
A24, A42
64
Note: Maximum junction temperature for above part: 125°C.
18
A14, A41
83
A23, A32
90
A33, A44
137
A34, A43
69
LED Drive Circuit Considerations for Ultra High CMR Performance
Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the
detector IC as shown in Figure 29. The HCPL-3150/315J
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts
the capacitively coupled current away from the sensitive
IC circuitry. How ever, this shield does not eliminate the
capacitive coupling between the LED and optocoupler
pins 5-8 as shown in Figure 30. This capacitive coupling
causes perturbations in the LED current during common
mode transients and becomes the major source of CMR
failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping
the LED in the proper state (on or off ) during common
mode transients. For example, the recommended application circuit (Figure 25), can achieve 15 kV/µs CMR
while minimizing component complexity.
Techniques to keep the LED in the proper state are discussed in the next two sections.
CMR with the LED On (CMRH)
Esw – ENERGY PER SWITCHING CYCLE – µJ
A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so
that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve
15 kV/µs CMR.
7
Qg = 100 nC
6
Qg = 250 nC
Qg = 500 nC
5
VCC = 19 V
VEE = -9 V
4
3
2
1
0
0
20
40
60
80
100
Rg – GATE RESISTANCE – Ω
Figure 27. Energy Dissipated in the HCPL-3150 for Each
IGBT Switching Cycle.
HCPL-3150 fig 27
19
CMR with the LED Off (CMRL)
A high CMR LED drive circuit must keep the LED off
(VF ≤ VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 31, the current
flowing through CLEDP also flows through the RSAT and VSAT
of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will
remain off and no common mode failure will occur.
The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVCM/dt transient, since
all the current flowing through CLEDN must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMRL performance. Figure 33 is an
alternative drive circuit which, like the recommended
application circuit (Figure 25), does achieve ultra high
CMR performance by shunting the LED in the off state.
Under Voltage Lockout Feature
The HCPL-3150/315J contains an under voltage lockout
(UVLO) feature that is designed to protect the IGBT under
fault conditions which cause the HCPL-3150/315J supply
voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in
a low resistance state. When the HCPL-3150/315J output
is in the high state and the supply voltage drops below
the HCPL-3150/315J VUVLO- threshold (9.5
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