HCPL-6651

Data Sheet 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers Description Features These units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either commercial product or with full MILPRF-38534 Class Level H or K testing or from the appropriate DLA Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and Class H and K devices are included in the DLA Qualified Manufacturers List QML-38534 for Hybrid Microcircuits. Quad channel devices are available by special order in the 16-pin DIP through hole packages.  CAUTION! It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.             Dual marked with device part number and DLA Standard Microcircuit Drawing (SMD) Manufactured and tested on a MIL-PRF-38534 Certified Line QML-38534, Class H and K Five hermetically sealed package configurations Performance guaranteed over full military temperature range: –55°C to +125°C High speed: 10 Mbd typical CMR: > 10,000 V/µs typical 1500 Vdc withstand test voltage 2500 Vdc withstand test voltage for HCPL-565x High radiation immunity 6N137, HCPL-2601, HCPL-2630/31 function compatibility Reliability data TTL circuit compatibility Applications           Broadcom Military and aerospace High reliability systems Transportation, medical, and life critical systems Line receiver Voltage level shifting Isolated input line receiver Isolated output line driver Logic ground isolation Harsh industrial environments Isolation for computer, communication, and test equipment systems AV02-1336EN September 16, 2020 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Functional Diagram V CC VE V OUT GND Multiple channel devices available. Truth Table (Positive Logic) Multichannel Devices Input Output On (H) L Off (L) H Single Channel DIP Input Enable Output On (H) H L Off (L) H H On (H) L H Off (L) L H NOTE: Broadcom Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers Each channel contains a GaAsP light emitting diode that is optically coupled to an integrated high speed photon detector. The output of the detector is an open collector Schottky clamped transistor. Internal shields provide a guaranteed common mode transient immunity specification of 1000 V/µs. For Isolation Voltage applications requiring up to 2500 Vdc, the HCPL-5650 family is also available. Package styles for these parts are 8- and 16-pin DIP through hole (case outlines P and E, respectively), and 16-pin surface mount DIP flat pack (case outline F), leadless ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating options. See the Selection Guide table for details. Standard Microcircuit Drawing (SMD) parts are available for each package and lead style. Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to package variations and limitations, and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other parts’ performance for reliability and certain limited radiation test results. The connection of a 0.1-µF bypass capacitor between VCC and GND is recommended. AV02-1336EN 2 Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Selection Guide – Package Styles and Lead Configuration Options Package 16-Pin DIP 8-Pin DIP 8-Pin DIP 8-Pin DIP 16-Pin Flat Pack 20-Pad LCCC Lead Style Through Hole Through Hole Through Hole Through Hole Unformed Leads Surface Mount Channels 2 1 2 2 4 2 Common Channel Wiring VCC, GND None VCC, GND VCC, GND VCC, GND None Withstand Test Voltage 1500 Vdc 1500 Vdc 2500 Vdc 1500 Vdc 1500 Vdc HCPL-5600 HCPL-5630 HCPL-5650 HCPL-6650 HCPL-6630 HCPL-5651 HCPL-6651 HCPL-6631 HCPL-665K HCPL-663K Gold Platea Solder Padsb None 1500 Vdc Broadcom Part Number and Options Commercial 6N134 MIL-PRF-38534, Class H 6N134/883B HCPL-5601 HCPL-5631 MIL-PRF-38534, Class K HCPL-268K HCPL-560K HCPL-563K Standard Lead Finish Gold Platea Gold Platea Gold Platea Gold Platea Solder Dippedb Option #200 Option #200 Option #200 Option #200 Butt Cut/Gold Platea Option #100 Option #100 Option #100 Gull Wing/Solderedb Option #300 Option #300 Option #300 None 5962- None None None Gold Plate 8102801EC 9085501HPC 8102802PC 8102805PC 8102804FC Solder Dippedb 8102801EA 9085501HPA 8102802PA 8102805PA Butt Cut/Gold Platea 8102801UC 9085501HYC 8102802YC 8102801UA 9085501HYA 8102802YA 8102801TA 9085501HXA 8102802ZA Class H SMD Part Number Prescript for all below a Butt Cut/Solderedb Gull Wing/Soldered b 81028032A Class K SMD Part Number Prescript for all below 5962- 5962- 5962- 5962- Gold Platea 9800101KEC 9085501KPC 9800102KPC 9800104KFC Solder Dippedb 9800101KEA 9085501KPA 9800102KPA Butt Cut/Gold Platea 9800101KUC 9085501KYC 9800102KYC Butt Cut/Solderedb 9800101KUA 9085501KYA 9800102KYA Gull Wing/Solderedb 9800101KTA 9085501KXA 9800102KZA 59629800103K2A a. Gold Plate lead finish: Maximum gold thickness of leads is 10000 — 4, 5, 6 c, n ns ns V/µs c 7 c, m, o AV02-1336EN 10 Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Parameter Common Mode Transient Immunity at Low Output Level Symbol |CML| Limits Group Aa Subgroups Test Conditions VCM = 50V (PEAK), 9, 10, 11 VCC = 5V, VO (max.) = 0.8V, RL = 510, IF = 10 mA Min. Typ.b Max. Units 1000 >10000 — V/µs Figure Note 7 c, m, o a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25°, 125°C, and 55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typical values are at VCC = 5V, TA = 25°C. c. Each channel. d. It is essential that a bypass capacitor (0.01-µF to 0.1-µF ceramic) be connected from VCC to ground. Total lead length between both ends of this external capacitor and the isolator connections should not exceed 20 mm. e. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single channel parameter limits for each channel. f. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K, and 5962-9800101 types. g. Required for 6N134, 6N134/883B, 8102801, HCPL-268K, and 5962-9800101 types. h. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all output leads or terminals shorted together. i. This is a momentary withstand test, not an operating condition. j. Not required for HCPL-5650, HCPL-5651, and 8102805 types. k. Required for HCPL-5650, HCPL-5651, and 8102805 types only. l. Measured between each input pair shorted together and all output connections for that channel shorted together. m. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. n. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5V point on the leading edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5V point on the trailing edge of the output pulse. o. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO< 0.8V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0V). Single Channel Product Only Parameter Symbol Test Conditions VCC = 5.5V, VE = 0.5V Group Aa Subgroups Limits Min. Typ.b Max. Units 1, 2, 3 –2.0 –1.45 — mA Low Level Enable Current IEL High Level Enable Voltage VEH 1, 2, 3 2.0 — — V Low Level Enable Voltage VEL 1, 2, 3 — — 0.8 V Figure Note c a. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25°C, 125°C, and 55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typical values are at VCC = 5V, TA = 25°C. c. No external pull up is required for a high logic state on the enable input. Broadcom AV02-1336EN 11 Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Typical Characteristics, TA = 25°C, VCC = 5V Parameter Symbol Typ. Units CIN 60 pF Input Diode Temperature Coefficient VF/TA –1.5 Resistance (Input-Output) RI-O 1012 Input Capacitance Test Conditions Figure Note VF = 0V, f = 1 MHz a mV/°C IF = 20 mA a  VI-O = 500V b a. Each channel. b. All devices are considered two-terminal devices; II-O is measured between all input leads or terminals shorted together and all output leads or terminals shorted together. Single Channel Product Only Parameter Symbol Typ. Units Test Conditions Figure Note Propagation Delay Time of Enable from VEH to VEL tELH 35 ns RL = 510, CL = 50 pF, IF = 13 mA, VEH = 3V, VEL = 0V 8, 9 a, b Propagation Delay Time of Enable from VEL to VEH tEHL 35 ns a, c a. Each channel. b. The tELH enable propagation delay is measured from the 1.5V point on the trailing edge of the enable input pulse to the 1.5V point on the trailing edge of the output pulse. c. The tEHL enable propagation delay is measured from the 1.5V point on the leading edge of the enable input pulse to the 1.5V point on the leading edge of the output pulse. Dual and Quad Channel Product Only Parameter Symbol Typ. Units Test Conditions Figure Note Input-Input Leakage Current II-I 0.5 nA Relative Humidity ≤ 65% VI-I = 500V, t = 5s a Resistance (Input-Input) RI-I 1012  VI-I = 500V a Capacitance (Input-Input) CI-I 0.55 pF f = 1 MHz a a. Measured between adjacent input pairs shorted together for each multichannel device. Broadcom AV02-1336EN 12 Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Figure 1: High Level Output Current vs. Temperature Figure 2: Input-Output Characteristics Figure 4: Test Circuit for tPHL and tPLH Figure 5: Propagation Delay, tPHL and tPLH vs. Pulse Input Current, IFH D.U.T. INPUT MONITORING NODE 5V V CC PULSE GENERATOR Z O = 50: tH = 5 ns Figure 3: Input Diode Forward Characteristics RL IF VO 0.01 μF BYPASS VO C L* GND Rm * C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Broadcom AV02-1336EN 13 Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Figure 6: Propagation Delay vs. Temperature Figure 7: Test Circuit for Common Mode Transient Immunity and Typical Waveforms D.U.T. B II +5 V V CC A 510 : 0.01 μF BYPASS OUTPUT VO MONITORING NODE GND V FF V CM + PULSE GEN. Figure 8: Test Circuit for tEHL and tELH PULSE GENERATOR Z O = 50 : tr = 5 ns Figure 9: Enable Propagation Delay vs. Temperature OUTPUT V E MONITORING NODE +5 V D.U.T. I F = 13 mA V CC VE RL V OUT 0.01 μF BYPASS CL * OUTPUT V O MONITORING NODE GND * C L INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Broadcom AV02-1336EN 14 6N134, 81028, HCPL-563x, HCPL-663x, HCPL-565x, 5962-98001, HCPL-268K, HCPL-665x, 5962-90855, HCPL-560x Data Sheet Hermetically Sealed, High-Speed, High CMR, Logic Gate Optocouplers Figure 10: Operating Circuit for Burn-In and Steady State Life Tests V CC +5.5 V V OC +5.5 V D.U.T.* V CC (EACH INPUT) + V IN 0.01 μF 200 : 5.3 V (EACH OUTPUT) GND 200 : (EACH OUTPUT) CONDITIONS: I F = 20 mA IO = 25 mA T A = +125 oC * ALL CHANNELS TESTED SIMULTANEOUSLY. Broadcom AV02-1336EN 15 Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries, and/or the EU. Copyright © 2012–2020 Broadcom. All Rights Reserved. The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others.