HCPL-7560
Optically Isolated Sigma-Delta (Σ-∆) Modulator
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-7560 Optically Isolated Modulator and HCPL0872 Digital Interface IC or digital filter together form
an isolated programmable two-chip analog-to-digital
converter. The isolated modulator allows direct measurement of motor phase currents in power inverters.
• 8-bit Linearity
In operation, the HCPL-7560 Isolated Modulator (optocoupler with 3750 VRMS dielectric withstand voltage
rating) converts a low-bandwidth analog input into a
high-speed one-bit data stream by means of a SigmaDelta (Σ-∆) over-sampling modulator. This modulation
provides for high noise margins and excellent immunity
against isolation-mode transients. The modulator data
and on-chip sampling clock are encoded and transmitted across the isolation boundary where they are recovered and decoded into separate high-speed clock and
data channels.
• 200 ns Conversion Time
(Pre-Trigger Mode 2 with HCPL-0872)
• 8-bit Effective Resolution with 5µs Signal Delay
(14-bit with 102 µs) (with HCPL-0872)
• Fast 3 µs Over-Range Detection (with HCPL-0872)
• ± 200 mV Input Range with Single 5 V Supply
• 5% Internal Reference Voltage Matching
• Offset Calibration (with HCPL-0872)
• -40°C to +85°C Operating Temperature Range
• 15 kV/µs Isolation Transient Immunity
• Safety Approval: UL 1577, CSA and
IEC/EN/DIN EN 60747-5-2
Applications
• Motor Phase and Rail Current Sensing
• Data Acquisition Systems
• Industrial Process Control
• Inverter Current Sensing
• General Purpose Current Sensing and Monitoring
1
2
Input
Curr ent
3
8
SIGMA-DELTA
MOD./
ENCODE
7
DECODE
4
6
HCPL-0872
or
Digital Filter
MCU
or
DSP
5
HCPL-7560
NOTE: A 0.1 μF bypass capacitor must be connected between pins VDD1 and GND1 and between pins VDD2 and GND2.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
Pin Description
ISOLATION
BOUNDARY
V DD1
1
V IN+
2
V IN-
3
GND1
4
SIGMADELTA
MOD./
ENCODE
Description
VDD1
Supply voltage input (4.5 V to 5.5 V)
8 V DD2
VIN+
Positive input ( ± 200mV recommended)
7 MCLK
VIN-
Negative input (normally connected to GND1)
GND1
Input ground
VDD2
Supply voltage input (4.5 V to 5.5 V)
MCLK
Clock output (10 MHz typical)
MDAT
Serial data output
GND2
Output ground
DECODE
6 MDAT
5 GND2
SHIELD
Symbol
HCPL-7560
Ordering Information
HCPL-7560 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part number
HCPL-7560
RoHS
Compliant
Non-RoHS
Compliant
Package
Surface
Mount
Gull
Wing
-000E
No option
300 mil DIP-8
-300E
-300
X
X
-500E
-500
X
X
-060E
-060
-360E
-360
Tape
& Reel
IEC/EN/DIN EN
60747-5-2
Quantity
50 per tube
X
X
50 per tube
X
1000 per reel
X
50 per tube
X
50 per tube
-560E
-560
X
X
X
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7560-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-7560 to order product of 300 mil DIP-8 package in tube packaging and non-RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawings
8-pin DIP Package
9.80 ± 0.25
(0.386 ± 0.010)
8
7
6
5
OPTION CODE
DATE CODE
A 7560 Z
YYWW
1
2
3
7.62 ± 0.25
(0.300 ± 0.010)
4
6.35 ± 0.25
(0.250 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
5˚ TYP.
0.65 (0.025) MAX.
0.20 (0.008)
0.33 (0.013)
2.54 ± 0.25
(0.100 ± 0.010)
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
DIMENSIONS IN MILLIMETERS AND (INCHES).
NOTE: FLOATING LEAD PROTUSION IS 0.5 mm (20 mils) MAX.
NOTE: INITIAL OR CONTINUED VARIATION IN THE COLOR OF THE HCPL-7560’S WHITE MOLD COMPOUND IS NORMAL AND DOES NOT
AFFECT DEVICE PERFORMANCE OR RELIABILITY.
8-pin Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
9.80 ± 0.25
(0.386 ± 0.010)
8
7
6
1.02 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
MOLDED
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED):
0.51 ± 0.130
(0.020 ± 0.005)
xx.xx = 0.01
xx.xxx = 0.005
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
2.0 (0.080)
0.255 (0.075)
0.010 (0.003)
12˚ NOM.
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
Solder Reflow Temperature Profile
300
PREHEATING RATE 3˚C + 1˚C/-0.5˚C/SEC.
REFLOW HEATING RATE 2.5˚C ± 0.5˚C/SEC.
TEMPERATURE (˚C)
200
PEAK
TEMP.
245˚C
PEAK
TEMP.
240˚C
2.5˚C ± 0.5˚C/SEC.
30
SEC.
160˚C
150˚C
140˚C
SOLDERING
TIME
200˚C
30
SEC.
3˚C + 1˚C/-0.5˚C
100
PREHEATING TIME
150˚C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
Note: Use of non-chlorine-activated fluxes is highly recommended.
Recommended Pb-Free IR Profile
tp
TEMPERATURE (˚C)
Tp
TL
T smax
TIME WITHIN 5˚C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
260 +0/-5˚C
217˚C
RAMP-UP
3˚C/SEC. MAX.
150 - 200 ˚C
RAMP-DOWN
6˚C/SEC. MAX.
T smin
ts
PREHEAT
60 to 180 SEC.
tL
60 to 150 SEC.
25
t 25˚C to PEAK
TIME (SECONDS)
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200˚C, Tsmin = 150˚C
Note: Use of non-chlorine-activated fluxes is highly recommended.
PEAK
TEMP.
230˚C
200
250
Regulatory Information
The HCPL-7560 has been approved by the following organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
UL
Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics[1]
Description
Symbol
HCPL-7560
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
I - IV
I - III
I - II
Climatic Classification
40/85/21
Pollution Degree (DIN VDE 0110/1.89)
2
Unit
Maximum Working Insulation Voltage
VIORM
891
Vpeak
Input to Output Test Voltage, Method b[2]
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
VPR
1670
Vpeak
Input to Output Test Voltage, Method a[2]
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,
Partial discharge < 5 pC
VPR
1336
Vpeak
VIOTM
6000
Vpeak
Safety-limiting values - maximum values allowed in the event of a failure,
also see Figure 13.
Case Temperature
Input Current[3]
Output Power[3]
TS
IS, INPUT
PS, OUTPUT
175
400
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109
W
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec)
Notes:
1. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application. Surface Mount Classifications is Class A in accordance with CECC00802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/
EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.
3. Refer to the following figure for dependence of PS and IS on ambient temperature.
OUTPUT POWER - PS, INPUT CURRENT - IS
800
P S (mW)
700
IS (mA)
600
500
400
300
200
100
0
0
25
50 75 100 125 150 175 200
TA - CASE TEMPERATURE - oC
Insulation and Safety Related Specifications
Parameter
Symbol
HCPL-7560
Units
Conditions
Minimum External Air Gap
(Clearance)
L(101)
7.4
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(102)
8.0
mm
Measured from input terminals to output
terminals, shortest distance path along body.
0.5
mm
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
>175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Ambient Operating Temperature
TA
-40
85
°C
Supply Voltages
VDD1, VDD2
0
5.5
V
Steady-State Input Voltage
VIN+ ,VIN-
-2.0
VDD1 + 0.5
V
VDD2 + 0.5
V
Two Second Transient Input Voltage
Note
1
-6.0
Output Voltages
MCLK, MDAT
-0.5
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Maximum Solder Reflow Thermal Profile section
2
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
-40
+85
°C
Supply Voltages
VDD1, VDD2
4.5
5.5
V
Input Voltage
VIN+, VIN-
-200
+200
mV
Note
1
Electrical Specifications (DC)
Unless otherwise noted, all specifications are at VIN+ = 0 V and VIN- = 0 V, all Typical specifications are at TA = 25°C
and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply over the following ranges: TA = -40°C to
+85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.
Parameter
Symbol
Min.
Typ.
Average Input Bias Current
IIN
-0.8
µA
Average Input Resistance
RIN
450
kW
3
Input DC Common-Mode Rejection
Ratio
CMRRIN
60
dB
4
Output Logic High Voltage
VOH
4.9
V
IOUT = -100 µA
Output Logic Low Voltage
VOL
0.1
V
IOUT = 1.6 mA
Output Short Circuit Current
|IOSC|
30
mA
VOUT = VDD2
or GND2
Input Supply Current
IDD1
10
20
mA
VIN+ = -350 mV
to +350 mV
Output Supply Current
IDD2
10
20
mA
3
Output Clock Frequency
fCLK
10
15
MHz
4
Data Hold Time
tHDDAT
3.9
7.5
Max.
0.6
15
Units
Conditions
Fig.
Note
1
3
5
2
ns
6
Electrical Specifications (Tested with HCPL-0872 or Sinc3 Filter)
Unless otherwise noted, all specifications are at VIN+ = -200 mV to +200 mV and VIN- = 0 V; all Typical
specifications are at TA = 25°C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply
over the following ranges: TA = -40°C to +85°C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
Fig.
Note
STATIC CHARACTERISTICS
Resolution
Integral Nonlinearity
15
INL
bits
7
64
256
LSB
5
8
0.2
0.8
%
6
8
1
LSB
0
6
mV
VIN+ = 0 V
7
35
µV/°C
VIN+ = 0 V
7
VIN+ = 0 V
7
Differential Nonlinearity
DNL
Uncalibrated Input Offset
VOS
Offset Drift vs. Temperature
dVOS/dTA
2
Offset drift vs. VDD1
dVOS/dVDD1
0.12
mV/V
Internal Reference Voltage
VREF
320
mV
8
%
8
Absolute Reference Voltage
Tolerance
-6
-5
5
9
VREF Drift vs. Temperature
dVREF/dTA
150
ppm/°C.
8
VREF Drift vs. VDD1
dVREF/dVDD1
0.2
%
8
Full Scale Input Range
-VREF
+VREF
mV
Recommended Input Voltage
Range
-200
+200
mV
10
11
Dynamic Characteristics (Digital Interface IC HCPL-0872 is set to Conversion Mode 5.)
Parameter
Symbol
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
Min.
Units
Conditions
Fig.
53
dB
9,10
THD
-51
dB
Signal-to-(Noise + Distortion)
SND
50
dB
VIN+ = 35 Hz,
400 mVpk-pk
(141 mVrms)
sine wave.
Effective Number of Bits
ENOB
8
bits
Conversion Time
tC2
0.2
0.8
µs
tC1
5
8
tC0
10
16
Signal Delay
tDSIG
5
Over-Range Detect Time
tOVR1
Threshold Detect Time
(default configuration)
tTHR1
10
µs
Signal Bandwidth
BW
90
kHz
Isolation Transient Immunity
CMR
20
kV/µs
VISO = 1 kV
18
Units
Conditions
Note
Vrms
RH ≤ 50%, t = 1 min;
TA = 25°C
19, 20
2.0
15
Typ.
3.0
Max.
11
12
Pre-Trigger Mode 2
1,12
13
µs
Pre-Trigger Mode 1
1,12
13
µs
Pre-Trigger Mode 0
1,12
µs
4.2
Note
µs
VIN+ = 0 to 400mV
step waveform
13
14
14
15
16
15
17
Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Input-Output Momentary
Withstand Voltage*
VISO
3750
Input-Output Resistance
RI-O
≥109
Ω
VI-O = 500 Vdc
20
Input-Output Capacitance
CI-O
1.4
pF
f = 1 MHz
20
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your
equipment level safety specification, or Avago Technologies Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an
internal optical-coupling test mode may be activated. This test
mode is not intended for customer use.
2. Avago Technologies recommends the use of non-chlorinated solder fluxes.
3. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
4. CMRRIN is defined as the ratio of the gain for differential inputs applied between VIN+ and VIN- to the gain for common-mode inputs
applied to both VIN+ and VIN- with respect to input ground GND1.
5. Short-circuit current is the amount of output current generated
when either output is shorted to VDD2 or GND2. Use under these
conditions is not recommended.
6. Data hold time is amount of time that the data output MDAT will
stay stable following the rising edge of output clock MCLK.
7. Resolution is defined as the total number of output bits. The useable accuracy of any A/D converter is a function of its linearity and
signal-to-noise ratio, rather than how many total bits it has.
8. Integral nonlinearity is defined as one-half the peak-to-peak
deviation of the best-fit line through the transfer curve for VIN+ =
-200 mV to +200 mV, expressed either as the number of LSBs or as
a percent of measured input range (400 mV).
9. Differential nonlinearity is defined as the deviation of the actual
difference from the ideal difference between midpoints of successive output codes, expressed in LSBs.
10. Data sheet value is the average magnitude of the difference in offset voltage from TA =25°C to TA= 85°C, expressed in microvolts per
°C. Three standard deviation from typical value is less than 6mV/°C.
11. Beyond the full-scale input range the output is either all zeroes or
all ones.
12. The effective number of bits (or effective resolution) is defined by
the equation ENOB = (SNR-1.76)/6.02 and represents the resolution of an ideal, quantization-noise limited A/D converter with the
same SNR.
13. Conversion time is defined as the time from when the convert
start signal CS is brought low to when SDAT goes high, indicating
that output data is ready to be clocked out. This can be as small
as a few cycles of the isolated modulator clock and is determined
by the frequency of the isolated modulator clock and the selected
Conversion and Pre-Trigger modes. For determining the true
signal delay characteristics of the A/D converter for closed-loop
phase margin calculations, the signal delay specification should
be used.
14. Signal delay is defined as the effective delay of the input signal
through the Isolated A/D converter. It can be measured by applying a -200 mV to ± 200 mV step at the input of modulator and
adjusting the relative delay of the convert start signal CS so that
the output of the converter is at mid scale. The signal delay is the
elapsed time from when the step signal is applied at the input
to when output data is ready at the end of the conversion cycle.
The signal delay is the most important specification for determining the true signal delay characteristics of the A/D converter and
should be used for determining phase margins in closed-loop
applications. The signal delay is determined by the frequency of
the modulator clock and which Conversion Mode is selected, and
is independent of the selected Pre-Trigger Mode and, therefore,
conversion time.
15. The minimum and maximum overrange detection time is determined by the frequency of the channel 1 isolated modulator clock.
16. The minimum and maximum threshold detection time is determined by the user-defined configuration of the adjustable threshold detection circuit and the frequency of the channel 1 isolated
modulator clock. See the Applications Information section for further detail. The specified times apply for the default configuration.
17. The signal bandwidth is the frequency at which the magnitude
of the output signal has decreased 3 dB below its low-frequency
value. The signal bandwidth is determined by the frequency of the
modulator clock and the selected Conversion Mode.
18. The isolation transient immunity (also known as Common-Mode
Rejection) specifies the minimum rate-of-rise of an isolation-mode
signal applied across the isolation boundary beyond which the
modulator clock or data signals are corrupted.
19. In accordance with UL1577, for devices with minimum VISO specified at 3750 Vrms, each isolated modulator (optocoupler) is prooftested by applying an insulation test voltage greater than 4500
Vrms for one second (leakage current detection limit II-O< 5mA).
This test is performed before the Method b, 100% production test
for partial discharge shown in IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table.
20. This is a two-terminal measurement: pins 1-4 are shorted together
and pins 5-8 are shorted together.
10.5
1
-1
9.4
-40 oC
25 oC
85 oC
0
10.0
9.2
9.0
-2
-4
-5
9.5
IDD2 - mA
IDD1 - mA
IIN - mA
-3
9.0
-6
-4
-2
0
2
4
8.0
-400
6
-200
V IN - V
200
0
8.0
-400
400
0
-200
V IN - mV
Figure 1. IIN vs. VIN.
Figure 3. IDD2 vs. VIN.
7
V DD1 = 4.5 V
V DD1 = 5.0 V
V DD1 = 5.5 V
6
9.6
INL-LSB
9.4
9.2
0.02
V DD1 = 4.5 V
V DD1 = 5.0 V
V DD1 = 5.5 V
V DD1 = 4.5 V
V DD1 = 5.0 V
V DD1 = 5.5 V
0.018
0.016
5
INL-%
10.0
400
200
V IN - mV
Figure 2. IDD1 vs. VIN.
9.8
-40 oC
25 oC
85 oC
8.2
-8
CLOCK FREQUENCY - MHz
8.6
8.4
8.5
-7
-9
-6
8.8
4
9.0
0.014
0.012
0.01
3
8.8
0.008
-15
10
35
60
2
-40
85
Figure 4. Clock Frequency vs. Temperature.
100
0.6
50
0.4
V REF CHANGE - %
OFFSET CHANGE - µV
0.006
-40
85
-50
V DD1 = 4.5 V
V DD1 = 5.0 V
V DD1 = 5.5 V
-15
10
60
TEMPERATURE - ˚C
Figure 7. Offset Change vs. Temperature
85
10
35
85
60
Figure 6. INL (%) vs. Temperature
68
V DD1 = 4.5 V
V DD1 = 5.0 V
V DD1 = 5.5 V
67
66
65
0.2
0
-0.4
-40
64
63
-0.2
35
-15
TEMPERATURE - ˚C
0.8
0
10
60
35
Figure 5. INL (Bits) vs. Temperature
150
-150
-40
10
TEMPERATURE - C
TEMPERATURE - C
-100
-15
o
o
SNR
8.6
-40
62
-15
10
35
60
TEMPERATURE - ˚C
Figure 8. VREF Change vs. Temperature
85
61
-40
V DD1 = 4.5 V
V DD1 = 5.0 V
V DD1 = 5.5 V
-15
10
35
60
TEMPERATURE - ˚C
Figure 9. SNR vs. Temperature
85
80
70
SNR
65
60
55
50
1
2
3
4
5
CONVERSION MODE #
Figure 10. SNR vs. Conversion Mode.
160
12
11
10
9
1
2
3
4
CONVERSION MODE #
Figure 11. Effective Resolution vs. Conversion
Mode.
100
80
60
40
0
1
4
2
3
CONVERSION MODE #
5
Figure 12. Conversion Time vs. Conversion Mode.
100
V IN+ (200 mV/DIV.)
70
OVR1 (200 mV/DIV.)
60
50
THR1
(2 V/DIV.)
40
30
20
10
1
2
3
4
CONVERSION MODE #
Figure 13. Signal Delay vs. Conversion Mode.
5
SIGNAL BANDWIDTH - kHz
90
80
SIGNAL DELAY - µs
120
5
90
11
140
20
8
100
0
PRE-TRIGGER
MODE 0
PRE-TRIGGER
MODE 1
PRE-TRIGGER
MODE 2
180
13
CONVERSION TIME - µs
EFFECTIVE RESOLUTION (# BITS)
75
45
200
14
80
70
60
50
40
30
20
10
0
2 µs/DIV.
Figure 14. Over-Range and Threshold Detect
Times.
1
4
2
3
CONVERSION MODE #
Figure 15. Signal Bandwidth vs. Conversion
Mode.
5
Applications Information
Digital Current Sensing
As shown in Figure 16, using the Isolated 2-chip A/D
converter to sense current can be as simple as connecting a current-sensing resistor, or shunt, to the input and
reading output data through the 3-wire serial output
interface. By choosing the appropriate shunt resistance,
any range of current can be monitored, from less than 1
A to more than 100 A.
Even better performance can be achieved by fully utilizing the more advanced features of the Isolated A/D converter, such as the pre-trigger circuit, which can reduce
conversion time to less than 1ms, the fast over-range
detector for quickly detecting short circuits, different
conversion modes giving various resolution/speed
trade-offs, offset calibration mode to eliminate initial
offset from measurements, and an adjustable threshold
detector for detecting non-short circuit overload conditions.
NON-ISOLATED
+5V
ISOLATED
+5V
INPUT
CURRENT
+
R SHUNT
0.02
C1
0.1 µF
CCLK
V DD1
V DD2
V IN+
MCLK
V IN-
MDAT
GND1
GND2
HCPL-7560
C2
0.1 µF
CLAT
V DD
CHAN
CDAT
SCLK
MCLK1
SDAT
MDAT1
CS
MCLK2
THR1
MDAT2
OVR1
GND
RESET
HCPL-0872
Figure 16. Typical Application Circuit.
12
3-WIRE
SERIAL
INTERFACE
+
C3
10 µF
Product Description
The HCPL-7560 Isolated Modulator (optocoupler) uses
sigma-delta modulation to convert an analog input
signal into a high-speed (10 MHz) single-bit digital data
stream; the time average of the modulator’s single-bit
data is directly proportional to the input signal. The
isolated modulator’s other main function is to provide
galvanic isolation between the analog input and the
digital output. An internal voltage reference determines
the full-scale analog input range of the modulator (approximately ± 320 mV); an input range of ± 200 mV is
recommended to achieve optimal performance.
HCPL-7560 can be used together with HCPL-0872,
Digital Interface IC or a digital filter. The primary functions of the HCPL-0872 Digital Interface IC are to derive
a multi-bit output signal by averaging the single-bit
modulator data, as well as to provide a direct microcontroller interface. The effective resolution of the
multi-bit output signal is a function of the length of
time (measured in modulator clock cycles) over which
the average is taken; averaging over longer periods of
time results in higher resolution. The Digital Interface
IC can be configured for five conversion modes, which
have different combinations of speed and resolution
to achieve the desired level of performance. Other
functions of the HCPL-0872 Digital Interface IC include
a Phase Locked Loop based pre-trigger circuit that
can either give more precise control of the effective
sampling time or reduce conversion time to less than
1µs, a fast over-range detection circuit that rapidly indicates when the magnitude of the input signal is beyond
full-scale, an adjustable threshold detection circuit
that indicates when the magnitude of the input signal
is above a user adjustable threshold level, an offset
calibration circuit, and a second multiplexed input that
allows a second Isolated Modulator to be used with a
single Digital Interface IC.
The digital output format of the Isolated A/D Converter
is 15 bits of unsigned binary data. The input full-scale
range and code assignment is shown in Table 1 below.
Although the output contains 15 bits of data, the effective resolution is lower and is determined by selected
conversion mode as shown in Table 2 below.
Table 1. Input Full-Scale Range and Code Assignment.
Analog Input
Voltage Input
Digital Output
Full Scale Range
640 mV
32768 LSBs
Minimum Step Size
20 µV
1 LSB
+Full Scale
+320 mV
111111111111111
Zero
0 mV
100000000000000
-Full Scale
-320 mV
000000000000000
Table 2. Isolated A/D Converter Typical Performance Characteristics.
Conversion
Mode
Signal-to-Noise
Ratio (dB)
Effective
Resolution
(bits)
1
83
2
Conversion Time (µs)
Pre-Trigger Mode
Signal
Delay(µs)
Signal Bandwidth
(kHz)
102
102
3.4
103
51
51
6.9
11.9
39
19
19
22
66
10.7
20
10
10
45
53
8.5
10
5
5
90
0
1
13.5
205
79
12.8
3
73
4
5
Notes: Bold italic type indicates Default values.
13
2
0.2
Power Supplies and Bypassing
The recommended application circuit is shown in
Figure 17. A floating power supply (which in many applications could be the same supply that is used to
drive the high-side power transistor) is regulated to 5
V using a simple zener diode (D1); the value of resistor
R1 should be chosen to supply sufficient current from
the existing floating supply. The voltage from the current sensing resistor or shunt (Rsense) is applied to the
input of the HCPL-7560 (U2) through an RC anti-aliasing
filter (R2 and C2). And finally, the output clock and data
of the isolated modulator are connected to the digital
interface IC. Although the application circuit is relatively
simple, a few recommendations should be followed to
ensure optimal performance.
The power supply for the isolated modulator is most
often obtained from the same supply used to power the
power transistor gate drive circuit. If a dedicated supply
is required, in many cases it is possible to add an additional winding on an existing transformer. Otherwise,
some sort of simple isolated supply can be used, such
as a line powered transformer or a high-frequency DCDC converter.
An inexpensive 78L05 three-terminal regulator can also
be used to reduce the floating supply voltage to 5 V. To
help attenuate high-frequency power supply noise or
ripple, a resistor or inductor can be used in series with
the input of the regulator to form a low-pass filter with
the regulator’s input bypass capacitor.
As shown in Figure 17, 0.1µF bypass capacitors (C1 and
C3) should be located as close as possible to the input
and output power-supply pins of the isolated modulator (U2). The bypass capacitors are required because of
the high-speed digital nature of the signals inside the
isolated modulator. A 0.01µF bypass capacitor (C2) is
also recommended at the input due to the switchedcapacitor nature of the input circuit. The input bypass
capacitor also forms part of the anti-aliasing filter, which
is recommended to prevent high-frequency noise from
aliasing down to lower frequencies and interfering with
the input signal.
FLOATING
POSITIVE
SUPPLY
+5V
HV+
GATE DRIVE
CIRCUIT
R1
D1
5.1 V
C1
0.1 µF
R2 39Ω
MOTOR
+
C2
0.01 µF
R SENSE
CCLK
V DD
CLAT
CHAN
V DD1
V DD2
CDAT
SCLK
V IN+
MCLK
MCLK1
SDAT
V IN-
MDAT
MDAT1
CS
GND1
GND2
MCLK2
THR1
HCPL-7560
C3
0.1 µF
MDAT2
GND
OVR1
RESET
HCPL-0872
HV-
Figure 17. Recommended Application Circuit.
14
TO
CONTROL
CIRCUIT
The design of the printed circuit board (PCB) should
follow good layout practices, such as keeping bypass
capacitors close to the supply pins, keeping output
signals away from input signals, the use of ground and
power planes, etc. In addition, the layout of the PCB can
also affect the isolation transient immunity (CMR) of the
isolated modulator, due primarily to stray capacitive
coupling between the input and the output circuits. To
obtain optimal CMR performance, the layout of the PC
board should minimize any stray coupling by maintaining the maximum possible distance between the input
and output sides of the circuit and ensuring that any
ground or power plane on the PC board does not pass
directly below or extend much wider than the body of
the isolated modulator.
Shunt Resistors
The current-sensing shunt resistor should have low
resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which
could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). Choosing a
particular value for the shunt is usually a compromise
between minimizing power dissipation and maximizing accuracy. Smaller shunt resistances decrease power
dissipation, while larger shunt resistances can improve
circuit accuracy by utilizing the full input range of the
isolated modulator. The first step in selecting a shunt is
determining how much current the shunt will be sensing. The graph in Figure 18 shows the RMS current in
each phase of a three-phase induction motor as a function of average motor output power (in horsepower, hp)
and motor drive supply voltage. The maximum value of
the shunt is determined by the current being measured
and the maximum recommended input voltage of the
isolated modulator. The maximum shunt resistance can
be calculated by taking the maximum recommended
input voltage and dividing by the peak current that the
shunt should see during normal operation. For example,
if a motor will have a maximum RMS current of 10 A and
can experience up to 50% overloads during normal operation, then the peak current is 21.1 A (= 10 x 1.414 x
1.5). Assuming a maximum input voltage of 200 mV, the
maximum value of shunt resistance in this case would
be about 10 mΩ.
The maximum average power dissipation in the shunt
can also be easily calculated by multiplying the shunt
resistance times the square of the maximum RMS current, which is about 1 W in the previous example.
15
40
MOTOR OUTPUT POWER - HORSEPOWER
PC Board Layout
440
380
220
120
35
30
25
20
15
10
5
0
0
5
15
20
25
30
10
MOTOR PHASE CURRENT - A (rms)
35
Figure 18. Motor Output Horsepower vs. Motor Phase Current and Supply
Voltage.
If the power dissipation in the shunt is too high, the
resistance of the shunt can be decreased below the
maximum value to decrease power dissipation. The
minimum value of the shunt is limited by precision
and accuracy requirements of the design. As the shunt
value is reduced, the output voltage across the shunt
is also reduced, which means that the offset and noise,
which are fixed, become a larger percentage of the
signal amplitude. The selected value of the shunt will
fall somewhere between the minimum and maximum
values, depending on the particular requirements of a
specific design.
When sensing currents large enough to cause significant heating of the shunt, the temperature coefficient
(tempco) of the shunt can introduce nonlinearity due to
the signal dependent temperature rise of the shunt. The
effect increases as the shunt-to-ambient thermal resistance increases. This effect can be minimized either by
reducing the thermal resistance of the shunt or by using a shunt with a lower tempco. Lowering the thermal
resistance can be accomplished by repositioning the
shunt on the PC board, by using larger PC board traces
to carry away more heat, or by using a heat sink.
For a two-terminal shunt, as the value of shunt resistance decreases, the resistance of the leads becomes a
significant percentage of the total shunt resistance. This
has two primary effects on shunt accuracy. First, the effective resistance of the shunt can become dependent
on factors such as how long the leads are, how they are
bent, how far they are inserted into the board, and how
far solder wicks up the lead during assembly (these issues will be discussed in more detail shortly). Second,
the leads are typically made from a material such as
copper, which has a much higher tempco than the material from which the resistive element itself is made,
resulting in a higher tempco for the shunt overall. Both
of these effects are eliminated when a four-terminal
shunt is used. A four-terminal shunt has two additional
terminals that are Kelvin-connected directly across the
resistive element itself; these two terminals are used to
monitor the voltage across the resistive element while
the other two terminals are used to carry the load current. Because of the Kelvin connection, any voltage
drops across the leads carrying the load current should
have no impact on the measured voltage.
Several four-terminal shunts from Isotek (Isabellenhütte) suitable for sensing currents in motor drives up
to 71 Arms (71 hp or 53 kW) are shown in Table 3; the
maximum current and motor power range for each
of the PBV series shunts are indicated. For shunt resistances from 50 mΩ down to 10 mΩ, the maximum current is limited by the input voltage range of the isolated
modulator. For the 5 mΩ and 2 mΩ shunts, a heat sink
may be required due to the increased power dissipation
at higher currents.
When laying out a PC board for the shunts, a couple of
points should be kept in mind. The Kelvin connections
to the shunt should be brought together under the
body of the shunt and then run very close to each other
to the input of the isolated modulator; this minimizes
the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the
measured signal. If the shunt is not located on the same
PC board as the isolated modulator circuit, a tightly
twisted pair of wires can accomplish the same thing.
Also, multiple layers of the PC board can be used to
increase current carrying capacity. Numerous platedthrough vias should surround each non-Kelvin terminal
of the shunt to help distribute the current between the
layers of the PC board. The PC board should use 2 or 4
oz. copper for the layers, resulting in a current carrying
capacity in excess of 20 A. Making the current carrying
traces on the PC board fairly large can also improve the
shunt’s power dissipation capability by acting as a heat
sink. Liberal use of vias where the load current enters
and exits the PC board is also recommended.
16
Shunt Connections
The recommended method for connecting the isolated
modulator to the shunt resistor is shown in Figure 17.
VIN+ (pin 2 of the HPCL-7560) is connected to the positive terminal of the shunt resistor, while VIN- (pin 3) is
shorted to GND1 with the power-supply return path
functioning as the sense line to the negative terminal of
the current shunt. This allows a single pair of wires or PC
board traces to connect the isolated modulator circuit
to the shunt resistor. By referencing the input circuit
to the negative side of the sense resistor, any load current induced noise transients on the shunt are seen as
a common-mode signal and will not interfere with the
current-sense signal. This is important because the large
load currents flowing through the motor drive, along
with the parasitic inductances inherent in the wiring of
the circuit, can generate both noise spikes and offsets
that are relatively large compared to the small voltages
that are being measured across the current shunt.
If the same power supply is used both for the gate drive
circuit and for the current sensing circuit, it is very important that the connection from GND1 of the isolated
modulator to the sense resistor be the only return path
for supply current to the gate drive power supply in
order to eliminate potential ground loop problems. The
only direct connection between the isolated modulator
circuit and the gate drive circuit should be the positive
power supply line.
Table 3. Isotek (Isabellenhütte) Four-Terminal Shunt Summary.
Shunt Resistance
Tol.
Maximum RMS
Current
mW
%
A
hp
kW
PBV-R050-0.5
50
0.5
3
0.8 - 3
0.6 - 2
PBV-R020-0.5
20
0.5
7
2-7
0.6 - 2
PBV-R010-0.5
10
0.5
14
4 - 14
3 - 10
PBV-R005-0.5
5
0.5
25 [28]
7 - 25 [8 - 28]
5 - 19 [6 - 21]
PBV-R002-0.5
2
0.5
39 [71]
11 - 39 [19 - 71]
8 - 29 [14 - 53]
Shunt
Resistor Part
Num
Motor Power Range
120 Vac-440 Vac
Note: Values in brackets are with a heatsink for the shunt.
In some applications, however, supply currents flowing
through the power-supply return path may cause offset
or noise problems. In this case, better performance may
be obtained by connecting VIN+ and VIN- directly across
the shunt resistor with two conductors, and connecting
GND1 to the shunt resistor with a third conductor for
the power-supply return path, as shown in Figure 19.
When connected this way, both input pins should be
bypassed. To minimize electromagnetic interference of
the sense signal, all of the conductors (whether two or
three are used) connecting the isolated modulator to
the sense resistor should be either twisted pair wire or
closely spaced traces on a PC board.
HV+
The 39Ω resistor in series with the input lead (R2) forms
a lowpass anti-aliasing filter with the 0.01µF input
bypass capacitor (C2) with a 400 kHz bandwidth. The
resistor performs another important function as well;
it dampens any ringing which might be present in the
circuit formed by the shunt, the input bypass capacitor,
and the inductance of wires or traces connecting the
two. Undamped ringing of the input circuit near the
input sampling frequency can alias into the baseband
producing what might appear to be noise at the output
of the device.
FLOATING
POSITIVE
SUPPLY
GATE DRIVE
CIRCUIT
R1
D1
5.1 V
C1
0.1 µF
R2a 39Ω
R2b 39Ω
MOTOR
+
C2a
0.01 µF
R SENSE
HV-
Figure 19. Schematic for Three Conductor Shunt Connection.
17
C2b
0.01 µF
V DD1
V DD2
V IN+
MCLK
V IN-
MDAT
GND1
GND2
HCPL-7560
Voltage Sensing
The HCPL-7560 Isolated Modulator can also be used to
isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage
divider at its input. The only restrictions are that the
impedance of the divider be relatively small (less than 1
kΩ) so that the input resistance (280 kΩ) and input bias
current (1µA) do not affect the accuracy of the measurement. An input bypass capacitor is still required,
although the 39Ω series damping resistor is not (the
resistance of the voltage divider provides the same
function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the
achievable bandwidth. To obtain higher bandwidth,
the input bypass capacitor (C2) can be reduced, but it
should not be reduced much below 1000 pF to maintain
adequate input bypassing of the isolated modulator.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2164EN
AV02-0408EN - June 18, 2007
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