HCPL-788J-000E

HCPL-788J Isolation Amplifier with Short Circuit and Overload Detection Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features Avago’s Isolation Amplifier with Short Circuit and Overload Detection makes motor phase current sensing compact, affordable and easy-to-implement while satisfying worldwide safety and regulatory requirements. • Output Voltage Directly Compatible with A/D Converters (0 V to VREF) • Fast (3 µs) Short Circuit Detection with Transient Fault Rejection • Absolute Value Signal Out­put for Overload Detection • 1 µV/°C Offset Change vs. Temperature • SO-16 Package • -40 °C to +85 °C Operating Temperature Range • 25 kV/µs Isolation Transient Immunity • Regulatory Approvals: UL, CSA, IEC/EN/DIN EN 607475-5 (1414 Vpeak Working Voltage) Applications • • • • • • Motor phase and rail current sensing Power inverter current and voltage sensing Industrial process control Data acquisition systems General purpose current and voltage sensing Traditional current transducer replacements Low Cost Three Phase Current Sensing with Short Circuit and Overload Detection ISOLATION BOUNDARY RSENSE1 1 VIN+ 2 VIN- +5 V 16 SHORT CIRCUIT FAULT 15 3 FAULT 14 4 ABSVAL VOUT 13 5 6 VREF 7 12 MICRO CONTROLLER 11 10 HCPL-788J 8 9 ISOLATION BOUNDARY RSENSE2 1 VIN+ 2 VIN- 16 15 3 FAULT 14 4 13 5 ABSVAL VOUT 6 VREF 7 M A/D CONVERTER 12 VREF 11 10 HCPL-788J 8 3 PHASE MOTOR 9 ISOLATION BOUNDARY RSENSE3 1 VIN+ 2 VIN- 3 PHASE ABSOLUTE VALUE OUTPUT 16 15 3 FAULT 14 4 13 + 5 ABSVAL VOUT 12 – 6 VREF 7 8 11 10 HCPL-788J OVERLOAD FAULT 9 + – VTH CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments. Description The HCPL-788J isolation ampli-fier is designed for current sensing in electronic motor drives. In a typical implementa-tion, motor currents flow through an external resistor and the resulting analog voltage drop is sensed by the HCPL-788J. A larger analog output voltage is created on the other side of the HCPL-788J’s optical isolation barrier. The output voltage is proportional to the motor current and can be connected directly to a single-supply A/D converter. A digital over-range output (FAULT) and an analog rectified output (ABSVAL) are also provided. The wire OR-able over-range output (FAULT) is useful for quick detec­tion of short circuit con­ditions on any of the motor phases. The wire-OR-able rectified output (ABSVAL), simplifies measure-ment of motor load since it performs polyphase rectification. Since the common-mode voltage swings several hundred volts in tens of nanoseconds in modern electronic motor drives, the HCPL-788J was designed to ignore very high commonmode transient slew rates (10 kV/µs). ISOLATION BOUNDARY INPUT CURRENT + HCPL-788J 39 Ω GND2 16 2 VIN- VDD2 15 3 CH FAULT 14 4 CL ABSVAL 13 5 VDD1 VOUT 12 A/D 6 VLED+ VREF 11 VREF 7 VDD1 VDD2 10 8 GND1 GND2 9 0.01 µF RSHUNT 0.02 Ω 0.1 µF ISOLATED +5 V µC VIN+ 1 0.1 µF 0.1 µF 4.7 kΩ TO OTHER PHASE OUTPUTS GND +5 V Figure 1. Current sensing circuit Pin Descriptions Symbol Description Symbol Description VIN+ FAULT Positive input voltage (±200 mV recommended). VIN- Negative input voltage (normally connected to GND1). CH CL Internal Bias Node. Connections to or between CH and CL other than the re­quired 0.1 µF capacitor shown, are not recommended. VDD1 Supply voltage input (4.5 V to 5.5 V). VLED+ LED anode. This pin must be left uncon­nected for guaranteed data sheet perfor­mance. (For optical coupling testing only.) VDD1 Supply voltage input (4.5 V to 5.5 V). GND1 Ground input. GND2 Ground input. VDD2 Supply voltage input (4.5 V to 5.5 V). 2 Short circuit fault output. FAULT changes from a high to low output voltage within 6 µs after VIN exceeds the FAULT Detection Threshold. FAULT is an open drain output that allows outputs from all the HCPL-788Js in a circuit to be connected together (“wired-OR”) forming a single fault signal for interfacing directly to the microcontroller. ABSVAL Absolute value of VOUT output. ABSVAL is 0 V when VIN=0 and increases toward VREF as VIN approaches +256 mV or -256 mV. ABSVAL is “wired-OR” able and is used for detecting overloads. VOUT Voltage output. Swings from 0 to VREF. The nominal gain is VREF /504 mV. VREF Reference voltage input (4.0 V to VDD2). This voltage establishes the full scale output ranges and gains of VOUT and ABSVAL. VDD2 Supply voltage input (4.5 V to 5.5 V). GND2 Ground input. Ordering Information HCPL-788J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part Number HCPL-788J RoHS Compliant non RoHS Compliant -000E no option -500E #500 Surface Mount Package Tape & Reel X SO-16 X X IEC/EN/DIN EN 60747-5-5 Quantity X 45 per tube X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-788J-500E to order product of 16-Lead Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliant. Example 2: HCPL-788J to order product of 16-Lead Surface Mount package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and RoHS compliant will use ‘–XXXE.’ Package Outline Drawings 16-Lead Surface Mount 0.457 (0.018) LAND PATTERN RECOMMENDATION 1.270 (0.050) 16 15 14 13 12 11 10 0.64 (0.025) 9 TYPE NUMBER DATE CODE A XXXX YYWW EEE AVAGO LEAD-FREE 7.493 ± 0.254 (0.295 ± 0.010) PIN 1 DOT 11.63 (0.458) LOT ID 2.16 (0.085) 1 2 3 4 5 6 7 8 10.312 ± 0.254 (0.406 ± 0.10) 8.763 ± 0.254 (0.345 ± 0.010) 9° 0.457 (0.018) Dimensions in Millimeters (Inches) 3.505 ± 0.127 (0.138 ± 0.005) 0-8° 0.64 (0.025) MIN. 10.363 ± 0.254 (0.408 ± 0.010) ALL LEADS TO BE COPLANAR ± 0.05 (0.002) 0.203 ± 0.076 (0.008 ± 0.003) STANDOFF Floating lead protrusion is 0.25 mm (10 mils) Max. Note: Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device 3 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-788J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-5 Approval under: DIN EN 60747-5-5 (VDE 0884-5):2011-11 EN 60747-5-5:2011 Approval under UL 1577, component recognition program up to VISO = 5000 VRMS. File E55361. UL Approval under CSA Component Acceptance Notice #5, File CA 88324. CSA IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1   for rated mains voltage ≤ 300 Vrms   for rated mains voltage ≤ 600 Vrms   for rated mains voltage ≤ 1000 Vrms I-IV I-IV I-III Climatic Classification 55/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 Unit VIORM 1414 VPEAK Input to Output Test Voltage, Method b**  VIORM x 1.875 = VPR, 100% Production Test with  tm = 1 sec, Partial discharge < 5 pC VPR 2652 VPEAK Input to Output Test Voltage, Method a**  VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,   Partial discharge < 5 pC VPR 2262 VPEAK Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 VPEAK Safety-limiting values — maximum values allowed in the event of a failure, also see Figure 2.   Case Temperature   Input Power   Output Power TS PS1, INPUT PS1, OUTPUT 175 400 600 °C mW mW Insulation Resistance at TSI, VIO = 500 V RS >109 Ω Maximum Working Insulation Voltage * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits within the application. Surface Mount Classification is class A in accordance with CECC00802. ** Refer to IEC/EN/DIN EN 60747-5-5 Optoisolator Safety Standard section of the Avago Regulatory Guide to Isolation Circuits, AV02-2041EN for a detailed description of Method a and Method b partial discharge test profiles. 800 Psi – OUTPUT Psi – INPUT PS – POWER – mW 600 400 200 0 0 25 50 125 150 75 100 TS – CASE TEMPERATURE – °C Figure 2. Dependence of safety-limiting values on temperature. 4 175 200 Package Characteristics Parameter Symbol Min. Input-Output Momentary Withstand Voltage VISO 5000 Resistance (Input-Output) RI-O Capacitance (Input-Output) Typ. Max. Units Test Conditions Fig. Notes Vrms RH < 50%, t = 1 min., TA = 25 °C 1,2,3 >109 Ω VI-O = 500 VDC 3 CI-O 1.3 pF f = 1 MHz 3 Input IC Junction-to-Case Thermal Resistance θjci 120 °C/W TA = 85 °C Output IC Junction-to-Case Thermal Resistance θjco 100 °C/W TA = 85 °C Insulation and Safety Related Specifications Parameter Symbol Min. Max. Conditions Minimum External Air Gap (Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. >175 V DIN IEC 112/VDE 0303 Part 1 Comparative Tracking Index) Minimum Internal Plastic Gap Tracking Resistance CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C Supply Voltages VDD1, VDD2 0.0 5.5 V Steady-State Input Voltage VIN+, VIN- -2.0 VDD1 + 0.5 V 2 Second Transient Input Voltage VIN+, VIN- -6.0 VDD1 + 0.5 V Output Voltage VOUT -0.5 VDD2 + 0.5 V Absolute Value Output Voltage ABSVAL -0.5 VDD2 + 0.5 V Reference Input Voltage VREF 0 VDD2 + 0.5 V V Reference Input Current IREF 20 mA Output Current IVOUT 20 mA Absolute Value Current IABSVAL 20 mA FAULT Output Current IFAULT 20 mA Input IC Power Dissipation PI 200 mW Output IC Power Dissipation PO 200 mW Note 4 5 Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA -40 85 °C Supply Voltages VDD1, VDD2 4.5 5.5 V Input Voltage (accurate and linear) VIN+, VIN- -200 200 mV Input Voltage (functional) VIN+, VIN- -2 2 V Reference Input Voltage VREF 4.0 VDD2 V FAULT Output Current IFAULT 4 mA 5 Note DC Electrical Specifications Unless otherwise noted, all typicals and figures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VREF = 4.0 V, VDD1 = VDD2 = 5 V and TA = 25°C; all Minimum/Maximum specifications are within the Recommended Operating Conditions. Test Conditions Fig. Note mV VIN+ = 0 V, TA = –40 °C to +85 °C 3, 4, 5 6 10 µV/°C VIN+ = 0 V, TA = –40 °C to +85 °C VREF/504 mV VREF/504 mV + 3% V/V |VIN+| < 200 mV, TA = 25 °C 6,7, 8,9 VREF/504 mV VREF/504 mV + 5% V/V |VIN+| < 200 mV, TA = –40 °C to +85 °C 6,7, 8,9 |∆G/∆TA| 50 300 ppm/°C |VIN+| < 200 mV, TA = –40 °C to +85 °C 6,7, 8,9 VOUT 200 mV Nonlinearity NL200 0.06 0.4 % |VIN+| < 200 mV, TA = –40 °C to +85 °C 6,7, 8,9 Maximum Input Voltage Before VOUT Clipping |VIN+|MAX 256 FAULT Detection Threshold |V THF| FAULT Low Output Voltage Parameter Symbol Min. Typ. Max. Units Input Offset Voltage VOS -3 0 3 Magnitude of Input Offset Change vs. Temperature |∆VOS/∆TA| 1 VOUT Gain G VREF/504 mV - 3% VOUT Gain G VREF/504 mV - 5% Magnitude of VOUT Gain Change vs. Temperature 8 mV 256 280 mV VOLF 350 800 mV IOL = 4 mA FAULT High Output Current IOHF 0.2 15 µA VFAULT = VDD2 ABSVAL Output Error eABS 0.6 2 % of full scale output Input Supply Current IDD1 10.7 20 mA Output Supply Current IDD2 10.4 20 mA Reference Voltage Input Current IVREF 0.26 1 mA Input Current IIN+ -350 nA VIN+ = 0 V Input Resistance RIN 800 kΩ VIN+ = 0 V VOUT Output Resistance ROUT 0.2 Ω ABSVAL Output Resistance RABS 0.3 Ω Input DC CommonMode Rejection Ratio CMRRIN 85 dB 6 230 7 10 9 11 10 11 AC Electrical Specifications Unless otherwise noted, all typicals and figures are at the nominal operating conditions of VIN+ = 0, VIN- = 0 V, VREF = 4.0 V, VDD1 = VDD2 = 5 V and TA = 25 °C; all Minimum/Maximum specifications are within the Recommended Operating Conditions. Parameter Symbol Min. Typ. VOUT Bandwidth (-3 dB) BW 20 30 VOUT Noise NOUT 2.2 VIN to VOUT Signal Delay (50 - 50%) tDSIG VOUT Rise/Fall Time (10–90) Units Test Conditions Fig. kHz VIN+ = 200 mVpk-pk sine wave 12, 20 4 mVrms VIN+ = 0 V 20 12 9 20 µs VIN+ = 50 mV to 200 mV step 14, 20 13 tRFSIG 10 25 µs VIN+ = 50 mV to 200 mV step 14, 20 ABSVAL Signal Delay tDABS 9 20 µs VIN+ = 50 mV to 200 mV step 14, 20 ABSVAL Rise/Fall Time (10–90%) tRFABS 10 25 µs VIN+ = 50 mV to 200 mV step 14, 20 FAULT Detection Delay tFHL 3 6 µs VIN+ = 0 mV to ±500 mV step. 15, 20 14 FAULT Release Delay tFLH 10 20 µs VIN+ = ±500 mV to 0 mV step 16, 20 15 Transient Fault Rejection tREJECT 1 2 µs VIN+ = 0 mV to ±500 mV pulse 17, 20 16 Common Mode Transient Immunity CMTI 10 25 kV/µs For VOUT, FAULT, and ABSVAL outputs Common-Mode Rejection Ratio at 60 Hz CMRR >140 dB 7 Max. Note 17 18 Notes: 1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 600 Vrms for 1 second. This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table, if applicable. 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output  continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 insulation characteristics table. 3. Device considered a two terminal device: pins 1-8 shorted together and pins 9-16 shorted together. 4. VDD1 must be applied to both pins 5 and 7. VDD2 must be applied to both pins 10 and 15. 5. If VREF exceeds VDD2 (due to power-up sequence, for example), the current into pin 11 (IREF) should be limited to 20 mA or less. 6. Input Offset voltage is defined as the DC Input voltage required to obtain an output voltage (at pin 12) of VREF/2. 7. This is the Absolute Value of Input Offset Change vs. Temperature. 8. This is the Absolute Value of VOUT Gain Change vs. Temperature. 9. |VIN+| must exceed this amount in order for the FAULT output to be activated. 10. ABSVAL is derived from VOUT (which has the gain and offset tolerances stated earlier). ABSVAL is 0 V when VIN = 0 V and increases toward VREF as VIN approaches +256 mV or -256 mV. εABS is the difference between the actual ABSVAL output and what ABSVAL should be, given the value of VOUT. εABS is expressed in terms of percent of full scale and is defined as: |ABSVAL - 2 x | VOUT - VREF / 2| | VREF x 100. 11. CMRRIN is defined as the ratio of the gain for differential inputs applied between pins 1 and 2 to the gain for common mode inputs applied to both pins 1 and 2 with respect to pin 8. 12. The signal-to-noise ratio of the HCPL-788J can be improved with the addition of an external low pass filter to the output. See Frequently Asked Question #4.2 in the Applications Information Section at the end of this data sheet. 13. As measured from 50% of VIN to 50% of VOUT. 14. This is the amount of time from when the FAULT Detection Threshold (230 mV ≤ VTHF ≤ 280 mV) is exceeded to when the FAULT output goes low. 15. This is the amount of time for the FAULT Output to return to a high state once the FAULT Detection Threshold (230 mV ≤ V THF ≤ 280 mV) is no longer exceeded. 16. Input pulses shorter than the fault rejection pulse width (tREJECT ), will not activate the FAULT (pin 14) output. See Frequently Asked Question #2.3 in the Applications Information Section at the end of this data sheet for additional detail on how to avoid false tripping of the FAULT output due to cable capacitance charging transients. 17. CMTI is also known as Common Mode Rejection or Isolation Mode Rejection. It is tested by applying an exponentially rising falling voltage step on pin 8 (GND1) with respect to pin 9 (GND2). The rise time of the test waveform is set to approximately 50 ns. The amplitude of the step is adjusted until VOUT (pin 12) exhibits more than 100 mV deviation from the average output voltage for more than 1µs. The HCPL-788J will continue to function if more than 10 kV/µs common mode slopes are applied, as long as the break-down voltage limitations are observed. [The HCPL-788J still functions with common mode slopes above 10 kV/µs, but output noise may increase to as much as 600 mV peak to peak.] 18. CMRR is defined as the ratio of differential signal gain (signal applied differentially between pins 1 and 2) to the common mode gain (input pins tied to pin 8 and the signal applied between the input and the output of the isolation amplifier) at 60 Hz, expressed in dB. 8 800 TYPICAL MAX 600 600 OFFSET CHANGE - ∆VOS -µV INPUT OFFSET CHANGE - ∆VOS -µV 800 400 200 0 200 0 -200 -200 -400 -400 -600 -600 -800 -800 -40 -20 0 20 40 TEMPERATURE – °C 60 80 800 4.0 600 3.5 400 200 0 -200 -400 -600 -800 4.5 4.75 5.0 5.25 OUTPUT SUPPLY VOLTAGE – VDD2 – V 2.0 1.5 1.0 0.5 -200 0 100 -100 INPUT VOLTAGE – VIN – mV 200 300 1.5 ∆GAIN CHANGE - % ∆GAIN CHANGE - % 2.5 2.0 1.0 0.5 0 -0.5 1.0 0.5 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 5.5 Figure 6. VOUT vs. VIN TYPICAL WORST CASE 1.5 4.75 5.0 5.25 INPUT SUPPLY VOLTAGE – VDD1 – V 3.0 0 -300 5.5 Figure 5. Input offset voltage change vs. VDD2 2.0 4.5 Figure 4. Input offset voltage change vs. VDD1 VOUT – OUTPUT VOLTAGE – V OFFSET CHANGE - ∆VOS -µV Figure 3. Input offset voltage change vs. temperature -40 -20 0 20 40 TEMPERATURE – °C Figure 7. Gain change vs. temperature 9 400 60 80 -2.0 4.5 4.75 5.0 5.25 INPUT SUPPLY VOLTAGE – VDD1 – V Figure 8. Gain change vs. VDD1 5.5 FAULT OUTPUT VOLTAGE – FAULTBAR – V 2.0 ∆GAIN CHANGE - % 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 4.75 5.0 5.25 OUTPUT SUPPLY VOLTAGE – VDD2 – V 4.5 5.5 Figure 9. Gain change vs. VDD2 3.0 BANDWIDTH – kHz ABSVAL – ABSOLUTE VALUE OUTPUT – V 3.5 2.5 2.0 1.5 1.0 0.5 -200 0 100 -100 INPUT VOLTAGE – VIN – mV 300 200 Figure 11. ABSVAL output voltage vs. VIN FAULT DETECTION DELAY – µs 30 29 28 27 26 25 -40 -20 0 20 40 TEMPERATURE – °C 60 300 mV 0 mV 3.25 -300 mV 5V 2.5 V 3.0 VIN 300 mV/D VOUT (PIN 12) 2.5 V/D 0V 5V 2.75 2.5 V -40 -20 300 200 35 34 33 32 31 0 40 20 TEMPERATURE – °C 60 80 0V 5V 2.5 V 0V Figure 13. FAULT detection delay vs. temperature 10 0 100 -100 INPUT VOLTAGE – VIN – mV Figure 12. Bandwidth vs. temperature 3.5 2.5 -200 Figure 10. FAULT output voltage vs. VIN 4.0 0 -300 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -300 ABSVAL (PIN 13) 2.5 V/D FAULT (PIN 14) 2.5 V/D 5.00 µs/DIV Figure 14. Step response, 0 mV to 200 mV input, at VREF = 5 V 80 300 mV 0 mV -300 mV 5V 2.5 V 0V 5V 2.5 V VIN 300 mV/D VOUT (PIN 12) 2.5 V/D 0V ABSVAL (PIN 13) 2.5 V/D 0 mV FAULT (PIN 14) 2.5 V/D 5.00 µs/DIV VIN 300 mV/D -300 mV 5V 2.5 V 0V 5V 2.5 V 0V VOUT (PIN 12) 2.5 V/D ABSVAL (PIN 13) 2.5 V/D FAULT (PIN 14) 2.5 V/D 5.00 µs/DIV VIN 300 mV/D 0 mV -300 mV 5V VOUT (PIN 12) 2.5 V/D 2.5 V 0V 5V ABSVAL (PIN 13) 2.5 V/D 2.5 V 0V 5V 2.5 V 0V FAULT (PIN 14) 2.5 V/D 100 µs/DIV Figure 19. Sine response 400 mV peak-to-peak 4 kHz input, at VREF = 5 V 11 VOUT (PIN 12) 2.5 V/D 2.5 V ABSVAL (PIN 13) 2.5 V/D 2.5 V FAULT (PIN 14) 2.5 V/D 2.5 V 0V 5.00 µs/DIV Figure 16. FAULT release, 300 mV to 0 mV input, at VREF = 5 V 2V 0 mV 2.5 V 0V 5.0 V VIN 2.0 V/D VOUT (PIN 12) 2.5 V/D ABSVAL (PIN 13) 2.5 V/D 2.5 V 0V 5.0 V Figure 17. FAULT rejecting a 1 µs, 0 V to 2 V to 0 V input. Rejection is independent of amplitude 300 mV -300 mV 5V -2 V 5.0 V 0V 5V 2.5 V VIN 300 mV/D 0V 5V Figure 15. FAULT detection, 0 mV to 300 mV input, at VREF = 5 V 300 mV 0 mV 0V 5V 0V 5V 2.5 V 300 mV 2.5 V 0V FAULT (PIN 14) 2.5 V/D 5.00 µs/DIV Figure 18. Detection of 6 µs fault 0 to 2 V to 0 input, at VREF = 5 V 5V VIN+ 50 Ω 10 Ω 14 1 4.7 kΩ FAULT 13 0.01 µF ABSVAL 12 3 VOUT 11 0.1 µF 4 VREF HCPL-788J 0.1 µF 6 5, 7 VDD1 0.1 µF 10,15 2, 8 VDD2 0.1 µF 9, 16 Figure 20. AC test circuit HCPL-788J 1 VIN+ 2 VIN- 3 CH 4 CL FAULT DETECT ENCODER Σ∆ MODULATOR DECODER D/A LPF VOUT 12 256 mV REFERENCE 6 VLED+ 5 VDD1 7 VDD1 8 GND1 Figure 21. Internal block diagram 12 VREF 11 HCPL-788J fig 20 ABSVAL 13 RECTIFIER FAULT 14 VDD2 15 VDD2 10 GND2 9 GND2 16 Applications Information Production Description Figure 21 shows the internal block diagram of the HCPL788J. The analog input (VIN) is con­verted to a digital signal using a sigma-delta (∑-∆) analog to digital (A/D) converter. This A/D samples the input 6 million times per second and generates a high speed 1-bit output representing the input very accurately. This 1 bit data stream is transmitted via a light emitting diode (LED) over the optical barrier after encoding. The detector converts the optical signal back to a bit stream. This bit stream is decoded and drives a 1 bit digital to analog (D/A) con­verter. Finally a low pass filter and output buffer drive the output signal (VOUT ) which linearly rep­re­sents the analog input. The output signal full-scale range is determined by the external reference voltage (VREF). By sharing this reference voltage (which can be the supply voltage), the full-scale range of the HCPL-788J can precisely match the full-scale range of an external A/D converter. 4.0 3.0 3.0 2.0 0 0 0.01 0 0.01 0.04 4.0 3.0 2.0 1.0 0 2.0 1.0 0.02 0.03 TIME – SECONDS Figure 22. ABSVAL with 3 phases, wired-ORed together ABSVAL – V The HCPL-788J’s other main function is to provide galvanic isolation between the analog input and the analog output. An internal voltage reference determines the full-scale analog input range of the modulator (approximately ±256 mV); an input range of ±200 mV is recommended to achieve optimal performance. 4.0 1.0 Figure 24. ABSVAL with 1 phase 13 One other output is provided — the rectified output (ABSVAL). This output is also wire OR-able. The motor phase having the highest instantaneous rectified output pulls the common output high. When three sinusoidal motor phases are combined, the rectified output (ABSVAL) is essentially a DC signal represent­ing the rms motor current. This single DC signal and a threshold comparator can indicate motor overload conditions before dam­age to the motor or drive occur. Figure 22 shows the ABSVAL output when 3 HCPL-788Js are used to monitor a sinusoidal 60 Hz current. Figures 23 and 24 show the ABSVAL output when only 2 or 1 of the 3 phases are monitored, respectively. ABSVAL – V ABSVAL – V In addition, the HCPL-788J compares the analog input (VIN) to both the negative and positive full-scale values. If the input exceeds the full-scale range, the short-circuit fault output (FAULT) is activated quickly. This feature operates indepen­dently of the ∑-∆ A/D converter in order to provide the high-speed response (typically 3 µs) need- ed to protect power tran­sistors. The FAULT output is wire OR-able so that a short circuit on any one motor phase can be detected using only one signal. 0.02 TIME – SECONDS 0.03 0.04 0 0 0.01 0.02 0.03 TIME – SECONDS Figure 23. ABSVAL with 2 phases, wired-ORed together 0.04 INPUT CURRENT R2 39 Ω + RSHUNT 0.02 Ω HCPL-788J .01 µF R1 C3 0.1 µF ISOLATED +5 V C1 0.1 µF 1 VIN+ GND2 16 2 VIN- VDD2 15 3 CH FAULT 14 4 CL ABSVAL 13 5 VDD1 VOUT 12 A/D 6 VLED1+ VREF 11 VREF 7 VDD1 VDD2 10 8 GND1 GND2 9 C2 C6 0.1 µF R3 4.7 kΩ µC TO OTHER PHASE OUTPUTS C8 C4 C7 C5 GND +5 V Figure 25. Recommended applications circuit C5 = C7 = C8 = 470 pF C4 = 0.1 µF + HV+ FLOATING POWER SUPPLY GATE DRIVE CIRCUIT – R4 R2 39 Ω MOTOR + D1 5.1 V C1 0.1 µF C2 0.01 µF R1 + RSENSE HV- HCPL-788J 5 VDD1 GND2 16 1 VIN+ VDD2 15 2 VIN- FAULT 14 8 GND1 ABSVAL 13 7 VDD1 VOUT 12 3 CH VREF 11 4 CL VDD2 10 6 VLED+ GND2 9 Figure 26. Recommended supply and sense resistor connections Analog Interfacing Power Supplies and Bypassing The recommended supply con­nec­tions are shown in Figure 26. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple zener diode (D1); the value of resistor R4 should be chosen to supply sufficient current from the existing floating supply. The voltage from the current sensing resistor (Rsense) is applied to the input of the HCPL-788J through an RC anti-aliasing filter (R2 and C2). 14 Although the application cir­cuit is relatively simple, a few re­c­ommendations should be followed to ensure optimal performance. The power supply for the HCPL-788J is most often obtained from the same supply used to power the power transistor gate drive circuit. If a dedicated supply is required, in many cases it is possible to add an additional winding on an existing trans­former. Otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency DC-DC converter. An inexpensive 78L05 three-terminal regulator can also be used to reduce the floating supply voltage to 5 V. To help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulator’s input bypass capacitor. As shown in Figure 25, 0.1 µF bypass capacitors (C1, C3, C4, and C6) should be located as close as possible to the pins of the HCPL-788J. The bypass capacitors are required because of the high-speed digital nature of the signals inside the HCPL-788J. A 0.01 µF bypass capacitor (C2) is also recommended at the input due to the switched-capacitor nature of the input circuit. The input bypass capacitor also forms part of the anti-aliasing filter, which is recommended to prevent high-frequency noise from aliasing down to lower frequencies and interfering with the input signal. The input filter also performs an important reliability function — it reduces transient spikes from ESD events flowing through the current sensing resistor. TOP LAYER BOTTOM LAYER Figure 27. Example printed circuit board layout 15 PC Board Layout The design of the printed circuit board (PCB) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. In addition, the layout of the PCB can also affect the isolation transient immunity (CMTI) of the HCPL788J, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMTI performance, the layout of the PC board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring that any ground or power plane on the PC board does not pass directly below or extend much wider than the body of the HCPL-788J. Current Sensing Resistors The current sensing resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to main­­tain overall circuit accuracy). Choosing a particular value for the resistor is usually a compro­mise between minimizing power dissipation and maximizing ac­curacy. Smaller sense resistance decreases power dissipation, while larger sense resistance can improve circuit accuracy by utilizing the full input range of the HCPL-788J. The first step in selecting a sense resistor is determining how much current the resistor will be sens­ing. The graph in Figure 28 shows the rms current in each phase of a three-phase induction motor as a function of average motor output power (in horse­power, hp) and motor drive supply voltage. The maximum value of the sense resistor is determined by the current being measured and the maximum recommended input voltage of the isolation amplifier. The maxi­mum sense resistance can be calculated by taking the maxi­mum recommended input voltage and dividing by the peak current that the sense resistor should see during normal operation. For example, if a motor will have a maximum rms current of 10 A and can experience up to 50% overloads during normal operation, then the peak current is 21.1 A (=10 × 1.414 × 1.5). Assuming a maximum input voltage of 200 mV, the maximum value of sense resistance in this case would be about 10 mΩ. MOTOR OUTPUT POWER – HORSEPOWER The maximum average power dissipation in the sense resistor can also be easily calculated by multiplying the sense resistance times the square of the maximum rms current, which is about 1 W in the previous example. 40 440 380 220 120 35 30 25 20 15 10 5 0 0 5 10 15 20 25 MOTOR PHASE CURRENT – A (rms) 30 35 Figure 28. Motor output horsepower vs. motor phase current and supply voltage 16 If the power dissipation in the sense resistor is too high, the resistance can be decreased below the maximum value to decrease power dissipation. The minimum value of the sense resistor is limited by precision and accuracy requirements of the design. As the resistance value is reduced, the output voltage across the resistor is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. The selected value of the sense resistor will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specific design. When sensing currents large enough to cause significant heating of the sense resistor, the temperature coefficient (tempco) of the resistor can introduce nonlinearity due to the signal dependent temperature rise of the resistor. The effect increases as the resistor-to-ambient thermal resistance increases. This effect can be minimized by reducing the thermal resistance of the current sensing resistor or by using a resistor with a lower tempco. Lowering the thermal resistance can be accomplished by reposi­tion­ing the current sensing resistor on the PC board, by using larger PC board traces to carry away more heat, or by using a heat sink. For a two-terminal current sensing resistor, as the value of resistance decreases, the resistance of the leads become a significant per­centage of the total resistance. This has two primary effects on resistor accuracy. First, the effective resistance of the sense resistor can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the leads during assembly (these issues will be discussed in more detail shortly). Second, the leads are typically made from a material, such as copper, which has a much higher tempco than the material from which the resis­tive element itself is made, result­ing in a higher tempco overall. Both of these effects are eliminated when a four-terminal current sensing resistor is used. A four-terminal resistor has two additional terminals that are Kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. Because of the Kelvin connection, any voltage drops across the leads carrying the load current should have no impact on the measured voltage. When laying out a PC board for the current sensing resistors, a couple of points should be kept in mind. The Kelvin connections to the resistor should be brought together under the body of the resistor and then run very close to each other to the input of the HCPL-788J; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. If the sense resistor is not located on the same PC board as the HCPL-788J circuit, a tightly twisted pair of wires can accomplish the same thing. Also, multiple layers of the PC board can be used to increase current carrying capacity. Numerous platedthrough vias should surround each non-Kelvin terminal of the sense resistor to help distribute the current between the layers of the PC board. The PC board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 A. Making the current carrying traces on the PC board fairly large can also improve the sense resistor’s power dissipation capability by acting as a heat sink. Liberal use of vias where the load current enters and exits the PC board is also recommended. 17 Sense Resistor Connections The recommended method for connecting the HCPL-788J to the current sensing resistor is shown in Figure 26. VIN+ (pin 1 of the HCPL-788J) is connected to the positive terminal of the sense resistor, while VIN- (pin 2) is shorted to GND1 (pin 8), with the power-supply return path functioning as the sense line to the negative terminal of the current sense resistor. This allows a single pair of wires or PC board traces to connect the HCPL-788J circuit to the sense resistor. By referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the resistor are seen as a commonmode signal and will not interfere with the current-sense signal. This is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are rela­tively large compared to the small voltages that are being measured across the current sensing resistor. Ifthesamepowersupplyisusedbothforthegatedrivecircuit and for the current sensing circuit, it is very important that the connection from GND1 of the HCPL-788J to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. The only direct connection between the HCPL-788J circuit and the gate drive circuit should be the positive power supply line. Please refer to Avago Technologies’ Applications Note 1078 for additional information on using Isolation Amplifiers. Frequently Asked Questions about the HCPL-788J 1. The Basics 1.1: Why should I use the HCPL-788J for sensing current when Hall-effect sensors are available which don’t need an isolated supply voltage? Historically, motor control current sense designs have required trade-offs between signal accuracy, response time, and the use of discrete components to detect short circuit and overload conditions. The HCPL-788J greatly simplifies current-sense designs by providing an output voltage which can connect directly to an A/D converter as well as integrated short circuit and overload detection (eliminating the need for external circuitry). Available in an auto-insertable, SO-16 package, the HCPL-788J is smaller than and has better linearity, offset vs. temperature and Common Mode Rejection (CMR) performance than most Hall-effect sensors. 1.2: What is the purpose of the VREF input? The VREF input establishes the full scale output range. VREF can be connected to the supply voltage (VDD2) or a voltage between 4 V and VDD2. The nominal gain of the HCPL788J is the output full scale range divided by 504 mV. 1.3: What is the purpose of the rectified (ABSVAL) output on pin 13? When 3 phases are wire-ORed together, the 3 phase AC currents are combined to form a DC voltage with very little ripple on it. This can be simply filtered and used to monitor the motor load. Moderate overload currents which don’t trip the FAULT output can thus be detected easily. 2. Sense Resistor and Input Filter 2.1: Where do I get 10 mΩ resistors? I have never seen one that low. Although less common than values above 10 Ω, there are quite a few manufacturers of resistors suitable for measuring currents up to 50 A when combined with the HCPL788J. Example product information may be found at Vishay’s web site (http://www. vishay.com) and Isotek’s web site (http://www.isotekcorp.com). 2.2: Should I connect both inputs across the sense resistor instead of grounding VIN- directly to pin 8? This is not necessary, but it will work. If you do, be sure to use an RC filter on both pin 1 (VIN+) and pin 2 (VIN-) to limit the input voltage at both pads. 2.3: How can I avoid false tripping of the fault output due to cable capacitance charging transients? In PWM motor drives there are brief spikes of current flowing in the wires leading to the motor each time a phase voltage is switched between states. The amplitude and duration of these current spikes is determined by the slew rate of the power transistors and the wiring impedances. To avoid false tripping of the FAULT output (pin 14) the HCPL-788J includes a blanking filter. This filter ignores over-range input conditions shorter than 1 µs. For very long motor wires, it may be necessary to increase the time constant of the input RC antialiasing filter to keep the peak value of the HCPL-788J inputs below ±230 mV. For example, a 39 Ω, 0.047 µF RC filter on pin 1 will ensure that 2 µs wide 500 mV pulses across the sense resistor do not trip the FAULT output. 2.4: Do I really need an RC filter on the input? What is it for? Are other values of R and C okay? This filter prevents damage from input spikes which may go beyond the absolute maximum ratings of the HCPL-788J inputs during ESD and other transient events. The filter also prevents aliasing of high frequency (above 3 MHz) noise at the sampled input. Other RC values are certainly OK, but should be chosen to prevent the input voltage (pin 1) from exceeding ±5 V for any conceivable current waveform in the sense resistor. Remember to account for inductance of the sense resistor since it is possible to momentarily have tens of volts across even a 1 mΩ resistor if di/dt is quite large. 2.5: How do I ensure that the HCPL-788J is not destroyed as a result of short circuit conditions which cause voltage drops across the sense resistor that exceed the ratings of the HCPL-788J’s inputs? Select the sense resistor so that it will have less than 5 V drop when short circuits occur. The only other requirement is to shut down the drive before the sense resistor is damaged or its solder joints melt. This ensures that the input of the HCPL-788J cannot be damaged by sense resistors going open-circuit. 18 3. Isolation and Insulation 3.1: How many volts will the HCPL-788J withstand? The momentary (1 minute) withstand voltage is 5000 V rms per UL1577 and CSA Component Acceptance Notice #5. 3.2: What happens if I don’t use the 470 pF output capacitors Avago recommends? These capacitors are to reduce the narrow output spikes caused by high common mode slew rates. If your application does not have rapid common mode voltage changes, these capacitors are not needed. 4. Accuracy 4.1: What is the meaning of the offset errors and gain errors in terms of the output? For zero input, the output should ideally be 1/2 of VREF. The nominal slope of the input/ output relationship is VREF divided by 0.504 V. Offset errors change only the DC input voltage needed to make the output equal to 1/2 of VREF. Gain errors change only the slope of the input/output relationship. For example, if VREF is 4.0 V, the gain should be 7.937 V/V. For zero input, the output should be 2.000 V. Input offset voltage of ±3 mV means the output voltage will be 2.000 V ±0.003*7.937 or 2.000 ±23.8 mV when the input is zero. Gain tolerance of ±5% means that the slope will be 7.937 ±0.397. Over the full range of ±3 mV input offset error and ±5% gain error, the output voltage will be 2.000 ±25.0 mV when the input is zero. 4.2: Can the signal to noise ratio be improved? Yes. Some noise energy exists beyond the 30 kHz bandwidth of the HCPL-788J. An external RC low pass filter can be used to improve the signal to noise ratio. For example, a 680 Ω, 4700 pF RC filter will cut the rms output noise roughly by a factor of 2. This filter reduces the -3dB signal bandwidth only by about 10%. In applications needing only a few kHz bandwidth even better noise performance can be obtained. The noise spectral density is roughly 400 nV/√ Hz below 15 kHz (input referred). As an example, a 2 kHz (680 Ω, 0.1 µF) RC low pass filter reduces output noise to a typical value of 0.08 mVrms. 4.3: I need 1% tolerance on gain. Does Avago sell a more precise version? At present Avago does not have a standard product with tighter gain tolerance. A 100 Ω variable resistor divider can be used to adjust the input voltage at pin 1, if needed. 4.4: The output doesn’t go all the way to VREF when the input is above full scale. Why not? Op-amps are used to drive VOUT (pin 12) and ABSVAL (pin 13). These op-amps can swing nearly from rail to rail when there is no load current. The internal VDD2 is about 100 mV below the external VDD2. In addition, the pullup and pulldown output transistors are not identical in capability. The net result is that the output can typically swing to within 20 mV of GND2 and to within 150 mV of VDD2. When VREF is tied to VDD2, the output cannot reach VREF exactly. This limitation has no effect on gain — only on maximum output voltage. The output remains linear and accurate for all inputs between -200 mV and +200 mV. For the maximum possible swing range, separate VREF and VDD2 voltages can be used. Since 5.0 V is normally recommended for VDD2, use of 4.5 V or 4.096 V references for VREF allow the outputs to swing all the way up to VREF (and down to typically 20 mV). 4.5: Does the gain change if the internal LED light output degrades with time? No. The LED is used only to transmit a digital pattern. Gain is determined by a bandgap voltage reference and the user-provided VREF. Avago has accounted for LED degradation in the design of the product to ensure long life. 4.6: Why is gain defined as VREF/504 mV, not VREF/512 mV as expected, based on Figure 24? Ideally gain would be VREF/512 mV, however, due to internal settling characteristics, the average effective value of the internal 256 mV reference is 252 mV. 19 5. Power Supplies and Start-Up 5.1: What are the output voltages before the input side power supply is turned on? VOUT (pin 12) is close to zero volts, ABSVAL (pin 13) is close to VREF and FAULT (pin 14) is in the high (inactive) state when power to the input side is off. In fact, a self test can be performed using this information. In a motor drive, it is possible to turn off all the power transistors and thus cause all the sense resistor voltages to be zero. In this case, finding VOUT less than 1/4 of VREF, ABSVAL more than 3/4 of VREF and FAULT in the high state indicates that power to the input side is not on. 5.2: How long does the HCPL-788J take to begin working properly after power-up? About 50 µs after a VDD2 power-up and 100 µs after a VDD1 power-up. 6. Miscellaneous 6.1: How does the HCPL-788J measure negative signals with only a +5 V supply? The inputs have a series resistor for protection against large negative inputs. Normal signals are no more than 200 mV in amplitude. Such signals do not forward bias any junctions sufficiently to interfere with accurate operation of the switched capacitor input circuit. 6.2: What load capacitance can the HCPL788J drive? Typically, noticeable ringing and overshoot begins for CLOAD above 0.02 µF. Avago recommends keeping the load capacitance under 5000 pF (at pin 12). ABSVAL (pin 13) typically exhibits no instability at any load capacitance, but speed of response gradually slows above 470 pF load. 6.3: Can I use the HCPL-788J with a bipolar input A/D converter? Yes, with a compromise on offset accuracy. One way to do this is by connecting +2.5 V to pins 10, 11, and 15 and connecting -2.5 V to pins 9 and 16 with 0.1 µF bypass capacitors from +2.5 V to -2.5 V and from -2.5 V to ground. Note that FAULT cannot swing above 2.5 V in this case, so a level shifter may be needed. Alternately, a single 5 V supply could be power the HCPL-788J which could drive an op amp configured to subtract 1/2 of VREF from VOUT. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. Obsoletes AV01-0570EN AV02-1546EN - March 9, 2015