HCPL-J314-000E

HCPL-J314 0.6 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-J314 family of devices consists of an AlGaAs LED optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power IGBTs. For IGBTs with higher ratings the HCPL-3150 (0.6 A) or HCPL-3120 (2.5 A) optocouplers can be used. • 0.6 A maximum peak output current • 0.4 A minimum peak output current • High speed response: 0.7 µs max. propagation delay over temperature range • Ultra high CMR: min. 25 kV/µs at VCM = 1.5 kV • Bootstrappable supply current: max. 3 mA • Wide operating temperature range: -40°C to 100°C • Wide VCC operating range: 10 V to 30 V over temperature range • Available in DIP8 (single) and SO16 (dual) package • Safety approvals: UL Recognized, 3750 Vrms for 1 minute. CSA Approval IEC/EN/DIN EN 60747-5-2 Approval. VIORM = 891 Vpeak Functional Diagram N/C 1 8 VCC ANODE 2 7 VO CATHODE 3 6 VO N/C 4 5 VEE SHIELD HCPL-J314 Applications • • • • • • Isolated IGBT/Power MOSFET gate drive AC and brushless DC motor drives Inverters for appliances Industrial inverters Switch Mode Power Supplies (SMPS) Uninterruptable Power Supplies (UPS) Truth Table LED   VO OFF LOW ON HIGH A 0.1 µF bypass capacitor must be connected between pins VCC and VEE. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide Package Type Part Number Number of Channels 8-pin DIP (300 Mil) HCPL-J314 1 SO16 HCPL-314J 2 Note: Please refer to HCPL-314J datasheet for more details Ordering Information HCPL-J314 is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part Number HCPL-J314 RoHS Compliant Non RoHS Compliant -000E No option -300E #300 -500E #500 Package 300mil DIP-8 Surface Mount Gull Wing X X X X Tape & Reel X IEC/EN/DIN EN 60747-5-2 Quantity X 50 per tube X 50 per tube X 1000 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-J314-500E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-J314 to order product of 300 mil DIP package in tube packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and non RoHS complaint Option data sheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘.  HCPL-J314 Package Outline Drawings Standard DIP Package 7.62 ± 0.25 (0.300 ± 0.010) 9.80 ± 0.25 (0.386 ± 0.010) 8 7 6 5 HCPL-J314 6.35 ± 0.25 (0.250 ± 0.010) DATE CODE YYWW 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. + 0.076 0.254 - 0.051 + 0.003) (0.010 - 0.002) 5° TYP. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). 1.080 ± 0.320 (0.043 ± 0.013) 0.65 (0.025) MAX. NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX. 2.54 ± 0.25 (0.100 ± 0.010) Gull Wing Surface Mount Option 300 LAND PATTERN RECOMMENDATION 9.80 ± 0.25 (0.386 ± 0.010) 8 7 6 1.02 (0.040) 5 HCPL-J314 YYWW MOLDED 1 2 3 6.350 ± 0.25 (0.250 ± 0.010) 10.9 (0.430) 4 1.27 (0.050) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 2.540 (0.100) BSC 0.51 ± 0.130 (0.020 ± 0.005) DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.  2.0 (0.080) 0.255 (0.075) 0.010 (0.003) 12° NOM. LEAD COPLANARITY MAXIMUM: 0.102 (0.004) Solder Reflow Temperature Profile Regulatory Information The HCPL-J314 has been approved by the following organizations: 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. 200 PEAK TEMP. 245°C PEAK TEMP. 240°C 2.5°C ± 0.5°C/SEC. 30 SEC. 160°C 150°C 140°C SOLDERING TIME 200°C 100 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 200 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TL TEMPERATURE PEAK TEMP. 230°C 30 SEC. 3°C + 1°C/–0.5°C PREHEATING TIME 150°C, 90 + 30 SEC. Tsmax 260 +0/-5 °C TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 217 °C RAMP-UP 3 °C/SEC. MAX. 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25 °C to PEAK TIME NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C Note: Non-halide flux should be used.  IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01 250 UL Approval under UL 1577, component recognition program up to VISO = 3750 Vrms. File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Description Symbol Characteristic Installation classification per DIN VDE 0110/1.89, Table 1   for rated mains voltage ≤ 150 Vrms   for rated mains voltage ≤ 300 Vrms   for rated mains voltage ≤ 600 Vrms I - IV I - IV I - III Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 891 Vpeak Input to Output Test Voltage, Method b*   VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,   Partial discharge < 5 pC VPR 1670 Vpeak Input to Output Test Voltage, Method a*   VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec,   Partial discharge < 5 pC VPR 1336 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec) VIOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure.   Case Temperature TS   Input Current** IS,INPUT   Output Power** PS, OUTPUT 175 400 1200 °C mA mW Insulation Resistance at TS, VIO = 500 V >109 Ω RS Unit *Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, IEC/ EN/DIN EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles. OUTPUT POWER – PS, INPUT CURRENT – IS ** Refer to the following figure for dependence of PS and IS on ambient temperature. 800 PS (mW) IS (mA) 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C HCPL-J314  Insulation and Safety Related Specifications Parameter Symbol HCPL-J314 Units Conditions Minimum External Air Gap (Clearance) L(101) 7.4 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap (Internal Clearance) 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current ( 5 V Input Forward Voltage VF 1.2 1.5 1.8 V IF = 10 mA 16 Temperature Coefficient of Input Forward Voltage DVF/DTA -1.6 mV/°C Input Reverse Breakdown Voltage BVR 5 V IR = 10 µA Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V  14 Switching Specifications (AC) Over recommended operating conditions unless otherwise specified.     Test Parameter Symbol Min. Typ. Max. Units    Conditions   Fig. Note Propagation Delay Time to High Output tPLH Level 0.1 0.2 0.7 µs Propagation Delay Time to Low Output tPHL Level 0.1 0.3 0.7 µs Propagation Delay Difference Between Any Two Parts or Channels PDD -0.5 0.5 µs Rg = 47 Ω, Cg = 3 nF, 10,11, 14 f = 10 kHz, 12,13, Duty Cycle = 50%, 14,17 f = 10 kHz, IF = 8 mA, VCC = 30 V 10 Rise Time tR 50 ns Fall Time tF 50 ns Output High Level Common Mode Transient Immunity |CMH| 25 35 kV/µs TA = 25°C, VCM = 1.5 kV 18 11 Output Low Level Common Mode Transient Immunity |CML| 25 35 kV/µs 18 12 Package Characteristics For each channel unless otherwise specified.     Test Parameter Symbol Min. Typ. Max. Units     Conditions Input-Output Momentary Withstand Voltage Fig. Note VISO 3750 Vrms TA = 25°C, RH < 50% for 1 min. 8,9 Output-Output Momentary Withstand VO-O Voltage 1500 Vrms 15 Input-Output Resistance RI-O 1012 Ω VI-O = 500 V 9 Input-Output Capacitance CI-O 1.2 pF Freq = 1 MHz Notes: 1. Derate linearly above 70°C free air temperature at a rate of 0.3 mA/°C. 2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.4 A. See Application section for additional details on limiting IOL peak. 3. Derate linearly above 85°C, free air temperature at the rate of 4.0 mW/°C. 4. Input power dissipation does not require derating. 5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%. 6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL 1577, each HCPL-J314 optocoupler is proof tested by applying an insulation test voltage ≥ 5000 Vrms for 1 second (leakage detection current limit II-O ≤ 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions. 11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the output will remain in the high state (i.e. Vo > 6.0 V). 12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. Vo < 1.0 V). 13. This load condition approximates the gate load of a 1200 V/25 A IGBT. 14. For each channel. The power supply current increases when operating frequency and Qg of the driven IGBT increases. 15. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together.  -0.5 -1.0 -1.5 -2.0 -25 0 25 50 75 100 125 0.36 0.34 0.32 0.30 -50 TA – TEMPERATURE – °C Figure 1. VOH vs. temperature. -25 0 0.42 0.41 0.40 0 25 50 75 100 125 0.465 0.460 0.455 0.450 0.445 0.440 -50 -25 0 25 50 75 100 125 1.0 0.8 0.6 0.4 ICCL ICCH 75 100 125 TA – TEMPERATURE – °C Figure 7. ICC vs. temperature. HCPL-J314 fig 07 ICC – SUPPLY CURRENT – mA 1.2 50 -6 0 0.2 0.4 0.6 IOH – OUTPUT HIGH CURRENT – A 20 15 10 5 0 0 100 200 300 400 500 600 700 IOL - OUTPUT LOW CURRENT - mA Figure 6. VOL vs. IOL. 1.2 25 -5 HCPL-J314 fig 05 1.4 0 -4 TA – TEMPERATURE – °C HCPL-J314 fig 04 -25 -3 25 Figure 5. IOL vs. temperature. 0.2 -2 HCPL-J314 fig 03 VOL - OUTPUT LOW VOLTAGE - V IOL – OUTPUT LOW CURRENT – A VOL – OUTPUT LOW VOLTAGE – V 0.43 -25 VOH -1 Figure 3. VOH vs. IOH. 0.470 Figure 4. VOL vs. temperature. ICC – SUPPLY CURRENT – mA 100 125 0 HCPL-J314 fig 02 TA – TEMPERATURE – °C  75 Figure 2. IOH vs. temperature. 0.44 0 -50 50 TA – TEMPERATURE – °C HCPL-J314 fig 01 0.39 -50 25 1.0 0.8 0.6 0.4 ICCL ICCH 0.2 0 10 15 20 25 VCC – SUPPLY VOLTAGE – V Figure 8. ICC vs. VCC. HCPL-J314 fig 08 30 IFLH – LOW TO HIGH CURRENT THRESHOLD – mA -2.5 -50 0.38 (VOH-VCC) – OUTPUT HIGH VOLTAGE DROP – V IOH – OUTPUT HIGH CURRENT – A (VOH-VCC) – HIGH OUTPUT VOLTAGE DROP – V 0.40 0 3.5 3.0 2.5 2.0 1.5 -50 -25 0 25 50 75 100 125 TA – TEMPERATURE – °C Figure 9. IFLH vs. temperature. HCPL-J314 fig 09 400 300 200 100 0 10 TPLH TPHL 15 20 25 300 200 100 0 30 500 TP – PROPAGATION DELAY – ns TP – PROPAGATION DELAY – ns 6 9 Figure 10. Propagation delay vs. VCC. TP – PROPAGATION DELAY – ns 350 TPLH TPHL 250 0 50 100 150 200 Rg – SERIES LOAD RESISTANCE – Ω 100 TPLH 0 TPHL 0 20 40 60 25 20 15 10 5 1.6 VF – FORWARD VOLTAGE – V Figure 16. Input current vs. forward voltage. 1.8 80 Cg – LOAD CAPACITANCE – nF HCPL-J314 fig 14 IF – FORWARD CURRENT – mA -25 0 25 50 75 100 125 HCPL-J314 fig 12 200 HCPL-J314 fig 13 HCPL-J314 fig 16 TPHL Figure 12. Propagation delay vs. temperature. 300 Figure 14. Propagation delay vs. Cg. 1.4 TPLH 35 Figure 13. Propagation delay vs. Rg. 0 1.2 100 TA – TEMPERATURE – °C 400 300 200 HCPL-J314 fig 11 400 10 18 Figure 11. Propagation delay vs. IF. HCPL-J314 fig 10 TP – PROPAGATION DELAY – ns 15 300 IF – FORWARD LED CURRENT – mA VCC – SUPPLY VOLTAGE – V 200 12 400 0 -50 VO - OUTPUT VOLTAGE - V TP – PROPAGATION DELAY – ns 400 100 30 25 20 15 10 5 0 -5 0 1 2 3 4 5 IF - FORWARD LED CURRENT - mA Figure 15. Transfer characteristics. 6 1 8 0.1 µF IF = 7 to 16 mA + 10 KHz – 500 Ω 50% DUTY CYCLE 2 + – 7 IF VCC = 15 to 30 V tr tf VO 3 6 90% 47 Ω 50% VOUT 3 nF 4 10% 5 tPLH tPHL Figure 17. Propagation delay test circuit and waveforms. VCM IF 5V + – 1 δt 0.1 µF A B δV 8 2 VO 6 4 5 VCC = 30 V VO – Figure 18. CMR test circuit and waveforms. 11 VOH SWITCH AT A: IF = 10 mA SWITCH AT B: IF = 0 mA + ∆t ∆t + – VO VCM = 1500 V VCM 0V 7 3 = VOL Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-J314 has a very low maximum VOL specification of 1.0 V. Minimizing Rg and the lead inductance from the HCPL-J314 to the IGBT gate and emitter (possibly by mounting the HCPL-J314 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 19. Care should be taken with such a PC board design to avoid routing the IGBT collector or HCPL-J314 +5 V 1 270 Ω CONTROL INPUT 74XXX OPEN COLLECTOR 8 0.1 µF 2 7 3 6 4 5 Figure 19. Recommended LED drive and application circuit for HCPL-J314. 12 emitter traces close to the HCPL-J314 input as this can result in unwanted coupling of transient signals into the input of HCPL-J314 and degrade performance. (If the IGBT drain must be routed near the HCPL-J314 input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-J314.) + - VCC = 15 V + HVDC Rg Q1 3-PHASE AC Q2 - HVDC Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 19 can be analyzed as a simple RC circuit with a voltage supplied by the HCPLJ314. Rg ≥ ­ VCC – VOL ————   IOLPEAK 24 V – 5 V = ­­­ ————       0.6A = 32 Ω The VOL value of 5 V in the previous equation is the VOL at the peak current of 0.6A. (See Figure 6). Step 2: Check the HCPL-J314 power dissipation and increase Rg if necessary. The HCPL-J314 total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO). PT = PE + PO PE = IF 6 VF 6 Duty Cycle PO = PO(BIAS) + PO(SWITCHING) = ICC 6 VCC + ESW (Rg,Qg) 6 f = (ICCBIAS + KICC 6 Qg 6 f) 6 VCC + ESW (Rg,Qg) 6 f where KICC 6 Qg 6 f is the increase in ICC due to switching and KICC is a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF (worst case) = 10 mA, Rg = 32 Ω, Max Duty Cycle = 80%, Qg = 100 nC, f = 20 kHz and TAMAX = 85°C: PE = 10 mA 6 1.8 V 6 0.8 = 14 mW PO = (3 mA + (0.001 mA/(nC 6 kHz)) 6 20 kHz 6 100 nC) 6 24 V + 0.4 µJ 6 20 kHz = 80 mW < 260 mW (PO(MAX) @ 85°C) The value of 3 mA for ICC in the previous equation is the max. ICC over entire operating temperature range. Since PO for this case is less than PO(MAX), Rg = 32 Ω is all right for the power dissipation. 13 Esw – ENERGY PER SWITCHING CYCLE – µJ Selecting the Gate Resistor (Rg) 4.0 Qg = 50 nC Qg = 100 nC Qg = 200 nC Qg = 400 nC 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 100 Rg – GATE RESISTANCE – Ω Figure 20. Energy dissipated in the HCPL-J314 and for each IGBT switching cycle. LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 21. The HCPL-J314 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 22. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 19), can achieve 10 kV/µs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. 8 1 CLEDP 2 3 1 7 2 6 CLEDN 4 3 5 8 CLEDP 7 6 CLEDN 4 Figure 21. Optocoupler input to output capacitance model for unshielded optocouplers. 5 Figure 22. Optocoupler input to output capacitance model for shielded optocouplers. HCPL-J314 fig 22 +5 V 8 1 2 + VSAT - CLEDP 7 0.1 µF + - VCC = 18 V ILEDP 3 6 CLEDN 4 5 SHIELD Rg *** *** * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING ÐdVCM/dt. + VCM Figure 23. Equivalent circuit for Figure 17 during common mode transient. 1 8 +5 V 2 Q1 1 8 +5 V 3 CLEDP CLEDN 7 2 6 3 5 4 CLEDP CLEDN 7 6 ILEDN 4 SHIELD Figure 24. Not recommended open collector drive circuit. 14 SHIELD 5 Figure 25. Recommended LED drive circuit for ultra-high CMR IPM dead time and propagation delay specifications. CMR with the LED On (CMRH) IPM Dead Time and Propagation Delay Specifications A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 8 mA provides adequate margin over the maximum IFigure 26. Minimum LED Skew for Zero Dead Time.Figure 27. Waveforms for Dead Time. of 5 mA to achieve 10 kV/µs CMR. The HCPL-J314 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time high and low side power transistors are off. Any overlap in Ql and Q2 conduction will result in large currents flowing through the power devices from the highvoltage to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 26. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD max, which is specified to be 500 ns over the operating temperature range of -40° to 100°C. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 23, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 24, can not keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMR1 performance. The alternative drive circuit which like the recommended application circuit (Figure 19), does achieve ultra high CMR performance by shunting the LED in the off state. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure 27. The maximum dead time for the HCPL-J314 is 1 µs (= 0.5 µs - (-0.5 µs)) over the operating temperature range of -40°C to 100°C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. ILED1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 ILED2 Q2 OFF tPHL MAX tPLH MIN PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 26. Minimum LED skew for zero dead time. HCPL-J314 fig 27 ILED1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 Q2 OFF ILED2 tPHL MIN tPHL MAX tPLH MIN tPLH MAX (tPHL-tPLH) MAX PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX) = PDD* MAX – PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 27. Waveforms for dead time.HCPL-J314 fig 28 For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2942EN AV02-0155EN - April 9, 2008