HCPL-M611-000E

HCPL-M600, HCPL-M601, HCPL-M611 Small Outline, 5 Lead, High CMR, High Speed, Logic Gate Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features These small outline high CMR, high speed, logic gate optocouplers are single channel devices in a five lead miniature footprint. They are electrically equivalent to the following Avago optocouplers (except there is no output enable feature): SO-5 Package Standard DIP SO-8 Package HCPL-M600 6N137 HCPL-0600 HCPL-M601 HCPL-2601 HCPL-0601 HCPL-M611 HCPL-2611 HCPL-0611 The SO-5 JEDEC registered (MO-155) package outline does not require “through holes” in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/μs for the HCPL-M601, and 10,000 V/μs for the HCPL-M611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from –40°C to 85°C allowing trouble free system performance. x Surface Mountable x Very Small, Low Profile JEDEC Registered Package Outline x Compatible with Infrared Vapor Phase Reflow and Wave Soldering Processes x Internal Shield for High Common Mode Rejection (CMR) HCPL-M601: 10,000 V/μs at VCM = 50 V HCPL-M611: 15,000 V/μs at VCM = 1000 V x High Speed: 10 Mbd x LSTTL/TTL Compatible x Low Input Current Capability: 5 mA x Guaranteed ac and dc Performance over Temperature: –40°C to 85°C x Safety and regulatory approvals: - UL recognized: 3750 Vac for 1 min. per U.L. (File No. 55361) - CSA component acceptance Notice #5 - IEC/EN/DIN EN 60747-5-2 approved for HCPL-M601/ M611 Option 060. x Lead Free Option Applications x x x x x x x x x Isolated Line Receiver Simplex/Multiplex Data Transmission Computer-Peripheral Interface Microprocessor System Interface Digital Isolation for A/D, D/A Conversion Switching Power Supply Instrument Input/Output Isolation Ground Loop Elimination Pulse Transformer Replacement CAUTION: The small device geometries inherent to the design of this bipolar component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The SO-5 JEDEC registered (MO-155) package outline does not require “through holes” in a PCB. This package occupies approximately one fourth the footprint area of the standard dual-in-line package. The lead profile is designed to be compatible with standard surface mount processes. The HCPL-M600/01/11 optically coupled gates combine a GaAsP light emitting diode and an integrated high gain photon detector. The output of the detector I.C. is an Open-collector Schottky-clamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/μs for the HCPL-M601, and 10,000 V/μs for the HCPL-M611. This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to 85°C allowing trouble free system performance. The HCPL-M600/01/11 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate, and are recommended for use in extremely high ground or induced noise environments. Ordering Information HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577. Option Part number HCPL-M600 HCPL-M601 HCPL-M611 RoHS Compliant Non RoHS Compliant -000E No option -500E #500 -000E No option -500E #500 -560E - Package SO-5 Surface Mount Gull Wing Tape& Reel UL 5000 Vrms/ IEC/EN/DIN EN 1 Minute rating 60747-5-2 Quantity X X 100 per tube X 1500 per reel X SO-5 100 per tube X X X X 1500 per reel X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 020 and Option 060 is not available. Example 1: HCPL-M600-500E to order product of Surface Mount SO-5 package in Tape and Reel packaging with RoHS compliant. Example 2: HCPL-M601 to order product of Surface Mount SO-5 package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 2 Outline Drawing (JEDEC MO-155) ANODE 1 4.4 ± 0.1 (0.173 ± 0.004) MXXX XXX 6 7.0 ± 0.2 (0.276 ± 0.008) VCC 5 VOUT CATHODE 3 4 GND 0.4 ± 0.05 (0.016 ± 0.002) 3.6 ± 0.1* (0.142 ± 0.004) 0.102 ± 0.102 (0.004 ± 0.004) 2.5 ± 0.1 (0.098 ± 0.004) 0.216 ± 0.038 (0.0085 ± 0.0015) 7° MAX. 0.71 MIN. (0.028) 1.27 BSC (0.050) MAX. LEAD COPLANARITY = 0.102 (0.004) DIMENSIONS IN MILLIMETERS (INCHES) * MAXIMUM MOLD FLASH ON EACH SIDE IS 0.15 mm (0.006) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. Land Pattern Recommendation Schematic 4.4 (0.17) + IF ICC 6 1 IO 5 1.3 (0.05) 2.5 (0.10) VCC VO – 4 3 GND HCPL-M601/11 SHIELD 2.0 (0.080) 0.64 (0.025) 8.27 (0.325) USE OF A 0.1 μF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN PINS 6 AND 4 (SEE NOTE 1). TRUTH TABLE (POSITIVE LOGIC) OUTPUT LED L ON H OFF Regulatory Information The HCPL-M600, HCPL-M601 and HCPL-M611 are approved by the following organizations: IEC/EN/DIN EN 60747-5-5 (Option 060 only) UL for HCPL-M601 and HCPL-M611 Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. CSA Approval under CSA Component Acceptance Notice #5, File CA 88324. 3 Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (External Clearance) L(101) 5 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 5 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060) Description Symbol Characteristic Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage d 150 Vrms for rated mains voltage d 300 Vrms I – IV I – III Climatic Classification 55/85/21 Pollution Degree (DIN VDE 0110/1.89) Unit 2 Maximum Working Insulation Voltage VIORM 560 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1050 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec, Partial discharge < 5 pC VPR 840 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini =10 sec) VIOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** TS IS, INPUT PS, OUTPUT 150 150 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS >109 : * Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/ EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles. ** Refer to the following figure for dependence of PS and IS on ambient temperature. Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Current, Low Level IFL* 0 250 μA Input Current, High Level IFH** 5 15 mA Supply Voltage, Output VCC 4.5 5.5 V Fan Out (RL = 1 kΩ) N 5 TTL Loads Output Pull-Up Resistor RL 330 4,000 Ω Operating Temperature TA -40 85 °C * The off condition can also be guaranteed by ensuring that VF(off ) ≤ 0.8 volts. ** The initial switching threshold is 5mA or less. It is recommended that 6.3mA to 10mA be used for best performance and to permit at least a 20% LED degradation guardband. 4 Absolute Maximum Ratings (No Derating Required up to 85°C) Parameter Abs. Max. Storage Temperature -55°C to +125°C Operating Temperature -40°C to +85°C Forward Input Current - IF (see Note 2) 20 mA Reverse Input Voltage - VR 5V Supply Voltage - VCC (1 Minute Maximum) 7V Output Collector Current - IO 50 mA Output Collector Power Dissipation 85 mW Output Collector Voltage - VO (Selection for higher output voltages up to 20 V is available) 7V Infrared and Vapor Phase Reflow Temperature see below Solder Reflow Thermal Profile 300 TEMPERATURE (°C) PREHEATING RATE 3°C + 1°C/–0.5°C/SEC. REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK TEMP. 245°C PEAK TEMP. 240°C PEAK TEMP. 230°C 200 2.5°C ± 0.5°C/SEC. SOLDERING TIME 200°C 30 SEC. 160°C 150°C 140°C 30 SEC. 3°C + 1°C/–0.5°C 100 PREHEATING TIME 150°C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 50 0 100 150 200 250 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax 20-40 SEC. 260 +0/-5 °C 217 °C RAMP-UP 3 °C/SEC. MAX. 150 - 200 °C RAMP-DOWN 6 °C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. tL 25 t 25 °C to PEAK TIME Note: Non-halide flux should be used. 5 TIME WITHIN 5 °C of ACTUAL PEAK TEMPERATURE 60 to 150 SEC. NOTES: THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200 °C, Tsmin = 150 °C Insulation Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap (Clearance) L(IO1) ≥5 mm Measured from input terminals to output terminals Min. External Tracking Path (Creepage) L(IO2) ≥5 mm Measured from input terminals to output terminals 0.08 mm Through insulation distance conductor to conductor 175 V DIN IEC 112/VDE 0303 Part 1 Min. Internal Plastic Gap (Clearance) Tracking Resistance CTI Isolation Group (per DIN VDE 0109) IIIa Material Group DIN VDE 0109 Electrical Specifications Over recommended temperature (TA = -40°C to 85°C) unless otherwise specified. (See note 1.) Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Input Threshold Current ITH 2 5 mA VCC = 5.5 V, IO ≥13 mA, VO = 0.6 V 13 High Level Output Current IOH 5.5 100 μA VCC = 5.5 V, VO = 5.5 V IF = 250 μA 1 Low Level Output Voltage VOL 0.4 0.6 V VCC = 5.5 V, IF = 5 mA, IOL (Sinking) = 13 mA 2, 4, 5, 13 High Level Supply Current ICCH 4 7.5 mA VCC = 5.5 V, IF = 0 mA, Low Level Supply Current ICCL 6 10.5 mA VCC = 5.5 V, IF = 10 mA, Input Forward Voltage VF 1.75 V 1.4 3 1.5 1.3 1.85 IF = 10 mA 5 IR = 10 μA Input Reverse Breakdown Voltage BVR Input Capacitance CIN 60 pF Input Diode Temperature Coefficient ∆VF/∆TA -1.6 mV/°C Input-Output Insulation VISO Resistance (Input-Output) RI-O 1012 Ω VI-O = 500 V 3 Capacitance (Input-Output) CI-O 0.6 pF f = 1 MHz 3 *All typicals at TA = 25°C, VCC = 5 V. 6 TA = 25°C, IF=10 mA Note 3750 VRMS VF = 0V, f = 1 MHz IF = 10 mA RH ≤ 50%, t = 1 min. 12 3, 4 Switching Specifications Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified. Parameter Symbol Device HCPL- Min. Typ.* Max. Unit 20 48 75 ns Propagation Delay Time to High Output Level tPLH Propagation Delay Time to Low Output Level tPHL Propagation Delay Skew tPSK Pulse Width Distortion |tPHL - tPLH| 3.5 Output Rise Time (10%-90%) trise 24 Output Fall Time (10%-90%) tfall 10 Test Conditions TA = 25°C 100 25 50 75 RL = 350 Ω CL = 15 pF TA = 25°C |CMH| Common |CMH| Mode Transient Immunity at Low Output Level Note 6, 7 5 8 6, 7 100 Common Mode Transient Immunity at High Output Level Fig. 6 8 40 10, 11 35 9 10 10 10 M600 10,000 V/μs VCM = 10 V VO(min) = 2 V M601 5,000 10,000 VCM = 50 V M611 10,000 15,000 VCM = 1000 V RL = 350 Ω IF = 0 mA TA = 25°C 10,000 VCM = 10 V VO(max) = 0.8 V RL = 350 Ω IF = 7.5 mA TA = 25°C M600 M601 5,000 10,000 VCM = 50 V M611 10,000 15,000 VCM = 1000 V 11 7, 9 11 8, 9 *All typicals at TA = 25°C, VCC = 5 V. Notes: 1. Bypassing of the power supply line is required with a 0.1 μF ceramic disc capacitor adjacent to each optocoupler. The total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. 3. Device considered a two terminal device: pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. 4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (Leakage detection current limit, II-O ≤ 5 μA). 5. The tPLH propagation delay is measured from 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 6. The tPHL propagation delay is measured from 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 7. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VOUT > 2.0 V). 8. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VOUT > 0.8 V). 9. For sinusoidal voltages, (|dVCM|/dt)max = SfCMVCM(p-p). 10. See application section; “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information. 11. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the worst case operating condition range. 7 10 5 0 -60 -40 -20 0 20 40 60 80 100 100 0.5 VCC = 5.5 V IF = 5.0 mA 0.4 IO = 12.8 mA IO = 16 mA 0.3 IO = 6.4 mA 0.2 IO = 9.6 mA 0.1 -60 -40 -20 TA – TEMPERATURE – °C 6 VO – OUTPUT VOLTAGE – V 0 20 40 60 10 IF + VF – 1.0 0.1 0.01 0.001 1.10 80 100 1.20 1 RL = 350 Ω VCC 6 0.1μF BYPASS 3 RL 5 RL = 1 KΩ *CL INPUT MONITORING NODE RL = 4 KΩ 1 3 GND 4 RM 0 1 2 3 4 6 5 IF – FORWARD INPUT CURRENT – mA *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 4. Output Voltage vs. Forward Input current. IF = 7.5 mA INPUT IF IF = 3.75 mA IOL – LOW LEVEL OUTPUT CURRENT – mA tPHL OUTPUT VO 80 VCC = 5.0 V VOL = 0.6 V 60 IF = 10 mA, 15 mA Figure 6. Test Circuit for tPHL and tPLH. 40 IF = 5.0 mA 20 0 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C Figure 5. Low Level Output Current vs. Temperature. 8 1.50 +5 V IF 2 1.40 Figure 3. Input Diode Forward Characteristic. PULSE GEN. ZO = 50 Ω tf = tr = 5 ns VCC = 5 V TA = 25 °C 1.30 1.60 VF – FORWARD VOLTAGE – VOLTS Figure 2. Low Level Output Voltage vs. Temperature. 4 0 TA = 25°C TA – TEMPERATURE – °C Figure 1. High Level Output Current vs. Temperature. 5 IF – FORWARD CURRENT – mA VCC = 5.5 V VO = 5.5 V IF = 250 μA VOL – LOW LEVEL OUTPUT VOLTAGE – V IOH – HIGH LEVEL OUTPUT CURRENT – μA 15 tPLH 1.5 V OUTPUT VO MONITORING NODE 80 tPLH , RL = 4 KΩ tPHL , RL = 350 Ω 1 KΩ 60 4 KΩ tPLH , RL = 1 KΩ 40 tPLH , RL = 350 Ω 20 0 -60 -40 -20 0 20 40 Figure 7. Propagation Delay vs. Temperature. tr, tf – RISE, FALL TIME – ns 75 tPLH , RL = 350 Ω 60 tPLH , RL = 1 KΩ 45 tPHL , RL = 350 Ω 1 KΩ 4 KΩ 5 7 11 13 15 VCC = 5.0 V IF = 7.5 mA 20 10 RL = 350 kΩ 0 RL = 1 kΩ -10 -60 -40 -20 0 +5 V VCC 6 A 5 VFF 290 60 3 RL = 1 kΩ GND 0.1 μF BYPASS 350 Ω OUTPUT VO MONITORING NODE 4 40 RL = 350 Ω _ + PULSE GENERATOR ZO = 50 Ω TA – TEMPERATURE – °C VCM (PEAK) VCM Figure 10. Rise and Fall Time vs. Temperature. 0V VO 5V dVF/dT – FORWARD VOLTAGE TEMPERATURE COEFFICIENT – mV/°C VO 0.5 V SWITCH AT A: IF = 0 mA CMH VO (MIN.) SWITCH AT B: IF = 7.5 mA VO (MAX.) CML -2.4 -2.2 Figure 11. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. -2.0 -1.8 -1.6 -1.4 -1.2 0.1 1 10 40 100 IF – PULSE INPUT CURRENT – mA Figure 12. Temperature Coefficient for Forward Voltage vs. Input Current. 60 80 100 Figure 9. Pulse Width Distortion vs. Temperature. B RL = 4 kΩ 20 20 IF tRISE tFALL 1 300 RL = 4 kΩ 30 TA – TEMPERATURE – °C Figure 8. Propagation Delay vs. Pulse Input Current. RL = 350 Ω, 1 kΩ, 4 kΩ 0 -60 -40 -20 0 20 40 60 80 100 9 9 40 IF – PULSE INPUT CURRENT – mA TA – TEMPERATURE – °C VCC = 5.0 V IF = 7.5 mA tPLH , RL = 4 KΩ 90 30 80 100 60 VCC = 5.0 V TA = 25°C PWD – PULSE WIDTH DISTORTION – ns 105 VCC = 5.0 V IF = 7.5 mA tP – PROPAGATION DELAY – ns tP – PROPAGATION DELAY – ns 100 Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 7). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 15, if the in- puts of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 11 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 16 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and input current, and power supply ranges. ITH – INPUT THRESHOLD CURRENT – mA 6 5 VCC = 5.0 V VO = 0.6 V VCC1 5V 6 IF VF 4 2 1 20 40 60 * DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT. 80 100 TA – TEMPERATURE – °C Figure 13. Input Threshold Current vs. Temperature. Figure 14. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit. DATA IF INPUTS 50% CLOCK 1.5 V VO IF DATA 50% OUTPUTS VO 1.5 V tPSK CLOCK tPSK Figure 15. Illustration of Propagation Delay Skew – tPSK. GND 2 SHIELD RL = 4 kΩ 0 0.1 μF BYPASS 3 GND 1 0 -60 -40 -20 5 1 *D1 RL = 350 Ω RL = 1 kΩ 2 1 VCC 2 390 Ω 470 4 3 5V tPSK Figure 16. Parallel Data Transmission Example. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0562EN AV02-0941EN - February 23, 2010