HDSP-2133

Data Sheet HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications Description Features The Broadcom® HDSP-2131 (yellow), HDSP-2179 (orange), HDSP-2132 (high efficiency red) and the HDSP-2133 (green) are eight-digit, 5 × 7 dot matrix, alphanumeric displays. The 5.0-mm (0.2-in.) high characters are packaged in a standard 7.64-mm (0.30-in.) 32-pin DIP. The on-board CMOS IC can decode 128 ASCII characters, which are permanently stored in ROM. In addition, 16 programmable symbols may be stored in an on-board RAM. Seven brightness levels provide versatility in adjusting the display intensity and power consumption. The HDSP-213x and HDSP-2179 are designed for standard microprocessor interface techniques. The display and special features are accessed through a bidirectional 8-bit data bus. These features make the HDSP-213x and HDSP-2179 ideally suited for applications where a hermetic, low power alphanumeric display is required.        Devices  Yellow High Efficiency Red High Performance Green Orange HDSP-2131 HDSP-2132 HDSP-2133 HDSP-2179       Wide operating temperature range: –55°C to +85°C Smart alphanumeric display – On-board CMOS IC – Built-in RAM – ASCII decoder – LED drive circuitry 128 ASCII character set 16 user-definable characters Programmable features: – Individual character flashing – Full display blinking – Multilevel dimming and blanking – Self-test – Clear function Read/write capability Full TTL compatibility HDSP-2131, HDSP-2133, and HDSP-2179 are usable in night vision lighting applications Categorized for luminous intensity HDSP-2131 and HDSP-2133 are categorized for color Excellent ESD protection Wave solderable X-Y stackable RoHS compliant CAUTION! Observe standard CMOS handling precautions with the HDSP-2131, HDSP-2132, HDSP-2133, and HDSP-2179. Broadcom AV02-0190EN September 4, 2019 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Package Dimensions 42.72 (1.68) 5.33 TYP. (0.210) 5.18 REF. (0.204) 2.67 TYP. (0.105) 9.91 (0.39) 0.38 TYP. (0.015) PIN 17 4.83 (0.190) 4.96 (0.195) 7.62 (0.300) 2.85 (0.112) PART NUMBER DATE CODE LIGHT INTENSITY CATEGORY COLOR BIN (NOTE 3) PIN #1 IDENTIFIER 6.35 MAX. (0.250) HDSP-XXXX YYWW X 1.78 TYP. (0.070) Z SEATING PLANE 6.00 (0.24) 12.70 (0.50) 2.29 TYP. (0.090) 0.51 TYP. (0.020) 1.27 TYP. (0.050) 2.54 TYP. (0.100) NON-ACCUM. HDSP-213X/2179 PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FUNCTION CLS CLK WR CE RST RD NO PIN NO PIN NO PIN NO PIN D0 D1 D2 D3 NC VDD PIN # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FUNCTION GND (SUPPLY) GND (LOGIC) D4 D5 D6 D7 NO PIN NO PIN NO PIN NO PIN FL A0 A1 A2 A3 A4 NOTES: 1. ALL DIMENSIONS ARE IN mm (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ISr 0.30 mm (0.015 INCH). 3. FOR GREEN AND YELLOW DEVICES ONLY. 4. LEADS ARE COPPER ALLOY, SOLDER DIPPED. Absolute Maximum Ratings Parameter Supply Voltage, VDD to Grounda Values –0.3V to 7.0V Operating Voltage, VDD to Groundb 5.5V Input Voltage, Any Pin to Ground –0.3V to VDD + 0.3V Free Air Operating Temperature Range, TA –55°C to +85°C Storage Temperature, TS –55°C to +100°C CMOS IC Junction Temperature, TJ (IC) Soldering Temperature (1.59 mm [0.063 in.] below Body) +150°C Solder Dipping 260°C for 5 seconds Wave Soldering 250°C for 3 seconds ESD Protection at 1.5 kΩ, 100 pF VZ = 4 kV (each pin) a. Maximum voltage is with no LEDs illuminated. b. 20 dots ON in all locations at full brightness. Broadcom AV02-0190EN 2 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Character Set D7 D6 0 0 0 D5 BIT S D3 0 0 0 0 D4 D2 D1 D0 COLUMN ROW Broadcom 0 0 0 0 0 1 1 1 0 1 1 0 2 0 1 0 1 3 0 1 0 0 4 0 1 1 1 5 1 X 1 0 6 X 1 7 X 8–F 0000 0 16 0001 1 U S E R 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F D E F I N E D C H A R A C T E R S AV02-0190EN 3 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Recommended Operating Conditions Parameter Symbol Minimum Nominal Maximum Units VDD 4.5 5.0 5.5 V Supply Voltage Electrical Characteristics over Operating Temperature Range 4.5V < VDD < 5.5V (unless otherwise specified). Max.b Units Test Conditions — +10.0 µA VIN = 0 to VDD, pins CLK, D0 to D7, A0 to A4 11 18 30 µA VIN = 0 to VDD, pins RST, CLS, WR, RD, CE, FL — 0.5 1.5 2.0 mA VIN = VDD IDD(V) — 200 255 330 mA "V" on in all 8 locations IDD(#) — 300 370 430 mA "#" on in all 8 locations Input Voltage High VIH 2.0 — — VDD + 0.3V V VDD = 5.5V Input Voltage Low VIL GND – 0.3V — — 0.8 V VDD = 4.5V Output Voltage High VOH 2.4 — — V VDD = 4.5V, IOH = –40 µA Output Voltage Low D0 to D7 VOL — — — 0.4 V VDD = 4.5V, IOL = 1.6 mA — — — 0.4 V VDD = 4.5V, IOL = 40 µA — 11 — Parameter 25°C Typ.a 25°C Max.a Symbol Min. Input Leakage (Input without Pullup) II –10.0 — Input Current (Input with Pullup) IIP –30.0 IDD (BLK) IDD Blank IDD 8 digits 12 Dots/Characterc IDD 8 digits 20 Dots/Characterc Output Voltage Low CLK Thermal Resistance IC Junction-to-Pin RθJ-PIN °C/W a. VDD = 5.0V. b. Maximum IDD occurs at –55°C. c. Average IDD measured at full brightness. See Table 2 for IDD at lower brightness levels. Peak IDD = 28/15 × Average IDD (#). Broadcom AV02-0190EN 4 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Optical Characteristics at 25°C1 VDD = 5.0V at full brightness. High Efficiency Red HDSP-2132 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Symbol Minimum Typical Units IV 2.5 7.5 mcd PEAK — 635 nm d — 626 nm Symbol Minimum Typical Units IV 2.5 7.5 mcd PEAK — 600 nm d — 602 nm Symbol Minimum Typical Units IV 2.5 7.5 mcd PEAK — 583 nm d — 585 nm Symbol Minimum Typical Units IV 2.5 7.5 mcd PEAK — 568 nm d — 574 nm Orange HDSP-2179 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength Yellow HDSP-2131 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength High Performance Green HDSP-2133 Description Luminous Intensity Character Average (#) Peak Wavelength Dominant Wavelength 1. Broadcom Refers to the initial case temperature of the device immediately prior to the light measurement. AV02-0190EN 5 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet AC Timing Characteristics over Temperature Range VDD = 4.5V to 5.5V unless otherwise specified. Reference Number 1 Symbol tACC Min.a Description Display Access Time ns Write 210 Read 230 2 tACS Address Setup Time to Chip Enable 3 tCE Chip Enable Active Timeb, c Units 10 ns ns Write 140 Read 160 4 tACH Address Hold Time to Chip Enable 20 ns 5 tCER Chip Enable Recovery Time 60 ns 6 tCES Chip Enable Active Prior to Rising Edge ofa, b ns Write 140 Read 7 tCEH Chip Enable Hold Time to Rising Edge of Read/Write 8 tW 9 160 0 ns Write Active Timeb, c 100 ns tWD Data Valid Prior to Rising Edge of Write Signal 50 ns 10 tDH Data Write Hold Time 20 ns 11 tR Chip Enable Active Prior to Valid Data 160 ns 12 tRD Read Active Prior to Valid Data 75 ns 13 tDF Read Data Float Delay 10 ns — tRC Reset Active Timed 300 ns Signalb, c a. Worst case values occur at an IC junction temperature of 150°C. b. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. c. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. d. The display must not be accessed until after three clock pulses (110 µs minimum using the internal refresh clock) after the rising edge of the reset line. Broadcom AV02-0190EN 6 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet AC Timing Characteristics Over Temperature Range VDD = 4.5V to 5.5V unless otherwise specified. Symbol Description 25°C Typical Minimum Units FOSC Oscillator Frequency 57 28 kHz FRFa Display Refresh Rate 256 128 Hz FFLb Character Flash Rate 2 1 Hz tSTc Self Test Cycle Time 4.6 9.2 Sec a. FRF = FOSC/224. b. FFL = FOSC/28,672. c. tST = 262,144/FOSC. Write Cycle Timing Diagram 1 A0 -A 4 FL 4 2 3 2 5 CE 6 7 8 WR 10 9 D0 -D 7 INPUT PULSE LEVELS: 0.6 V to 2.4 V Broadcom AV02-0190EN 7 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Read Cycle Timing Diagram 1 A0 -A 4 FL 4 2 2 5 3 CE 6 7 11 RD 12 13 D0 -D 7 INPUT PULSE LEVELS: 0.6 V to 2.4 V OUTPUT REFERENCE LEVELS: 0.6 V to 2.2 V OUTPUT LOADING = 1 TTL LOAD AND 100 pF Character Font Relative Luminous Intensity vs. Temperature 2.85 TYP. (0.112) C2 0.76 TYP. (0.030) C3 C4 4.0 C5 R1 R2 R3 R4 R5 R6 0.254 TYP. (0.010) R7 0.65 TYP. (0.026) NOTE: NOT TO SCALE Broadcom 4.83 TYP. (0.190) RELATIVE LUMINOUS INTENSITY (NORMALIZED TO 1 AT 25 qC) C1 3.5 HDSP-2132 (HER) -2179 (ORANGE) HDSP-2131 (YELLOW) HDSP-2133 (GREEN) 3.0 2.5 2.0 1.5 1.0 0.5 0 -55 -35 -15 5 25 45 65 85 105 TA – AMBIENT TEMPERATURE – qC AV02-0190EN 8 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Electrical Description Pin Function Description RESET (RST, Pin 5) Reset initializes the display. FLASH (FL, Pin 27) FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3 to A4. ADDRESS INPUTS (A0 to A4, Pins 28 to 32) Each location in memory has a distinct address. Address inputs (A0 to A2) select a specific location in the Character RAM, the Flash RAM, or a particular row in the UDC (User-Defined Character) RAM. A3 to A4 select which section of memory is accessed. See Table 1 for the logic levels needed to access each section of memory. CLOCK SELECT (CLS, Pin 1) This input select s either an internal (CLS = 1) or external (CLS = 0) clock source. CLOCK INPUT/OUTPUT (CLK, Pin 2) Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. WRITE (WR, Pin 3) Data is written into the display when the WR input is low and the CE input is low. CHIP ENABLE (CE, Pin 4) This input must be at a logic low to read data from or write data to the display and must go high between each read and write cycle. READ (RD, Pin 6) Data is read from the display when the RD input is low and the CE input is low. DATA Bus (D0 to D7, Pins 11 to 14, 19 to 22) The Data bus reads from or writes to the display. GND(SUPPLY) (Pin 17) This is the analog ground for the LED drivers. GND(LOGIC) (Pin 18) This is the digital round for internal logic. VDD(POWER) (Pin 16) This is the positive power supply input. Table 1: Logic Levels to Access Memory FL A4 A3 Section o f Memory A2 A1 A0 0 X X Flash RAM Character Address 1 0 0 UDC Address register Don't Care 1 0 1 UDC RAM Row Address 1 1 0 Control Word register Don't Care 1 1 1 Character RAM Character Address Broadcom AV02-0190EN 9 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Figure 1: HDSP-213x/HDSP-2179 Internal Block Diagram A3 A4 FL CE UDC ADDR REGI STER EN RD WR D 0- D 7 U DC ADDR CLR PRE SET A3 A4 FL CE UDC RAM A3 A4 FL CE RD WR D 0- D 7 A 0- A 2 A3 A4 FL CE 8x8 EN CHARACTER RD D 0- D 6 RAM WR D7 D 0- D 7 A 0- A 2 RESET CHAR ADDR FL CE A3 A4 FL CE RST EN FLASH RD DATA WR FLASH D0 RAM A 0- A 2 RESET CHAR ADDR RESET CON TROL W ORD REGI STER EN 0 I N TEN SI TY RD 1 WR 2 FLASH D 0- D 7 3 BLI N K 4 RESET SELF TEST 6 SELF TEST 7 RESULT CLR1 OCS Broadcom DECODER( *) EN D 0- D 6 ROW SEL SELF TEST DOT DATA DOT DATA DOT DRI VERS 8 5x 7 LED CHARACTERS TI M I N G ROW DRI VERS SELF TEST SELF TEST IN VI SUAL TEST ROM TEST SELF TEST CLR START TI M I N G TEST OK FLASH TEST OK CLR2 CLK CLS EN RD WR DOT D 0- D 4 A0- A2 DATA U DC ADDR ROW SET EN D 0- D 4 I N TEN SI TY FLASH BLI N K RESET CLOCK CHAR ADDR TI M I N G AN D CON TROL ROW SET TI M I N G AV02-0190EN 10 HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP-213x/HDSP-2179 display. The CMOS IC consists of an 8-byte Character RAM, an 8-bit Flash RAM, a 128-character ASCII decoder, a 16-character UDC RAM, a UDC Address register, a Control Word register, and the refresh circuitry necessary to synchronize the decoding and driving of eight 5 × 7 dot matrix characters. The major user accessible portions of the display are listed below. Character RAM This RAM stores either ASCII character data or a UDC RAM address. Flash RAM This is a 1 × 8 RAM which stores Flash data. User-Defined Character RAM (UDC RAM) This RAM stores the dot pattern for custom characters. User-Defined Character Address register (UDC Address register) This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. Control Word register This register allows the user to adjust the display brightness, flash individual characters, blink, self test, or clear the display. Character RAM Figure 2 shows the logic levels needed to access the HDSP-213x/HDSP-2179 Character RAM. During a normal access, the CE = "0" and either RD = "0" or WR = "0". However, erroneous data may be written into the Character RAM if the address lines are unstable when CE = "0" regardless of the logic levels of the RD or WR lines. Address lines A0 to A2 select the location in the Character RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 differentiates between an ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0 to D6 are used to input ASCII data and D0 to D3 are used to input a UDC address. Figure 2: Logic Levels to Access the Character RAM RST 1 CE 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL 1 A4 1 A3 A2 A1 A0 CHARACTER ADDRESS 1 000 = LEFT MOST 111 = RIGHT MOST CHARACTER RAM ADDRESS D7 D6 D5 0 D4 D3 D2 D1 D0 128 ASCII CODE 1 X X X UDC CODE CHARACTER RAM DATA FORMAT DIG 0 DIG 1 DIG 2 DIG 3 DIG 4 DIG 5 DIG 6 DIG 7 000 001 010 011 100 101 110 111 SYMBOL IS ACCESSED IN LOCATION SPECIFIED BY THE CHARACTER ADDRESS ABOVE DISPLAY 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Broadcom AV02-0190EN 11 HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address register. The UDC Address register is 8 bits wide. The lower four bits (D0 to D3) select one of the 16 UDC locations. The upper four bits (D4 to D7) are not used. When the UDC address has been stored in the UDC Address register, the UDC RAM can be accessed. To completely specify a 5 × 7 character requires eight write cycles. One cycle stores the UDC RAM address in the UDC Address register. Seven cycles store dot data in the UDC RAM. Data is entered by rows. One cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an "F." A0 to A2 select the row to be accessed, and D0 to D4 transmit the row dot data. The upper three bits (D5 to D7) are ignored. D0 (least significant bit) corresponds to the right most column of the 5×7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 × 7 matrix. Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications Figure 3: Logic Levels to Access a UDC Character RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL A4 A3 A2 A1 A0 1 0 0 X X X UDC ADDRESS REGISTER ADDRESS D7 D6 D5 D4 X X X X D3 D2 D1 D0 UDC CODE UDC ADDRESS REGISTER DATA FORMAT RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL A4 A3 1 0 1 A2 A1 A0 ROW SELECT 000 = ROW 1 110 = ROW 7 UDC RAM ADDRESS D7 D6 D5 X X X D4 D3 D2 D1 D0 DOT DATA UDC RAM DATA FORM AT C O L 1 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE C O L 5 Figure 4: Data to Load "F" into the UDC RAM C C C O O O L L L 1 2 3 D4 D3 D2 1 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 IGNORED C O L 4 D1 1 0 0 1 0 0 0 C O L 5 D0 1 0 0 0 0 0 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 UDC CHARACTER • • • • • • • • • • • • • • HEX CODE 1F 10 10 1D 10 10 10 0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED Broadcom AV02-0190EN 12 HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications Flash RAM Control Word Register Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input selects the Flash RAM. Address lines A3 to A4 are ignored. Address lines A0 to A2 select the location in the Flash RAM to store the attribute. D0 stores or removes the flash attribute. D0 = "1" stores the attribute, and D0 = "0" removes the attribute. Figure 6 shows how to access the Control Word register. This is an eight bit register that performs five functions. They are brightness control, Flash RAM control, blinking, self-test and clear. Each function is independent of the others. However, all bits are updated during each Control Word write cycle. When the attribute is enabled through bit 3 of the Control Word and a "1" is stored in the Flash RAM, the corresponding character will flash at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the flash rate can be calculated by dividing the clock frequency by 28,672. Figure 5: Logic Levels to Access the Flash RAM RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED A4 A3 0 X X A2 A1 A0 CHARACTER ADDRESS Bits 0 to 2 of the Control Word adjust the brightness of the display. Bits 0 to 2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0 to 2 also vary the average value of IDD. IDD can be calculated at any brightness level by multiplying the percent brightness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Figure 6: Logic Levels to Access the Control Word Register CONTROL SIGNALS FL Brightness (Bits 0 to 2) 000 = LEFT MOST 111 = RIGHT MOST RST CE 1 0 WR 0 0 1 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FLASH RAM ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X 0 1 FLASH RAM DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE REMOVE FLASH AT SPECIFIED DIGIT LOCATION STORE FLASH AT SPECIFIED DIGIT LOCATION FL A4 A3 A2 A1 A0 1 1 0 X X X CONTROL WORD ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 C S S BL F B B B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 DISABLE FLASH 1 ENABLE FLASH 0 1 0 1 0 1 0 1 100% 80% 53% BRIGHTNESS 40% CONTROL 27% LEVELS 20% 13% 0% 0 DISABLE BLINKING 1 ENABLE BLINKING 0 1 X NORMAL OPERATION; X IS IGNORED X START SELF TEST; RESULT GIVEN IN X X = 0 FAILED X = 1 PASSED 0 NORMAL OPERATION 1 CLEAR FLASH AND CHARACTER RAMS CONTROL WORD DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Broadcom AV02-0190EN 13 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Table 2: Current Requirements at Different Brightness Levels Symbol IDD (V) D2 D1 D0 % Brightness Units 0 0 0 100 200 mA 0 0 1 80 160 mA 0 1 0 53 106 mA 0 1 1 40 80 mA 1 0 0 27 54 mA 1 0 1 20 40 mA 1 1 0 13 26 mA Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a "1," the output of the Flash RAM is checked. If the content of a location in the Flash RAM is a "1," the associated digit will flash at approximately 2 Hz. For an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. If the flash enable bit of the Control Word is a "0," the content of the Flash RAM is ignored. To use this function with multiple display systems, see Display Reset. Blink Function (Bit 4) Bit 4 of the Control Word is used to synchronize blinking of all eight digits of the display. When this bit is a "1", all eight digits of the display will blink at approximately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems see Display Reset. Self-Test Function (Bits 5, 6) Bit 6 of the Control Word register initiates the self-test function. Results of the internal self-test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = "1" indicates a passed self test, and bit 5 = "0" indicates a failed self-test. Setting bit 6 to a logic 1 will start the self-test function. The built-in self-test function of the IC consists of two internal routines that exercise major portions of the IC and illuminates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum Broadcom 25°C Typ. on the output. If the checksum agrees with the correct value, bit 5 is set to "1." The second routine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approximately 2 seconds. During the self-test function, the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 kHz, then the time to execute the self-test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self-test function, the Character RAM is loaded with blanks, the Control Word register is set to zeros except for bit 5, and the Flash RAM is cleared and the UDC Address register is set to all ones. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a “1” will start the clear function. Three clock cycles (110 µs minimum. using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been completed, bit 7 will be reset to a "0." The ASCII character code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with "0"s. The UDC RAM, UDC Address register, and the remainder of the Control Word are unaffected. AV02-0190EN 14 HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Display Reset Figure 7 shows the logic levels needed to reset the display. The display should be reset on power- up. The external reset clears the Character RAM, Flash RAM, and Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 µs minimum using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word register are loaded with all "0"s. The UDC RAM and UDC Address register are unaffected. All displays that operate with the same clock source must be simultaneously reset to synchronize the flashing and blinking functions. Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications The inputs to the CMOS IC are protected against static discharge and input current latchup. However, for best results, use standard CMOS handling precautions. Prior to use, the HDSP-213X should be stored in antistatic packages or conductive material. During assembly, a grounded conductive work area should be used and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided because they are prone to static charge buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (VIN < ground) or to a voltage higher than VDD (VIN > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, connect unused inputs either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display. Transient input voltages should be eliminated. Figure 7: Logic Levels to Reset the Display CE WR RD FL 0 1 X X X A4 -A 0 D7 -D 0 X Figure 8: Maximum Power Dissipation vs. Ambient Temperature Derating Based on TJMAX = 125°C X 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE NOTE: IF RST, CE, AND WR ARE LOW, UNKNOWN DATA MAY BE WRITTEN INTO THE DISPLAY. Mechanical and Electrical Considerations The HDSP-213x/HDSP-2179 is a 32-pin dual-inline package with 24 external pins, that can be stacked horizontally and vertically to create arrays of any size. The HDSP-213x/HDSP-2179 is designed to operate continuously from –55° to +85°C with a maximum of 20 dots ON per character. Illuminating all 35 dots at full brightness is not recommended. The HDSP-213x/HDSP-2179 is assembled by die attaching and wire bonding 280 LED chips and a CMOS IC to a ceramic sub-strate. A glass window is placed over the ceramic substrate creating an air gap over the LED wire bonds. A second glass window creates an air gap over the CMOS IC. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering and visual inspection of the IC. 4.0 PD – POWER DISSIPATION – W RST 3.0 2.0 RTJ-A = 30 qC/W 1.0 0 25 35 45 55 65 75 85 95 105 TA – AMBIENT TEMPERATURE – qC Thermal Considerations The HDSP-213x/HDSP-2179 has been designed to provide a low thermal resistance path from the CMOS IC to the 24 package pins. This heat is then typically conducted through the traces of the user's printed circuit board to free air. For most applications, no additional heatsinking is required. The maximum operating IC junction temperature is 150°C. The maximum IC junction temperature can be calculated using the following equation: TJ(IC) MAX = TA + (PDMAX) (RθJ-PIN + RθPIN-A) Broadcom AV02-0190EN 15 Where PDMAX = (VDDMAX) × (IDDMAX) IDDMAX = 370 mA with 20 dots ON in eight character locations at 25°C ambient. This value is from the Electrical Characteristics table. PDMAX = (5.5V) × (0.370A) = 2.04 W Ground Connections Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the analog ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long interconnects between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. The logic ground should be connected to the same ground potential as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground that can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the analog ground can vary from –0.3V to +0.3V with respect to the logic ground. Voltage below –0.3V can cause all dots to be on. Voltage above +0.3V can cause dimming and dot mismatch. ESD Susceptibility These displays have ESD susceptibility ratings of CLASS 3 per DOD-STD-1686 and CLASS B per MIL-STD-883C. Soldering and Post Solder Cleaning Instructions for the HDSP-213x/HDSP-2179 The HDSP-213x/HDSP-2179 may be hand soldered or wave soldered with lead-free solder. When hand soldering, use an electronically temperature-controlled and securely grounded soldering iron. For best results, the iron tip temperature should be set at 315°C (600°F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245°C ± 5°C (473°F ± Broadcom Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications 9°F), and dwell in the wave should be set between 1½ to 3 seconds for optimum soldering. The preheat temperature should not exceed 105°C (221°F) as measured on the solder side of the PC board. Proper handling is imperative to avoid excessive thermal stresses to component when heated. Therefore, the solder PCB must be allowed to cool to room temperature, 25°C, before handling. For further information on soldering and post solder cleaning, refer to Application Note 1027, Soldering LED Components. Figure 9: Recommended Wave Soldering Profile for LeadFree Smart Display LAMINAR WAVE HOT AIR KNIFE TURBULENT WAVE 250 TEMPERATURE – °C HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet BOTTOM SIDE OF PC BOARD TOP SIDE OF PC BOARD 200 CONVEYOR SPEED = 1.83 M/MIN (6 FT/MIN) PREHEAT SETTING = 150°C (100°C PCB) SOLDER WAVE TEMPERATURE = 245°C AIR KNIFE AIR TEMPERATURE = 390°C AIR KNIFE DISTANCE = 1.91 mm (0.25 IN.) AIR KNIFE ANGLE = 40° 150 FLUXING 100 50 30 0 NOTE: ALLOW FOR BOARDS TO BE SUFFICIENTLY COOLED BEFORE EXERTING MECHANICAL FORCE. PREHEAT 10 20 30 40 50 60 70 80 90 100 TIME – SECONDS Contrast Enhancement When used with the proper contrast enhancement filters, the HDSP-213x/HDSP-2179 series displays are readable daylight ambients. Refer to Application Note 1029, Luminous Contrast and Sunlight Readability of the HDSP235x Series Alphanumeric Displays for Military Applications, for information on contrast enhancement for daylight ambients. Refer to Application Note 1015, Contrast Enhancement Techniques for LED Displays, for information on contrast enhancement in moderate ambients. Night Vision Lighting When used with the proper NVG/ DV filters, the HDSP2131, HDSP-2179, and HDSP-2133 may be used in night vision lighting applications. The HDSP-2131 (yellow) and HDSP-2179 (orange) displays are used as master caution and warning indicators. The HDSP-2133 (high performance green) displays are used for general instrumentation. For a list of NVG/DV filters and a discussion on night vision lighting technology, refer to Application Note 1030, LED AV02-0190EN 16 Eight-Character 5.0-mm (0.2-in.) Glass/Ceramic Intelligent 5 × 7 Alphanumeric Displays for Military Applications HDSP-2131, HDSP-2132, HDSP-2133, HDSP-2179 Data Sheet Displays and Indicators and Night Vision Imaging System Lighting. An external dimming circuit must be used to dim these displays to night vision lighting levels to meet NVIS radiance requirements. Refer to AN 1039, Dimming HDSP213x Displays to Meet Night Vision Lighting Levels. Color Bin Limits Color Range (nm) Color Green Intensity Bin Limits Intensity Range (mcd) NOTE: Yellow Bin Min. Max. 1 576.0 580.0 2 573.0 577.0 3 570.0 574.0 4 567.0 571.5 3 581.5 585.0 4 584.0 587.5 Bin Min. Max. G 2.50 4.00 5 586.5 590.0 H 3.41 6.01 6 589.0 592.5 I 5.12 9.01 J 7.68 13.52 K 11.52 20.28 NOTE: Test conditions as specified in the Optical Characteristics table. Test conditions as specified in the Optical Characteristics table. Option Code Definition HDSP-213x- x y z xx Broadcom Color Bin Range Identifier A Color Bin 2 or 3 B Color Bin 4 or 5 C Color Bin 5 or 6 D Color Bin 3 or 4 Iv bin Range Identifier x Minimum Iv bin y Maximum Iv bin AV02-0190EN 17 Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks of Broadcom and/or its affiliates in the United States, certain other countries, and/or the EU. Copyright © 2007–2019 Broadcom. All Rights Reserved. The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. For more information, please visit www.broadcom.com. Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom is believed to be accurate and reliable. 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