HDSP-2531

HDSP-253x Series Eight Character 5 mm Smart Alphanumeric Display Data Sheet Description Features The HDSP-253x is ideal for applications where displaying eight or more characters of dot matrix information in an aesthetically pleasing manner is required. These devices are eight-digit, 5 x 7 dot matrix, alpha­nu­meric displays. The 5.0 mm (0.2 inch) high characters are pack­aged in a 0.300 inch (7.62 mm) 30 pin DIP. The on-board CMOS IC has the ability to decode 128 ASCII characters, which are perma­nently stored in ROM. In addi­tion, 16 pro­gram­mable symbols may be stored in on-board RAM. Seven brightness levels provide versa­tility in adjust­ing the display intensity and power consump­tion. The HDSP-253x is designed for stan­dard micro­processor inter­face tech­niques. The display and special features are accessed through a bidirec­tional eight-bit data bus. • XY stackable • 128 character ASCII decoder • Programmable functions • 16 user definable characters • Multi-level dimming and blanking • TTL compatible CMOS IC • Wave solderable Applications • Avionics • Computer peripherals • Industrial instrumentation • Medical equipment • Portable data entry devices • Telecommunications • Test equipment Device Selection Guide AlGaAs Red HER Orange Yellow Green HDSP-2534 HDSP-2532 HDSP-2530 HDSP-2531 HDSP-2533 ESD WARNING: Normal CMOS handling precautions should be observed to avoid static discharge. Package Dimensions 42.93 (1.690) MAX. PIN FUNCTION ASSIGNMENT TABLE PIN # FUNCTION PIN # FUNCTION 2.68 SYM. (0.105) 5.36 TYP. (0.211) 4.57 TYP. (0.180) 0 1 2 3 4 5 6 7 2.29 SYM. (0.090) PIN #1 IDENTIFIER 11.43 MAX. (0.450) 2.54 TYP. (0.100) DATE CODE (YEAR, WEEK) LUMINOUS INTENSITY CATEGORY COLOR BIN (3) PART NUMBER RST FL A0 A1 A2 A3 NO PIN NO PIN NO PIN A4 CLS CLK WR CE VDD 5.31 (0.209) 5.08 SYM. (0.200) PIN #1 PIN #15 GND (SUPPLY) THERMAL TEST GND (LOGIC) RD D0 D1 NO PIN NO PIN NO PIN D2 D3 D4 D5 D6 D7 1.52 REF. (0.060) 4.01 TYP. (0.158) 0.46 0.13 TYP. (0.018 0.005) 2.54 0.13 TYP. (0.100 0.005) (TOL. NON ACCUM.) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0.25 (0.010) [4] HDSP-253x X Z YYWW PIN # 15 PIN # 16 3.81 SYM. (0.150) 7.62 (0.300) 10.16 (0.400) Notes: 1. Dimensions are in mm (inches). 2. Unless otherwise specified, tolerance on dimensions is ±0.25 mm (0.010 inch). 3. For yellow and green displays only. 4. Marking is on side opposite pin 1. Absolute Maximum Ratings Supply Voltage, VDD to Ground[1] -0.3 V to 7.0 V Operating Voltage, VDD to Ground[2] 5.5 V Input Voltage, Any Pin to Ground -0.3 V to VDD +0.3 V Free Air Operating Temperature Range, TA[3 ] -40°C to + 85°C Relative Humidity (Noncondensing) 85% Storage Temperature Range, TS -55°C to 100°C Soldering Temperature [1.59 mm (0.063 in.) Below Body]   Solder Dipping   Wave Soldering 260°C for 5 secs 250°C for 3 secs ESD Protection @ 1.5 kΩ, 100 pF 4 kV (each pin) Notes: 1.  Maximum voltage is with no LEDs illuminated. 2.  20 dots ON in all locations at full brightness. 3.  See Thermal Considerations section for information about operation in high temperature ambients.  1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ASCII Character Set D7 D6 BIT S D5 0 0 D4 D3 D2 D1 D0 ROW COLUMN 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 D 1110 E 1111 F 0 0 0 0 0 0 0 0 1 1 1 2 0 0 0 1 0 1 1 3 0 4 0 1 0 0 0 1 1 5 1 6 0 1 0 1 7 1 X 1 X X 8–F 16 U S E R D E F I N E D C H A R A C T E R S Optical Characteristics at 25°C[1] VDD = 5.0 V at Full Brightness LED Color Part Number Luminous Intensity Peak Character Average (#) IV (mcd) Min. Typ. Dominant Wavelength lPEAK (nm) Typ. Wavelength[2] ld (nm) Typ. AlGaAs Red HDSP-2534 5.1 25 645 637 High Efficiency Red HDSP-2532 2.5 7.5 635 626 Orange HDSP-2530 2.5 7.5 600 602 Yellow HDSP-2531 2.5 7.5 583 585 Green HDSP-2533 2.5 7.5 568 574 Notes: 1. Refers to the initial case temperature of the device immediately prior to measurement. 2.  Dominant wavelength, ld, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the device.  Recommended Operating Conditions Parameter Symbol Minimum Nominal Maximum Units Supply Voltage VDD 4.5 5.0 5.5 V Electrical Characteristics over Operating Temperature Range 4.5 < VDD < 5.5 unless otherwise specified Parameter Symbol Min. 25°C Typ.[1] 25°C Max.[1] Max. Units Test Conditions Input Leakage (Input without Pull-up) II -1.0 1.0 mA VIN = 0 to VDD, Pins CLK, D0-D7, A0-A4 Input Current (Input with Pull-up) IIP -30 -11 -18 0 mA VIN = 0 to VDD, Pins CLS, RST, WR, RD, CE, FL IDD Blank IDD(BL) 0.5 3.0 4.0 mA VIN = VDD IDD 8 Digits 12 Dots/Char[2,3,4] IDD(V) 230 295 390 mA “V” On in All 8 Locations IDD 8 Digits 20 Dots/Char[2,3,4] (AlGaAs) IDD(#) 330 410 480 mA “#” On in All 8 Locations IDD 8 Digits 12 Dots/Char[2,3,4] (All Colors Except AlGaAs) IDD(V) 200 255 330 mA “V” On in All 8 Locations IDD 8 Digits 20 Dots/Char[2,3,4] (All Colors Except AlGaAs) IDD(#) 300 370 430 mA “#” On in All 8 Locations Input Voltage High VIH 2.0 VDD +0.3 V V Input Voltage Low VIL GND -0.3 V 0.8 V Output Voltage High VOH 2.4 V VDD = 4.5 V, IOH = -40 µA Output Voltage Low D0-D7 VOL 0.4 V VDD = 4.5 V, IOL = 1.6 mA Output Voltage Low CLK VOL 0.4 V VDD = 4.5 V, IOL = 40 µA Thermal Resistance IC Junction-to-PIN RqJ-PIN 16 °C/W Measured at Pin 17 (AlGaAs) Notes: 1.  VDD = 5.0 V. 2.  See Thermal Considerations Section for information about operation in high temperature ambients. 3.  Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak IDD = 28/15 x IDD(#). 4.  Maximum IDD occurs at -55°C.  AC Timing Characteristics over Temperature Range VDD = 4.5 to 5.5 V unless otherwise specified. Reference Number Symbol Description Min.[1] Units 1 tACC Display Access Time   Write   Read 210 230 ns 2 tACS Address Setup Time to Chip Enable 10 ns 3 tCE Chip Enable Active Time[2, 3]   Write   Read 140 160 ns 4 tACH Address Hold Time to Chip Enable 20 ns 5 tCER Chip Enable Recovery Time 60 ns 6 tCES Chip Enable Active Prior to Rising Edge of[2, 3]   Write   Read 140 160 ns 7 tCEH Chip Enable Hold Time to Rising Edge of Read/Write Signal[2,3] 0 ns 8 tW Write Active Time 100 ns 9 tWD Data Valid Prior to Rising Edge of Write Signal 50 ns 10 tDH Data Write Hold Time 20 ns 11 tR Chip Enable Active Prior to Valid Data 160 ns 12 tRD Read Active Prior to Valid Data 75 ns 13 tDF Read Data Float Delay 10 ns tRC Reset Active Time[4] 300 ns Notes: 1.  Worst case values occur at an IC junction temperature of 125°C. 2.  For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be tied together. 3.  Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM, regardless of the logic levels of the WR and RD lines. 4.  The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the reset line. Symbol Description 25°C Typical Minimum[1] Units FOSC Oscillator Frequency 57 28 kHz FRF[5] Display Refresh Rate 256 128 Hz FFL[6] Character Flash Rate 2 1 Hz tST[7] Self Test Cycle Time 4.6 9.2 sec Notes: 5.  FRF = FOSC/224. 6.  FFL = FOSC/28,672. 7.  tST = 262,144/FOSC.  Write Cycle Timing Diagram 1 A0 -A4 FL 4 2 2 3 5 CE 6 7 8 WR 10 9 D0 -D7 Input Pulse Levels: 0.6 V to 2.4 V Read Cycle Timing Diagram 1 A0 -A4 FL 4 2 CE 6 7 11 RD 12 D0 -D7 Input Pulse Levels: 0.6 V to 2.4 V Output Reference Levels: 0.6 V to 2.2 V Output Loading = 1 TTL Load and 100 pF  2 5 3 13 Electrical Description Pin Function Description RESET (RST, pin 1) Reset initializes the display. FLASH (FL, pin 2) FL low indicates an access to the Flash RAM and is unaffected by the state of address lines A3-A4. ADDRESS INPUTS (A0-A4, pins 3-6, 10) Each location in memory has a distinct address. Address inputs (A0-A2) select a specific location in the Character RAM, the Flash RAM or a particular row in the UDC (User- Defined Character) RAM. A3-A4 are used to select which section of memory is accessed. Table 1 shows the logic levels needed to access each section of memory. Table 1. Logic Levels to Access Memory FL A4 A3 Section of Memory 0 X X Flash RAM Character Address 1 0 0 UDC Address Register Don’t Care 1 0 1 UDC RAM Row Address 1 1 0 Control Word Register Don’t Care 1 1 1 Character RAM Character Address CLOCK SELECT (CLS, pin 11) This input is used to select either an internal (CLS = 1) or external (CLS = 0) clock source. CLOCK INPUT/OUTPUT (CLK, pin 12) Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave displays. WRITE (WR, pin 13) Data is written into the display when the WR input is low and the CE input is low. CHIP ENABLE (CE, pin 14) This input must be at a logic low to read or write data to the display and must go high between each read and write cycle. READ (RD, pin 19) Data is read from the display when the RD input is low and the CE input is low. DATA Bus (D0-D7, pins 20, 21, 25-30) The Data bus is used to read from or write to the display. GND (SUPPLY) (pin 16) This is the analog ground for the LED drivers. GND (LOGIC) (pin 18) This is the digital ground for internal logic. VDD (POWER) (pin 15) This is the positive power supply input. Thermal Test (pin 17) This pin is used to measure the IC junction temperature. Do not connect.  A2 A1 A0  OCS A3 A4 FL CE FL CE A3 A4 FL CE CLR1 SELF TEST RESULT RESET CONTROL WORD REGISTER EN RD WR D0-D7 PRE SET CLR RD WR D0-D7 6 7 SELF TEST 0 INTENSITY 1 2 FLASH 3 BLINK 4 UDC ADDR UDC ADDR REGISTER EN Figure 1. HDSP-253X internal block diagram. CLS CLK RST RD WR D0-D7 A0-A2 A3 A4 FL CE A3 A4 FL CE RESET A3 A4 FL CE INTENSITY FLASH BLINK RESET CLOCK FLASH TEST OK CLR2 TIMING AND CONTROL TEST OK SELF TEST SELF TEST IN VISUAL TEST ROM TEST SELF TEST CLR START TIMING ROW SET CHAR ADDR EN RD WR FLASH D0 RAM A0-A2 RESET CHAR ADDR FLASH DATA 8x8 EN CHARACTER RD D0-D6 RAM WR D7 D0-D7 A0-A2 RESET CHAR ADDR UDC RAM ROW SEL SELF TEST DOT DATA DECODER(*) D0-D6 EN EN RD WR DOT D0-D4 DATA A0-A2 UDC ADDR ROW SET EN D0-D4 TIMING DOT DRIVERS DOT DATA TIMING ROW DRIVERS 8 5x7 LED CHARACTERS Display Internal Block Diagram Figure 1 shows the internal block diagram of the HDSP253X display. The CMOS IC consists of an 8 byte Charac­ter RAM, an 8 bit Flash RAM, a 128 character ASCII decoder, a 16 character UDC RAM, a UDC Address Register, a Control Word Register and the refresh circuitry necessary to synchronize the decoding and driving of eight 5 x 7 dot matrix characters. The major user accessible portions of the display are listed below: Character RAM This RAM stores either ASCII character data or a UDC RAM address. Flash RAM This is a 1 x 8 RAM which stores Flash data. User-Defined Character RAM (UDC RAM) This RAM stores the dot pattern for custom characters. User-Defined Character Address Register (UDC Address Register) This register is used to provide the address to the UDC RAM when the user is writing or reading a custom character. Control Word Register This register allows the user to adjust the display brightness, flash individual characters, blink, self test or clear the display. Character Ram Figure 2 shows the logic levels needed to access the HDSP253X Character RAM. During a normal access the CE = “0” and either RD = “0” or WR = “0”. However, erro­neous data may be written into the Character RAM if the Address lines are unstable when CE = “0” regardless of the logic levels of the RD or WR lines. Address lines A0-A2 are used to select the location in the Char­ac­ter RAM. Two types of data can be stored in each Character RAM location: an ASCII code or a UDC RAM address. Data bit D7 is used to differentiate between the ASCII character and a UDC RAM address. D7 = 0 enables the ASCII decoder and D7 = 1 enables the UDC RAM. D0-D6 are used to input ASCII data and D0-D3 are used to input a UDC address. RST 1 CE WR RD 0 0 0 1 1 0 1 0 1 A2 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL SIGNALS FL A4 A3 1 1 1 A1 A0 000 = LEFT MOST 111 = RIGHT MOST CHARACTER ADDRESS CHARACTER RAM ADDRESS D7 D6 D5 0 D4 D3 D2 D1 D0 128 ASCII CODE 1 X X X UDC CODE CHARACTER RAM DATA FORMAT DIG0 DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 000 001 010 011 100 101 110 111 SYMBOL IS ACCESSED IN LOCATION SPECIFIED BY THE CHARACTER ADDRESS ABOVE DISPLAY 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 2. Logic levels to access the character RAM.  UDC RAM and UDC Address Register Figure 3 shows the logic levels needed to access the UDC RAM and the UDC Address Register. The UDC Address Register is eight bits wide. The lower four bits (D0-D3) are used to select one of the 16 UDC locations. The upper four bits (D4-D7) are not used. Once the UDC address has been stored in the UDC Address Register, the UDC RAM can be accessed. To completely specify a 5 x 7 character requires eight write cycles. One cycle is used to store the UDC RAM address in the UDC Address Register. Seven cycles are used to store dot data in the UDC RAM. Data is entered by rows. One cycle is needed to access each row. Figure 4 shows the organization of a UDC character assuming the symbol to be stored is an “F.” A0-A2 are used to select the row to be accessed and D0-D4 are used to transmit the row dot data. The upper three bits (D5-D7) are ignored. D0 (least signif­i­ cant bit) corresponds to the right most column of the 5 x 7 matrix and D4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. Flash RAM Figure 5 shows the logic levels needed to access the Flash RAM. The Flash RAM has one bit associated with each location of the Character RAM. The Flash input is used to select the Flash RAM. Address lines A3-A4 are ignored. Address lines A0-A2 are used to select the location in the Flash RAM to store the attri­bute. D0 is used to store or remove the flash attribute. D0 = “1” stores the attribute and D0 = “0” removes the attribute. When the attribute is enabled through bit 3 of the Control Word and a “1” is stored in the Flash RAM, the corresponding character will flash at approximately 2 Hz. The actual rate is dependent on the clock fre­quency. For an external clock the flash rate can be calculated by dividing the clock frequency by 28,672. C C C O O O L L L 1 2 3 D4 D3 D2 1 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 IGNORED C O L 4 D1 1 0 0 1 0 0 0 C O L 5 D0 1 0 0 0 0 0 0 CE WR 0 0 1 0 1 1 CONTROL SIGNALS FL A4 A3 A2 A1 A0 1 0 0 X X X ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 UDC CHARACTER • • • • • • • • • • • • • • Figure 4. Data to load “”F’’ into the UDC RAM. HEX CODE 1F 10 10 1E 10 10 10 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED UDC ADDRESS REGISTER ADDRESS D7 D6 D5 D4 X X X X D3 D2 D1 D0 UDC CODE UDC ADDRESS REGISTER DATA FORMAT RST CE WR 0 0 1 0 1 1 CONTROL SIGNALS FL A4 A3 1 0 1 RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED A2 A1 A0 000 = ROW 1 110 = ROW 7 ROW SELECT UDC RAM ADDRESS D7 D6 D5 X X X D4 D3 D2 D1 D0 DOT DATA UDC RAM DATA FORMAT C O L 1 C O L 5 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 3. Logic levels to access a UDC character. WR 0 0 1 0 1 1 CONTROL SIGNALS 0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED 10 RST RST CE FL A4 A3 0 X X RD 0 1 0 1 UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED A2 A1 A0 CHARACTER ADDRESS 000 = LEFT MOST 111 = RIGHT MOST FLASH RAM ADDRESS D7 D6 D5 D4 D3 D2 D1 X X X X X X X D0 0 1 FLASH RAM DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 5. Logic levels to access the Flash RAM. REMOVE FLASH AT SPECIFIED DIGIT LOCATION STORE FLASH AT SPECIFIED DIGIT LOCATION Control Word Register Figure 6 shows how to access the Control Word Register. This is an eight bit register which performs five functions. They are Brightness control, Flash RAM control, Blinking, Self Test and Clear. Each function is independent of the others. How­ever, all bits are updated during each Control Word write cycle. Brightness (Bits 0-2) Bits 0-2 of the Control Word adjust the brightness of the display. Bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. In addition to varying the display brightness, bits 0-2 also vary the average value of IDD. IDD can be calcu­lated at any brightness level by multiplying the percent brightness level by the value of IDD at the 100% brightness level. These values of IDD are shown in Table 2. Flash Function (Bit 3) Bit 3 determines whether the flashing character attribute is on or off. When bit 3 is a “1,” the output of the Flash RAM is checked. If the content of a loca­tion in the Flash RAM is a “1,” the associated digit will flash at approximately 2 Hz. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. If the flash enable bit of the Control Word is a “0,” the content of the Flash RAM is ignored. To use this function with multiple dis­play systems see the Reset section. Blink Function (Bit 4) RST CE WR 0 0 1 0 1 1 CONTROL SIGNALS RD 0 1 0 1 FL A4 A3 A2 A1 A0 1 1 0 X X X UNDEFINED WRITE TO DISPLAY READ FROM DISPLAY UNDEFINED CONTROL WORD ADDRESS D7 D6 D5 D4 D3 D2 D1 D0 C S S BL F B B B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 DISABLE FLASH 1 ENABLE FLASH 0 DISABLE BLINKING 1 ENABLE BLINKING 0 X NORMAL OPERATION; X IS IGNORED 1 X START SELF TEST; RESULT GIVEN IN X X = 0 FAILED X = 1 PASSED 0 NORMAL OPERATION 1 CLEAR FLASH AND CHARACTER RAMS 100% 80% 53% BRIGHTNESS 40% CONTROL 27% LEVELS 20% 13% 0% CONTROL WORD DATA FORMAT 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Figure 6. Logic levels to access the control word register. Bit 4 of the Control Word is used to synchronize blinking of all eight digits of the display. When this bit is a “1” all eight digits of the display will blink at approxi­mately 2 Hz. The actual rate is dependent on the clock frequency. For an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. This function will override the Flash function when it is active. To use this function with multiple display systems see the Reset section. Table 2. Current Requirements at Different Brightness Levels for All Colors Except AlGaAs Symbol D2 D1 D0 % Brightness VDD = 5.0 V 25°C Typ. Units IDD (V) 0 0 0 100 200 mA 0 0 1 80 160 mA 0 1 0 53 106 mA 0 1 1 40 80 mA 1 0 0 27 54 mA 1 0 1 20 40 mA 1 1 0 13 26 mA 11 Self Test Function (Bits 5, 6) Display Reset Bit 6 of the Control Word Regis­ter is used to initiate the self test function. Results of the internal self test are stored in bit 5 of the Control Word. Bit 5 is a read only bit where bit 5 = “1” indicates a passed self test and bit 5 = “0” indicates a failed self test. Figure 7 shows the logic levels needed to reset the display. The display should be reset on Power-up. The external Reset clears the Character RAM, Flash RAM, Control Word and resets the internal counters. After the rising edge of the Reset signal, three clock cycles (110 ms min. using the internal refresh clock) are required to complete the reset sequence. The display must not be accessed while the display is being reset. The ASCII Character code for a space (20H) will be loaded into the Character RAM to blank the display. The Flash RAM and Control Word Register are loaded with all “0”s. The UDC RAM and UDC Address Register are unaffected. All displays which operate with the same clock source must be simul­ta­ne­ously reset to synchronize the Flashing and Blinking functions. Setting bit 6 to a logic 1 will start the self test function. The built-in self test function of the IC consists of two internal rou­tines which exercises major portions of the IC and illumin­ates all of the LEDs. The first routine cycles the ASCII decoder ROM through all states and performs a checksum on the output. If the checksum agrees with the correct value, bit 5 is set to “1.” The second rou­tine provides a visual test of the LEDs using the drive circuitry. This is accomplished by writing checkered and inverse checkered patterns to the display. Each pattern is displayed for approxi­mately 2 seconds. During the self test function the display must not be accessed. The time needed to execute the self test function is calculated by multiplying the clock period by 262,144. For example, assume a clock frequency of 58 KHz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. At the end of the self test func­tion, the Character RAM is loaded with blanks, the Control Word Register is set to zeros except for bit 5, and the Flash RAM is cleared and the UDC Address Register is set to all ones. Clear Function (Bit 7) Bit 7 of the Control Word will clear the Character RAM and the Flash RAM. Setting bit 7 to a “1” will start the clear func­tion. Three clock cycles (110 ms min. using the internal refresh clock) are required to complete the clear function. The display must not be accessed while the display is being cleared. When the clear function has been com­pleted, bit 7 will be reset to a “0.” The ASCII char­acter code for a space (20H) will be loaded into the Character RAM to blank the display and the Flash RAM will be loaded with “1”s. The UDC RAM, UDC Address Register and the re­ mainder of the Control Word are unaffected. 12 Mechanical Considerations The HDSP-253X is assembled by die attaching and wire bond­ing 280 LED chips and a CMOS IC to a thermally conductive printed circuit board. A polycarbonate lens placed over the pcb creates an air gap over the LED wire bonds. A backfill epoxy seals the display package. Figure 8 shows the proper method to insert the display by hand. To prevent damage to the LED wire bonds, apply pressure uniformly with fingers located at both ends of the part. Using a tool, shown in Figure 9, such as a screwdriver or pliers to push the display into the printed circuit board or socket may damage the LED wire bonds. The force exerted by a screw­driver is sufficient to push the lens into the LED wire bonds. The bent wire bonds cause shorts or opens that result in catastrophic failure of the LEDs. RST CE WR RD FL A4 -A0 D7 -D0 0 1 X X X X X 0 = LOGIC 0; 1 = LOGIC 1; X = DO NOT CARE Note: If RST, CE, and WR are low, unkown data may be written into the display. Figure 7. Logic levels to reset the display. Figure 8. Proper method to manually insert a display. Figure 9. Improper method to manually insert a display. Thermal Considerations The HDSP-253X can operate from -40°C to +85°C. The display’s low thermal resistance allows heat to flow from the CMOS IC to the 24 package pins. Typically, this heat is conducted through the printed circuit board traces to free air. For most applications, no additional heatsinking is needed. Illuminating all 280 LEDs simultaneously at full brightness is not recommended for continuo­us operation. How­ever, all 280 LEDs can be illuminated simul­taneously at full brightness for 10 seconds at 25°C as a lamp test. The IC has a maximum allow­able junction temperature of 150°C. The IC junction tempera­ture can be calculated with the following equation: TJMAX = TA + (PD x RqJ-A) TJMAX is the maximum allow­able IC junction temperature. TA is the ambient temperature surrounding the display. PD is the power dissipated by the IC. PD can be calculated as follows: PD = VDD x IDD VDD is the supply voltage and IDD is the supply current. VDD can vary from 4.5 V to 5.5 V. IDD changes with VDD, temperature, brightness level, and number of on-pixels. For AlGaAs IDD (#) = (83.8 x VDD -0.35 x TJ ) x B x N/8 IDD(V) = (63 x VDD -0.79 x TJ ) x B x N/8 For the other colors IDD (#) = (75.4 x VDD -0.28 x TJ ) x B x N/8 IDD(V) = (54 x VDD -0.6 x TJ ) x B x N/8 IDD (#) is the supply current using “#” as the displayed character. IDD(V) is the supply current using “V” as the displayed character. RqJ-A is the thermal resistance from the IC through the display package and printed circuit board to the ambient. TJ is the IC junction temperature. A typical value for RqJ-A is 39°C/W. This value is typical for a display mounted in a socket and covered with a plastic filter. The socket is soldered to a 0.062 in. thick printed circuit board with 0.020 in. wide one-ounce copper traces. N is the number of characters illuminated. 13 B is the percent brightness level. Operation in high temperature ambients may require power derating or heatsinking. Figure 10 shows how to derate the power for an HDSP-253X. You can reduce the power by tighter supply voltage regulation or lowering the brightness level. PD MAX. – MAXIMUM POWER DISSIPATION – W Table 3 shows the calculated maximum allowable ambient temperature for several differ­ent sets of operating conditions. The worst case alphanumeric characters (#,@,B) have 20 pixels. Displaying eight 20-pixel characters will not occur in normal operation. Thus, using eight 20-pixel characters to calculate power dissipation will over estimate the power and the IC junction temperature. The average number of pixels per character, supply voltage, brightness level, and number of characters are needed to calcu­late the power dissipated by the IC. The ambient temper­ature, power dissipated by the IC, and the thermal resistance are then used to calculate IC junction tempera­ture. The typical alpha­numeric character is 15 pixels. For conditions not listed in Table 3, you can calculate the power dissipated by the IC and use Figure 10 to determine the maximum ambient temperature. 2.3 2.2 AlGaAs RθJ-A = 39C/W 2.1 2.0 1.9 ALL OTHER COLORS 1.8 1.7 1.6 1.5 50 55 60 65 70 75 80 85 90 TA – AMBIENT TEMPERATURE – C Figure 10. Maximum allowable power dissipation vs. ambient temperature. TJMAX = 150°C or 120°C. Table 3. Maximum Allowable Ambient Temperature for Various Operating Conditions AlGaAs Red Character Number of Characters Brightness Level VDD V IDD mA PD W RqJ-A °C/W TAMAX °C # (20 dots) 8 100% 5.5 408 2.2 39 64 # (20 dots) 8 100% 5.25 387 2.0 39 72 # (20 dots) 8 100% 5.0 366 1.8 39 80 # (20 dots) 7 100% 5.5 357 2.0 39 72 # (20 dots) 6 100% 5.5 306 1.7 39 84 # (20 dots) 8 80% 5.5 327 1.8 39 80 # (20 dots) 8 80% 5.25 310 1.6 39 85 # (20 dots) 8 53% 5.5 216 1.2 39 85 V (12 dots) 8 100% 5.5 228 1.3 39 85 Table 4. Maximum Allowable Ambient Temperature for Various Operating Conditions (cont’d.) All Colors Except AlGaAs Red Character Number of Characters Brightness Level VDD V IDD mA PD W RqJ-A °C/W TAMAX °C # (20 dots) 8 100% 5.5 373 2.0 39 72 # (20 dots) 8 100% 5.25 354 1.9 39 77 # (20 dots) 8 100% 5.0 335 1.67 39 85 # (20 dots) 7 100% 5.5 326 1.8 39 80 # (20 dots) 6 100% 5.5 280 1.5 39 85 # (20 dots) 8 80% 5.5 298 1.6 39 85 V (12 dots) 8 100% 5.5 207 1.1 39 85 The actual IC temperature is easy to measure. Pin 17 is thermally and electrically connected to the IC substrate. The thermal resistance from pin 17 to the IC is 16°C/W. The procedure to measure the IC junction temperature is as follows: 1.  Measure VDD and IDD for the display. Measure VDD between pins 15 and 16. Measure the current entering pin 15. 2.  Measure the temperature of pin 17 after 45 minutes. Use an electrically isolated thermal couple probe. 3.  TJ(IC) = Tpin + VDD x IDD x 16°C/W. 14 Ground Connections Two ground pins are provided to keep the internal IC logic ground clean. The designer can, when necessary, route the ana­log ground for the LED drivers separately from the logic ground until an appropriate ground plane is available. On long inter­­connections between the display and the host system, the designer can keep voltage drops on the analog ground from affect­ing the display logic levels by isolating the two grounds. The logic ground should be con­nected to the same ground poten­tial as the logic interface circuitry. The analog ground and the logic ground should be connected at a common ground which can withstand the cur­rent induced by the switch­ing LED drivers. When separate ground connections are used, the analog ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Volt­age below -0.3 V can cause all dots to be on. Voltage above +0.3 V can cause dimming and dot mismatch. Solder and Post Solder Cleaning Note: Freon vapors can cause the black paint to peel off the display. See Application Note 1027 for information on soldering and post solder cleaning. Contrast Enhancement (Filtering) See Application Note 1015 for information on contrast enhancement. Intensity Bin Limits for HDSP-2534 Color Bin Limits Color Range (nm) Intensity Range (mcd) Bin Min. Max. Color Bin Min. Max. I 5.12 9.01 Green 1 576.0 580.0 J 7.68 13.52 2 573.0 577.0 K 11.52 20.28 3 570.0 574.0 L 17.27 30.42 4 567.0 571.0 M 25.91 45.63 Yellow 3 581.5 585.0 4 584.0 587.5 5 586.5 590.0 6 589.0 592.5 7 591.5 595.0 Note: Test conditions as specified in Optical Characteristic table. Intensity Bin Limits for HDSP-253x Note: Test conditions as specified in Optical Characteristic table. Intensity Range (mcd) Bin Min. Max. G 2.50 4.00 H 3.41 6.01 I 5.12 9.01 J 7.68 13.52 K 11.52 20.28 Note: Test conditions as specified in Optical Characteristic table. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-3184EN AV02-2018EN - July 15, 2009