HFBR-1115TZ Transmitter
HFBR-2115TZ Receiver
Fiber Optic Transmitter and Receiver Data Links
for 125 MBd
Data Sheet
Description
The HFBR-1115TZ/-2115TZ series of data links are
high-performance, cost-efficient, transmitter and
receiver modules for serial optical data communication
applications specified at 100 Mbps for FDDI PMD or
100 Base-FX Fast Ethernet applications.
These modules are designed for 50 or 62.5 µm core
multi-mode optical fiber and operate at a nominal
wavelength of 1300 nm. They incorporate our highperformance, reliable, long-wavelength, optical devices
and proven circuit technology to give long life and
consistent performance.
Transmitter
The transmitter utilizes a 1300 nm surface-emitting
InGaAsP LED, packaged in an optical subassembly.
The LED is dc-coupled to a custom IC which converts
differential-input, PECL logic signals, ECL-referenced
(shifted) to a +5 V power supply, into an analog LED
drive current.
Receiver
The receiver utilizes an InGaAs PIN photodiode coupled
to a custom silicon transimpedance preamplifier IC.
The PIN-preamplifier combination is ac-coupled to a
custom quantizer IC which provides the final pulse
shaping for the logic output and the Signal Detect
function. Both the Data and Signal Detect Outputs are
differential. Also, both Data and Signal Detect Outputs
are PECL compatible, ECL-referenced (shifted) to a
+5 V power supply.
Package
The overall package concept for the Data Links consists
of the following basic elements: two optical
subassemblies, two electrical subassemblies, and the
outer housings as illustrated in Figure 1.
*ST is a registered trademark of AT&T Lightguide Cable Connectors.
Features
• Full compliance with the optical performance
requirements of the FDDI PMD standard
• Full compliance with the optical performance
requirements of the ATM 100 Mbps physical layer
• Full compliance with the optical performance requirements of the 100 Mbps fast ethernet physical layer
• Other versions available for:
– ATM
– Fibre Channel
• Compact 16-pin DIP package with plastic ST*
connector
• Wave solder and aqueous wash process compatible
package
• Manufactured in an ISO 9001 certified facility
Applications
• FDDI concentrators, bridges, routers, and network
interface cards
• 100 Mbps ATM interfaces
• Fast ethernet interfaces
• General purpose, point-to-point data communications
• Replaces DLT/R1040-ST1 model transmitters and
receivers
RECEIVER
DIFFERENTIAL
DATA IN
DIFFERENTIAL
SIGNAL
DETECT OUT
The package outline drawing and
pinout are shown in Figures 2
and 3. The details of this package
outline and pinout are compatible
with other data-link modules from
other vendors.
PIN PHOTODIODE
QUANTIZER
IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
ELECTRICAL
SUBASSEMBLIES
SIMPLEX ST®
RECEPTACLE
TRANSMITTER
DIFFERENTIAL
DATA IN
VBB
DRIVER IC
LED
TOP VIEW
Figure 1. Transmitter and receiver block diagram.
THREADS
3/8 – 32 UNEF-2A
HFBR-111X/211XT
DATE CODE (YYWW)
SINGAPORE
12.19
MAX.
8.31
41 MAX.
5.05
0.9
7.01
9.8 MAX.
5.0
2.45
19.72
NOTES:
1. MATERIAL ALLOY 194 1/2H – 0.38 THK
FINISH MATTE TIN PLATE 7.6 µm MIN.
2. MATERIAL PHOSPHOR BRONZE WITH
120 MICROINCHES TIN LEAD (90/10)
OVER 50 MICROINCHES NICKEL.
12
17.78
(7 x 2.54)
8 x 7.62
3. UNITS = mm
HOUSING PINS 0.38 x 0.5 mm
NOTE 1
PCB PINS
DIA. 0.46 mm
NOTE 2
Figure 2. Package outline drawing.
2
3
NC
OPTICAL PORT
9
8
NC
GND
10
7
NO PIN
9
8
NC
NO PIN
VCC
11
6
VCC
12
NC
10
7
GND
GND
GND
11
6
VCC
5
GND
GND
12
5
VCC
GND
13
4
GND
GND
13
4
VCC
DATA
14
3
GND
SD
14
3
DATA
DATA
15
2
VBB
SD
15
2
DATA
NC
16
1
NC
NO PIN
16
1
NC
TRANSMITTER
RECEIVER
Figure 3. Pinout drawing.
The optical subassemblies consist
of a transmitter subassembly in
which the LED resides and a
receiver subassembly housing the
PIN-preamplifier combination.
The electrical subassemblies consist of a multi-layer printed circuit
board on which the IC chips and
various sufrace-mounted, passive
circuit elements are attached.
Each transmitter and receiver
package includes an internal shield
for the electrical subassembly to
ensure low EMI emissions and high
immunity to external EMI fields.
The outer housing, including the
ST* port, is molded of filled, nonconductive plastic to provide
mechanical strength and electrical
isolation. For other port styles,
please contact your Avago
Technologies Sales Representative.
Each data-link module is attached
to a printed circuit board via the
16-pin DIP interface. Pins 8 and 9
provide mechanical strength for
these plastic-port devices and will
provide port-ground for forthcoming metal-port modules.
3
Application Information
The Applications Engineering
group of the Fiber Optics Product
Division is available to assist you
with the technical understanding
and design tradeoffs associated
with these transmitter and receiver
modules. You can contact them
through your Avago Technologies
sales representative.
The following information is
provided to answer some of the
most common questions about the
use of these parts.
Transmitter and Receiver Optical
Power Budget versus Link Length
The Optical Power Budget (OPB)
is the available optical power for a
fiber-optic link to accommodate
fiber cable losses plus losses due to
in-line connectors, splices, optical
switches, and to provide margin for
link aging and unplanned losses
due to cable plant reconfiguration
or repair.
Figure 4 illustrates the predicted
OPB associated with the transmitter and receiver specified in this
data sheet at the Beginning of Life
(BOL). This curve represents the
attenuation and chromatic plus
modal dispersion losses associated
with 62.5/125 µm and 50/125 µm
fiber cables only. The area under
the curve represents the remaining
OPB at any link length, which is
available for overcoming non-fiber
cable related losses.
OPB – OPTICAL POWER BUDGET – dB
OPTICAL PORT
14
12
62.5/125 µm
10
8
6
50/125 µm
4
2
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FIBER OPTIC CABLE LENGTH – km
Figure 4. Optical power budget at BOL vs.
fiber optic cable length.
Avago LED technology has
produced 1300 nm LED devices
with lower aging characteristics
than normally associated with
these technologies in the industry.
The industry convention is 1.5 dB
aging for 1300 nm LEDs; however,
Avago 1300 nm LEDs will
experience less than 1 dB of aging
over normal commercial
equipment mission-life periods.
Contact your Avago Technologies
sales representative for additional
details.
Figure 4 was generated with an
Avago fiber-optic link model
containing the current industry
conventions for fiber cable
specifications and the FDDI PMD
optical parameters.
These parameters are reflected in
the guaranteed performance of the
transmitter and receiver specifications in this data sheet. This same
model has been used extensively in
the ANSI and IEEE committees,
including the ANSI X3T9.5
committee, to establish the optical
performance requirements for
various fiber-optic interface
standards. The cable parameters
used come from the ISO/IEC JTC1/
SC 25/WG3 Generic Cabling for
Customer Premises per DIS 11801
document and the EIA/TIA-568-A
Commercial Building Telecommunications Cabling Standard per
SP-2840.
TRANSMITTER/RECEIVER RELATIVE OPTICAL
POWER BUDGET AT CONSTANT BER (dB)
Transmitter and Receiver Signaling
Rate Range and BER Performance
For purposes of definition, the
symbol rate (Baud), also called
signaling rate, is the reciprocal of
the symbol time. Data rate (bits/
sec) is the symbol rate divided by
the encoding factor used to encode
the data (symbols/bit).
Figure 5. Transmitter/Receiver relative optical
power budget at constant BER vs. signaling
rate.
The data link modules can be used
for other applications at signaling
rates outside of the 10 MBd to 125
MBd range with some penalty in
the link optical power budget
primarily caused by a reduction of
receiver sensitivity. Figure 5 gives
an indication of the typical
performance of these 1300 nm
products at different rates.
4
2.5
2.0
1.5
1.0
0.5
0
0
25
50
75 100 125 150 175 200
SIGNAL RATE (MBd)
The 1300 nm transmitter will
tolerate the worst-case input
electrical jitter allowed in the table
without violating the worst-case
output jitter requirements of
Section 8.1 Active Output Interface
of the FDDI PMD standard.
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
The 1300 nm receiver will tolerate
4. TA = 25° C
5. VCC = 5 Vdc
the worst-case input optical jitter
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
These data link modules can also
be used for applications which
require different bit-error-ratio
(BER) performance. Figure 6
illustrates the typical trade-off
between link BER and the receiver
input optical power level.
1 x 10-2
BIT ERROR RATIO
When used in FDDI, ATM 100
Mbps, and Fast Ethernet
applications, the performance of
Avago Technologies’ 1300 nm
HFBR-1115TZ/-2115TZ data link
modules is guaranteed over the
signaling rate of 10 MBd to 125
MBd to the full conditions listed in
the individual product specification
tables.
Data Link Jitter Performance
The Avago 1300 nm data link
modules are designed to operate
per the system jitter allocations
stated in Table E1 of Annex E of
the FDDI PMD standard.
3.0
1 x 10-3
CENTER OF
SYMBOL
1 x 10-4
1 x 10-5
1 x 10-6
1 x 10-7
1 x 10-8
2.5 x 10-10
1 x 10-11
1 x 10-12
-6
-4
-2
0
2
4
RELATIVE INPUT OPTICAL POWER – dB
CONDITIONS:
1. 125 MBd
2. PRBS 27-1
3. TA = 25° C
4. VCC = 5 Vdc
5. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 6. Bit-error-ratio vs. relative receiver
input optical power.
allowed in Section 8.2 Active Input
Interface of the FDDI PMD
standard without violating the
worst-case output electrical jitter
allowed in the Table E1 of the
Annex E.
The jitter specifications stated in
the following transmitter and
receiver specification table are
derived from the values in Table
E1 of Annex E. They represent the
worst-case jitter contribution that
the transmitter and receiver are
allowed to make to the overall
system jitter without violating the
Annex E allocation example. In
practice, the typical jitter
contribution of the Avago
Technologies’ data link modules is
well below the maximum amounts.
Recommended Handling Precautions
It is advised that normal static
precautions be taken in the
handling and assembly of these
data link modules to prevent
damage which may be induced by
electrostatic discharge (ESD). The
HFBR-1115TZ/-2115TZ series
meets MIL-STD-883C Method
3015.4 Class 2.
Care should be taken to avoid
shorting the receiver Data or
Signal Detect Outputs directly to
ground without proper currentlimiting impedance.
Solder and Wash Process
Compatibility
The transmitter and receiver are
delivered with protective process
caps covering the individual ST*
ports. These process caps protect
the optical subassemblies during
wave solder and aqueous wash
processing and act as dust covers
during shipping.
Shipping Container
The data link modules are
packaged in a shipping container
designed to protect it from
mechanical and ESD damage
during shipment or storage.
Board Layout–Interface Circuit and
Layout Guidelines
It is important to take care in the
layout of your circuit board to
achieve optimum performance
from these data link modules.
Figure 7 provides a good example
These data link modules are
compatible with either industry
standard wave- or hand-solder
processes.
Rx
Tx
*
A
L2
1
+5 Vdc
C2
0.1
GND
9 NC
NC 8
10 GND
NO 7
PIN
11 VCC
*
*
9 NC
NC 8
GND 7
GND 6
10 NO
PIN
11 GND
12 VCC
GND 5
12 GND
VCC 5
VCC 4
13 GND
GND 4
13 GND
14 D
GND 3
14 SD
D 3
DATA
15 D
VBB 2
15 SD
D 2
NC 1
NO
16 PIN
NC 1
R2
82
R4
130
R1
130
16 NC
*
L1
1
VCC 6
DATA
R3
82
of a power supply filter circuit that
works well with these parts. Also,
suggested signal terminations for
the Data, Data-bar, Signal Detect
and Signal Detect-bar lines are
shown. Use of a multilayer,
ground-plane printed circuit board
will provide good high-frequency
circuit performance with a low
inductance ground return path. See
additional recommendations noted
in the interface schematic shown in
Figure 7.
C1
0.1
C7
10
(OPTIONAL)
C3
0.1
C4
10
A
DATA
DATA
R7
82
C6
0.1
R5
82
R8
130
R6
130
R9
82
C5
0.1
R11
82
SD
SD
TERMINATE D, D
AT Tx INPUTS
TOP VIEWS
R10
130
R12
130
TERMINATE D, D, SD, SD AT
INPUTS OF FOLLOW-ON DEVICES
NOTES:
1. RESISTANCE IS IN OHMS. CAPACITANCE IS IN MICROFARADS. INDUCTANCE IS IN MICROHENRIES.
2. TERMINATE TRANSMITTER INPUT DATA AND DATA-BAR AT THE TRANSMITTER INPUT PINS. TERMINATE THE RECEIVER OUTPUT DATA, DATA-BAR, AND SIGNAL DETECT-BAR
AT THE FOLLOW-ON DEVICE INPUT PINS. FOR LOWER POWER DISSIPATION IN THE SIGNAL DETECT TERMINATION CIRCUITRY WITH SMALL COMPROMISE TO THE SIGNAL
QUALITY, EACH SIGNAL DETECT OUTPUT CAN BE LOADED WITH 510 OHMS TO GROUND INSTEAD OF THE TWO RESISTOR, SPLIT-LOAD PECL TERMINATION SHOWN IN THIS
SCHEMATIC.
3. MAKE DIFFERENTIAL SIGNAL PATHS SHORT AND OF SAME LENGTH WITH EQUAL TERMINATION IMPEDANCE.
4. SIGNAL TRACES SHOULD BE 50 OHMS MICROSTRIP OR STRIPLINE TRANSMISSION LINES. USE MULTILAYER, GROUND-PLANE PRINTED CIRCUIT BOARD FOR BEST HIGHFREQUENCY PERFORMANCE.
5. USE HIGH-FREQUENCY, MONOLITHIC CERAMIC BYPASS CAPACITORS AND LOW SERIES DC RESISTANCE INDUCTORS. RECOMMEND USE OF SURFACE-MOUNT COIL
INDUCTORS AND CAPACITORS. IN LOW NOISE POWER SUPPLY SYSTEMS, FERRITE BEAD INDUCTORS CAN BE SUBSTITUTED FOR COIL INDUCTORS. LOCATE POWER
SUPPLY FILTER COMPONENTS CLOSE TO THEIR RESPECTIVE POWER SUPPLY PINS. C7 IS AN OPTIONAL BYPASS CAPACITOR FOR IMPROVED, LOW-FREQUENCY NOISE
POWER SUPPLY FILTER PERFORMANCE.
6. DEVICE GROUND PINS SHOULD BE DIRECTLY AND INDIVIDUALLY CONNECTED TO GROUND.
7. CAUTION: DO NOT DIRECTLY CONNECT THE FIBER-OPTIC MODULE PECL OUTPUTS (DATA, DATA-BAR, SIGNAL DETECT, SIGNAL DETECT-BAR, VBB) TO GROUND WITHOUT
PROPER CURRENT LIMITING IMPEDANCE.
8. (*) OPTIONAL METAL ST OPTICAL PORT TRANSMITTER AND RECEIVER MODULES WILL HAVE PINS 8 AND 9 ELECTRICALLY CONNECTED TO THE METAL PORT ONLY AND
NOT CONNECTED TO THE INTERNAL SIGNAL GROUND.
Figure 7. Recommended interface circuitry and power supply filter circuits.
5
Board Layout–Hole Pattern
The Avago transmitter and receiver
hole pattern is compatible with
other data link modules from other
vendors. The drawing shown in
Figure 8 can be used as a guide in
the mechanical layout of your
circuit board.
Regulatory Compliance
These data link modules are
intended to enable commercial
system designers to develop
equipment that complies with the
various international regulations
governing certification of Information Technology Equipment.
Additional information is available
from your Avago sales
representative.
ered eye safe. See Application Note
1094, LED Device Classifications
with Respect to AEL Values as
Defined in the IEC 825-1
Standard and the European
EN60825-1 Directive.
All HFBR-1115TZ LED transmitters are classified as IEC-825-1
Accessible Emission Limit (AEL)
Class 1 based upon the current
proposed draft scheduled to go
into effect on January 1, 1997. AEL
Class 1 LED devices are consid-
The material used for the housing
in the HFBR-1115TZ/-2115TZ
series is Ultem 2100 (GE). Ultem
2100 is recognized for a UL
flammability rating of 94V-0 (UL
File Number E121562) and the
CSA (Canadian Standards
Association) equivalent (File
Number LS88480).
(16X) ø 0.8 ± 0.1
.032 ± .004
–A–
Ø 0.000 M A
17.78
.700
(7X) 2.54
.100
7.62
.300
TOP VIEW
UNITS = mm/INCH
Figure 8. Recommended board layout hole pattern.
6
180
4.40
1.975
1.25
3.0
4.850
1.5
10.0
160
140 2.5
120
1.025
1.00
0.975
0.90
3.5
2.0
tr/f – TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES – ns
3.0
3.5
100
1280
1300 1320
1340 1360 1380
λC – TRANSMITTER OUTPUT OPTICAL
CENTER WAVELENGTH –nm
HFBR-1115TZ FDDI TRANSMITTER TEST RESULTS
OF λC, ∆λ AND tr/f ARE CORRELATED AND
COMPLY WITH THE ALLOWED SPECTRAL WIDTH
AS A FUNCTION OF CENTER WAVELENGTH FOR
VARIOUS RISE AND FALL TIMES.
RELATIVE AMPLITUDE
∆λ – TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) –nm
200
1.525
0.525
5.6
0.075
100% TIME
INTERVAL
40 ± 0.7
0.50
± 0.725
± 0.725
0% TIME
INTERVAL
0.10
0.025
0.0
-0.025
-0.05
0.075
1.525
0.525
4.850
80 ± 500 ppm
5.6
10.0
Figure 9. HFBR-1115TZ transmitter output
optical spectral width (FWHM) vs. transmitter
output optical center wavelength and rise/fall
times.
1.975
4.40
TIME – ns
THE HFBR-1115TZ OUTPUT OPTICAL PULSE SHAPE FITS WITHIN THE BOUNDARIES
OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.
5
-31.0 dBm
4
MIN (PO + 4.0 dB OR -31.0 dBm)
OPTICAL POWER
3
2.5 x 10-10 BER
2
1.0 x 10-12 BER
1
PA (PO + 1.5 dB
< PA < -31.0 dBm)
INPUT OPTICAL POWER
(> 1.5 dB STEP INCREASE)
INPUT OPTICAL POWER
(> 4.0 dB STEP DECREASE)
-45.0 dBm
-4
-3
-2
-1
0
1
2
3
4
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1.TA = 25° C
2. VCC = 5 Vdc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 21 AND 22 APPLY.
Figure 11. HFBR-2115TZ receiver relative
input optical power vs. eye sampling time
position.
AS – MAX
ANS – MAX
SIGNAL – DETECT (ON)
SIGNAL – DETECT (OFF)
TIME
AS – MAX — MAXIMUM ACQUISITION TIME (SIGNAL).
AS – MAX IS THE MAXIMUM SIGNAL – DETECT ASSERTION TIME FOR THE STATION.
AS – MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS – MAX IS 100.0 µs.
ANS – MAX — MAXIMUM ACQUISITION TIME (NO SIGNAL).
ANS – MAX IS THE MAXIMUM SIGNAL – DETECT DEASSERTION TIME FOR THE STATION.
ANS – MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS – MAX IS 350 µs.
Figure 12. Signal detect thresholds and timing.
7
PO = MAX (PS OR -45.0 dBm)
(PS = INPUT POWER FOR BER < 102)
0
SIGNAL
DETECT
OUTPUT
RELATIVE INPUT OPTICAL POWER – dB
Figure 10. Output optical pulse envelope.
HFBR-1115TZ Transmitter Pin-Out Table
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
NC
VBB
GND
GND
GND
GND
OMIT
NC
NC
GND
VCC
VCC
GND
DATA
DATA
NC
Functional Description
No internal connect, used for mechanical strength only
VBB Bias output
Ground
Ground
Ground
Ground
No pin
No internal connect, used for mechanical strength only
No internal connect, used for mechanical strength only
Ground
Common supply voltage
Common supply voltage
Ground
Data input
Inverted Data input
No internal connect, used for mechanical strength only
Reference
Note 3
Note 3
Note 3
Note 3
Note 5
Note 5
Note 3
Note 1
Note 1
Note 3
Note 4
Note 4
HFBR-2115TZ Receiver Pin-Out Table
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
NC
DATA
DATA
VCC
VCC
VCC
GND
NC
NC
OMIT
GND
GND
GND
SD
SD
OMIT
Functional Description
No internal connect, used for mechanical strength only
Inverted Data input
Data input
Common supply voltage
Common supply voltage
Common supply voltage
Ground
No internal connect, used for mechanical strength only
No internal connect, used for mechanical strength only
No pin
Ground
Ground
Ground
Signal Detect
Inverted Signal Detect
No pin
Reference
Note 4
Note 4
Note 1
Note 1
Note 1
Note 3
Note 5
Note 5
Note 3
Note 3
Note 3
Note 2, 4
Note 2, 4
Notes:
1. Voltages on VCC must be from the same power supply (they are connected together internally).
2. Signal Detect is a logic signal that indicates the presence or absence of an input optical signal. A logic-high, VOH, on Signal Detect indicates
presence of an input optical signal. A logic-low, VOL, on Signal Detect indicates an absence of input optical signal.
3. All GNDs are connected together internally and to the internal shield.
4. DATA, DATA, SD, SD are open-emitter output circuits.
5. On metal-port modules, these pins are redefined as “Port Connection.”
8
Specifications–Absolute Maximum Ratings
Parameter
Storage Temperature
Lead Soldering Temperature
Lead Soldering Time
Supply Voltage
Data Input Voltage
Differential Input Voltage
Output Current
Symbol
TS
TSOLD
tSOLD
VCC
VI
VD
IO
Min.
-40
Symbol
TA
VCC
VIL - VCC
VIH - VCC
RL
fS
Min.
0
4.5
-1.810
-1.165
Typ.
-0.5
-0.5
Max.
100
260
10
7.0
VCC
1.4
50
Unit
°C
°C
sec.
V
V
V
mA
Reference
Max.
70
5.5
-1.475
-0.880
Unit
°C
V
V
V
Ω
MBd
Reference
Reference
Note 4
Note 7
Note 5
350
Unit
mA
W
V
µA
µA
Unit
mA
W
V
V
ns
ns
V
Reference
Note 6
Note 7
Note 8
Note 8
Note 9
Note 9
Note 8
Note 1
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltage
Data Input Voltage–Low
Data Input Voltage–High
Data and Signal Detect Output Load
Signaling Rate
10
Typ.
50
125
Note 2
Note 3
Figure 5
HFBR-1115TZ Transmitter Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.5 V to 5.5 V)
Parameter
Supply Current
Power Dissipation
Threshold Voltage
Data Input Current–Low
Data Input Current–High
Symbol
ICC
PDISS
VBB - VCC
IIL
IIH
Min.
-1.42
-350
Typ.
145
0.76
-1.3
0
14
Max.
185
1.1
-1.24
HFBR-2115TZ Receiver Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.5 V to 5.5 V)
Parameter
Supply Current
Power Dissipation
Data Output Voltage–Low
Data Output Voltage–High
Data Output Rise Time
Data Output Fall Time
Signal Detect Output
Voltage–Low (De-asserted)
Signal Detect Output
Voltage–High (Asserted)
Signal Detect Output Rise Time
Signal Detect Output Fall Time
9
Symbol
ICC
PDISS
VOL - VCC
VOH - VCC
tr
tf
VOL - VCC
Min.
Typ.
82
0.3
-1.840
-1.045
0.35
0.35
-1.840
Max.
145
0.5
-1.620
-0.880
2.2
2.2
-1.620
VOH - VCC
-1.045
-0.880
V
Note 8
tr
tf
0.35
0.35
2.2
2.2
ns
ns
Note 9
Note 9
HFBR-1115TZ Transmitter Optical Characteristics
(TA = 0°C to 70°C, VCC = 4.5 V to 5.5 V)
Parameter
Output Optical Power
62.5/125 µm, NA = 0.275 Fiber
Output Optical Power
50/125 µm, NA = 0.20 Fiber
Optical Extinction Ratio
Symbol
PO, BOL
PO, EOL
PO, BOL
PO, EOL
Output Optical Power at Logic “0” State
PO(“0”)
Min.
-19
-20
-22.5
-23.5
Typ.
-16.8
1308
1380
Unit
dBm
avg.
dBm
avg.
%
dB
dBm
avg.
nm
137
170
nm
-20.3
0.001
-50
Center Wavelength
λC
Spectral Width–FWHM
∆λ
Reference
Note 13
Note 13
Note 14
Note 15
Optical Rise Time
tr
0.6
1.0
3.0
ns
Optical Fall Time
tf
0.6
2.1
3.0
ns
DCD
0.02
0.6
ns p-p
DDJ
0.02
0.6
ns p-p
Note 16
Figure 9
Note 16
Figure 9
Note 16, 17
Figure 9, 10
Note 16, 17
Figure 9, 10
Note 18
Figure 10
Note 19
RJ
0
0.69
ns p-p
Note 20
Typ.
-33.5
Max.
-31
-34.5
-31.8
Reference
Note 21,
Figure 11
Note 22,
Figure 8
Note 21
0.02
1380
0.4
Unit
dBm
avg.
dBm
avg.
dBm
avg.
nm
ns p-p
DDJ
0.35
1.0
ns p-p
Note 11
RJ
1.0
2.14
ns p-p
Note 12
-33
Note 23, 24
Figure 9
Note 25, 26
Figure 12
Figure 9
Note 23, 24
Figure 12
Note 25, 26
Figure 12
Duty Cycle Distortion Contributed by
the Transmitter
Data Dependent Jitter Contributed by
the Transmitter
Random Jitter Contributed by the
Transmitter
1270
Max.
-14
-14
-14
-14
0.03
-35
-45
HFBR-2115TZ Receiver Optical and Electrical Characteristics
(TA = 0°C to 70°C, VCC = 4.5 V to 5.5 V)
Parameter
Input Optical Power
Minimum at Window Edge
Input Optical Power
Minimum at Eye Center
Input Optical Power Maximum
Operating Wavelength
Duty Cycle Distortion
Contributed by the Receiver
Data Dependent Jitter
Contributed by the Receiver
Random Jitter Contributed by the
Receiver
Signal Detect–Asserted
Signal Detect–De-asserted
Signal Detect–Hysteresis
Signal Detect Assert Time
(off to on)
Signal Detect De-assert Time
(on to off)
10
Symbol
PIN Min. (W)
Min.
PIN Min. (C)
PIN Max.
-14
λ
DCD
1270
-11.8
PA
PD+1.5 dB
PD
-45
PA-PD
AS_Max
1.5
0
2.4
55
100
dBm
avg.
dBm
avg.
dB
µs
ANS_Max
0
110
350
µs
Note 10
Notes:
1. This is the maximum voltage that can be
applied across the Differential Transmitter
Data Inputs to prevent damage to the input
ESD protection circuit.
2. The outputs are terminated with 50 Ω
connected to VCC - 2 V.
3. The specified signaling rate of 10 MBd to
125 MBd guarantees operation of the
transmitter and receiver link to the full
conditions listed in the FDDI Physical
Layer Medium Dependent standard.
Specifically, the link bit-error-ratio will be
equal to or better than 2.5 x 10-10 for any
valid FDDI pattern. The transmitter section
of the link is capable of dc to 125 MBd.
The receiver is internally ac-coupled which
limits the lower signaling rate to 10 MBd.
For purposes of definition, the symbol rate
(Baud), also called signaling rate, fs, is the
reciprocal of the symbol time. Data rate
(bits/sec) is the symbol rate divided by the
encoding factor used to encode the data
(symbols/bit).
4. The power supply current needed to
operate the transmitter is provided to
differential ECL circuitry. This circuitry
maintains a nearly constant current flow
from the power supply. Constant current
operation helps to prevent unwanted
electrical noise from being generated and
conducted or emitted to neighboring
circuitry.
5. This value is measured with an output load
RL = 10 kΩ.
6. This value is measured with the outputs
terminated into 50 Ω connected to VCC - 2
V and an Input Optical Power level of
-14 dBm average.
7. The power dissipation value is the power
dissipated in the transmitter and receiver
itself. Power dissipation is calculated as
the sum of the products of supply voltage
and currents, minus the sum of the
products of the output voltages and
currents.
8. This value is measured with respect to VCC
with the output terminated into 50 Ω
connected to VCC - 2 V.
9. The output rise and fall times are
measured between 20% and 80% levels
with the output connected to VCC - 2 V
through 50 Ω.
10. Duty Cycle Distortion contributed by the
receiver is measured at the 50% threshold
using an IDLE Line State, 125 MBd (62.5
MHz square-wave), input signal. The input
optical power level is -20 dBm average.
See Application Information–Data Link
Jitter Section for further information.
11. Data Dependent Jitter contributed by the
receiver is specified with the FDDI DDJ
test pattern described in the FDDI PMD
Annex A.5. The input optical power level is
-20 dBm average. See Application
Information–Data Link Jitter Section for
further information.
11
12. Random Jitter contributed by the receiver
is specified with an IDLE Line State,
125 MBd (62.5 MHz square-wave), input
signal. The input optical power level is at
the maximum of “PIN Min. (W).” See
Application Information–Data Link Jitter
Section for further information.
13. These optical power values are measured
with the following conditions:
• The Beginning of Life (BOL) to the Endof
Life (EOL) optical power degradation is
typically 1.5 dB per the industry
convention for long wavelength LEDs.
The actual degradation observed in
Avago Technologie’s 1300 nm LED
products is < 1dB, as specified in this
data sheet.
• Over the specified operating voltage and
temperature ranges.
• With HALT Line State, (12.5 MHz
square-wave), input signal.
• At the end of one meter of noted optical
fiber with cladding modes removed.
The average power value can be
converted to a peak power value by
adding 3 dB. Higher output optical
power transmitters are available on
special request.
14. The Extinction Ratio is a measure of the
modulation depth of the optical signal.
The data “0” output optical power is
compared to the data “1” peak output
optical power and expressed as a
percentage. With the transmitter driven by
a HALT Line State (12.5 MHz squarewave) signal, the average optical power is
measured. The data “1” peak power is
then calculated by adding 3 dB to the
measured average optical power. The data
“0” output optical power is found by
measuring the optical power when the
transmitter is driven by a logic “0” input.
The extinction ratio is the ratio of the
optical power at the “0” level compared to
the optical power at the “1” level
expressed as a percentage or in decibels.
15. The transmitter provides compliance with
the need for Transmit_Disable commands
from the FDDI SMT layer by providing an
Output Optical Power level of