HSMP-386L-TR2

HSMP-386x Surface Mount PIN Diodes Data Sheet Description/Applications Features The HSMP-386x series of general purpose PIN diodes are designed for two classes of applications. The first is attenuators where current consumption is the most important design consideration. The second application for this series of diodes is in switches where low capacitance is the driving issue for the designer. • The HSMP-386x series Total Capacitance (C T ) and Total Resistance (RT ) are typical specifications. For applications that require guaranteed performance, the general purpose HSMP-383x series is recommended. Unique Configurations in Surface Mount Packages – Add Flexibility – Save Board Space – Reduce Cost • Switching – Low Distortion Switching – Low Capacitance • Attenuating – Low Current Attenuating for Less Power Consumption A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime. • Matched Diodes for Consistent Performance Pin Connections and Package Marking, SOT-363 • Low Failure in Time (FIT) Rate[1] 2 3 LUx 1 6 5 4 Notes: 1. Package marking provides orientation, identification, and date code. 2. See “Electrical Specifications” for appropriate package marking. • Better Thermal Conductivity for Higher Power Dissipation • Lead-free Note: 1. For more information see the Surface Mount PIN Reliability Data Sheet. Package Lead Code Identification, SOT-23, SOT-143 (Top View) SINGLE Package Lead Code Identification, SOT-323 (Top View) SERIES Package Lead Code Identification, SOT-363 (Top View) SERIES SINGLE #0 #2 B C COMMON ANODE COMMON CATHODE COMMON ANODE COMMON CATHODE #3 #4 E F UNCONNECTED TRIO 6 5 1 2 4 L 3 RING QUAD 4 3 1 D 2 See separate data sheet HSMP-386D Absolute Maximum Ratings[1] TC = +25°C Symbol Parameter Unit SOT-23 SOT-323 If Forward Current (1 µs Pulse) Amp 1 1 PIV Peak Inverse Voltage V 50 50 Tj Junction Temperature °C 150 150 Tstg Storage Temperature °C -65 to 150 -65 to 150 qjc Thermal Resistance °C/W 500 150 [2] ESD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge. Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board. Electrical Specifications TC = 25°C, each diode PIN General Purpose Diodes, Typical Specifications TA = 25°C Part Number HSMP- 3860 3862 3863 3864 386B 386C 386E 386F 386L Package Marking Lead Code Code Configuration L0 L2 L3 L4 L0 L2 L3 L4 LL 0 Single 2 Series 3 Common Anode 4 Common Cathode B Single C Series E Common Anode F Common Cathode L Unconnected Trio    Test Conditions 2 Minimum Typical Typical Breakdown Series Resistance Total Capacitance Voltage VBR (V) RS (Ω) CT (pF) 50 VR = VBR Measure IR ≤ 10 µA 3.0/1.5* IF = 10 mA f = 100 MHz IF = 100 mA* 0.20 VR = 50 V f = 1 MHz HSMP-386x Typical Parameters at TC = 25°C Part Number HSMP- Total Resistance RT (Ω) 386x Carrier Lifetime t (ns) 22 Reverse Recovery Time Trr (ns) 500 Total Capacitance CT (pF) 80    Test Conditions IF = 1 mA IF = 50 mA f = 100 MHz TR = 250 mA 0.20 VR = 10 V IF = 20 mA 90% Recovery VR = 50 V f = 1 MHz Typical Performance, TC = 25°C, each diode 1000 1 MHz 0.25 100 MHz 0.20 0.15 1 GHz 0 2 4 6 8 100 10 1 0.01 10 12 14 16 18 20 0.1 1 10 100 Figure 1. RF Capacitance vs. Reverse Bias. Figure 2. Typical RF Resistance vs. Forward Bias Current. 1000 VR = 10 V 100 VR = 20 V 10 10 20 30 FORWARD CURRENT (mA) Figure 4. Reverse Recovery Time vs. Forward Current for Various Reverse Voltages. IF – FORWARD CURRENT (mA) 100 VR = 5 V 10 1 0.1 0.01 125 C 25 C –50 C 0 0.2 0.4 0.6 0.8 1.0 1.2 VF – FORWARD VOLTAGE (mA) Figure 5. Forward Current vs. Forward Voltage. Equivalent Circuit Model HSMP-386x Chip* Rs Rj 1.5 Ω Cj 0.12 pF 3 115 110 Diode Mounted as a Series Switch in a 50 Microstrip and Tested at 123 MHz 105 100 95 90 85 1 10 30 IF – FORWARD BIAS CURRENT (mA) BIAS CURRENT (mA) REVERSE VOLTAGE (V) Trr – REVERSE RECOVERY TIME (ns) 120 TA = +85 C TA = +25 C TA = –55 C INPUT INTERCEPT POINT (dBm) 0.30 RESISTANCE (OHMS) TOTAL CAPACITANCE (pF) 0.35 RT = 1.5 + R j CT = CP + Cj 12 R j = 0.9 Ω I I = Forward Bias Current in mA � * See AN1124 for package models Figure 3. 2nd Harmonic Input Intercept Point vs. Forward Bias Current for Switch Diodes. Typical Applications for Multiple Diode Products RF COMMON RF COMMON RF 1 RF 2 BIAS 1 RF 2 RF 1 BIAS 2 BIAS Figure 6. Simple SPDT Switch, Using Only Positive Current. BIAS Figure 7. High Isolation SPDT Switch, Dual Bias. RF COMMON RF COMMON BIAS RF 1 RF 2 RF 2 RF 1 BIAS Figure 8. Switch Using Both Positive and Negative Current. Figure 9. Very High Isolation SPDT Switch, Dual Bias. VARIABLE BIAS RF IN/OUT INPUT FIXED BIAS VOLTAGE Figure 10. Four Diode p Attenuator. See AN1048 for details. Figure 10. Four Diode π Attenuator. See AN1048 for details. 4 Typical Applications for Multiple Diode Products (continued) BIAS “ON” “OFF” 1 1 +V 0 2 0 +V 1 6 5 4 1 2 3 RF out RF in 2 Figure 11. High Isolation SPST Switch Figure 11. High Isolation SPST Switch (Repeat Cells as Required). (Repeat Cells as Required). Figure 12. HSMP-386L Unconnected Trio used in a Positive Voltage, High Isolation Switch. 1 2 0 3 2 1 4 5 6 3 2 “ON” “OFF” 1 b1 b2 3 2 1 4 5 6 1 0 0 2 +V –V 1 b3 RF in Figure 13. HSMP-386L used in a SP3T Switch. 5 Figure 14. HSMP-386L Unconnected Trio used in a Dual Voltage, High Isolation Switch. RF out Ordering Information Specify part number followed by option. For example: HSMP - 386x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” Assembly Information 0.026 SOT-323 PCB Footprint Recommended PCB pad layouts for the miniature SOT packages are shown in Figures 15, 16, 17. These layouts provide ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.079 0.039 0.026 0.018 Dimensions in inches 0.079 Figure 16. Recommended PCB Pad Layout for Avago’s SC70 6L/SOT-363 Products. 0.039 1 0.039 0.039 1 0.022 Dimensions in inches Figure 15. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT‑323 Products. 0.079 2.0 0.035 0.9 0.031 0.8 Dimensions in inches mm Figure 17. Recommended PCB Pad Layout for Avago’s ­­SOT-23 Products. 6 SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT package, will reach solder reflow temperatures faster than those with a greater mass. Avago’s diodes have been qualified to the time-temperature profile shown in Figure 18. This profile is representative of an IR reflow type of surface mount assembly process. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 260°C. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. tp Tp Critical Zone T L to Tp Ramp-up Temperature TL Ts Ts tL max min Ramp-down ts Preheat 25 t 25° C to Peak Time Figure 18. Surface Mount Assembly Profile. Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C) Reflow Parameter Lead-Free Assembly Average ramp-up rate (Liquidus Temperature (TS(max) to Peak) 3°C/ second max Preheat Temperature Min (TS(min)) 150°C Temperature Max (TS(max)) 200°C Time (min to max) (tS) 60-180 seconds Ts(max) to TL Ramp-up Rate Time maintained above: 3°C/second max Temperature (TL) 217°C Time (tL) 60-150 seconds Peak Temperature (TP) 260 +0/-5°C Time within 5 °C of actual Peak temperature (tP) 20-40 seconds Ramp-down Rate 6°C/second max Time 25 °C to Peak Temperature 8 minutes max Note 1: All temperatures refer to topside of the package, measured on the package body surface 7 Package Dimensions Outline 23 (SOT-23) Outline SOT-323 (SC-70, 3 Lead) e1 e2 e1 XXX E XXX E E1 e e L B L DIMENSIONS (mm) C DIMENSIONS (mm) D A A1 Notes: XXX-package marking Drawings are not to scale SYMBOL A A1 B C D E1 e e1 e2 E L MIN. 0.79 0.000 0.30 0.08 2.73 1.15 0.89 1.78 0.45 2.10 0.45 MAX. 1.20 0.100 0.54 0.20 3.13 1.50 1.02 2.04 0.60 2.70 0.69 A A1 Notes: XXX-package marking Drawings are not to scale Outline 363 (SC-70, 6 Lead) HE E L e c D DIMENSIONS (mm) A2 b Package Characteristics A SYMBOL E D HE A A2 A1 e b c L MIN. MAX. 1.15 1.35 1.80 2.25 1.80 2.40 0.80 1.10 0.80 1.00 0.00 0.10 0.650 BCS 0.15 0.30 0.08 0.25 0.10 0.46 Lead Material............................................ Copper (SOT-323/363); Alloy 42 (SOT-23) Lead Finish.......................................................................... Tin 100% (Lead-free option) Maximum Soldering Temperature............................................. 260°C for 5 seconds Minimum Lead Strength............................................................................ 2 pounds pull Typical Package Inductance....................................................................................... 2 nH Typical Package Capacitance...............................................0.08 pF (opposite leads) 8 C D B A1 E1 SYMBOL A A1 B C D E1 e e1 E L MIN. MAX. 0.80 1.00 0.00 0.10 0.15 0.40 0.08 0.25 1.80 2.25 1.10 1.40 0.65 typical 1.30 typical 1.80 2.40 0.26 0.46 Device Orientation REEL CARRIER TAPE USER FEED DIRECTION COVER TAPE For Outlines SOT-23, -323 For Outline SOT-363 TOP VIEW END VIEW TOP VIEW 4 mm 8 mm ABC ABC ABC 8 mm ABC Tape Dimensions and Product Orientation For Outline SOT-23 P P2 D E P0 F W D1 t1 Ko 9 MAX 13.5 MAX 8 MAX B0 A0 DESCRIPTION SYMBOL ABC ABC ABC ABC Note: "AB" represents package marking code. "C" represents date code. Note: "AB" represents package marking code. "C" represents date code. SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 3.15 ± 0.10 2.77 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.05 0.124 ± 0.004 0.109 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 ± 0.002 PERFORATION DIAMETER PITCH POSITION D P0 E 1.50 + 0.10 4.00 ± 0.10 1.75 ± 0.10 0.059 + 0.004 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 + 0.30 - 0.10 0.229 ± 0.013 0.315 + 0.012 - 0.004 0.009 ± 0.0005 DISTANCE BETWEEN CENTERLINE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 9 END VIEW 4 mm Tape Dimensions and Product Orientation For Outlines SOT-323, -363 P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) K0 An A0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.0 4 ± 0.004 0.0 4 ± 0.004 0.04 ± 0.004 0.15 ± 0.004 0.0 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 ± 0.05 4.00 ± 0.10 1. 5 ± 0.10 0.0 1 ± 0.002 0.15 ± 0.004 0.0 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 .00 ± 0. 0 0.254 ± 0.02 0. 15 ± 0.012 0.0100 ± 0.000 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.0 2 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F .50 ± 0.05 0.1 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.0 ± 0.002 FOR SOT 2 (SC 0 LEAD) An FOR SOT (SC 0 LEAD) An B0 CAVITY ANGLE Tt (COVER TAPE THICKNESS) ° C MA 10° C MA For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes 5989-4028EN AV02-0293EN - October 21, 2013