HSMP-3892-TR1

HSMP-389x Series, HSMP-489x Series Surface Mount RF PIN Switch Diodes Data Sheet Description/Applications Features The HSMP-389x series is ­optimized for switching applications where low resistance at low current and low capacitance are required. The HSMP-489x series products feature ultra low parasitic inductance. These products are specifically ­ designed for use at frequencies which are much higher than the upper limit for conventional PIN diodes. • Unique Configurations in Surface Mount Packages Pin Connections and Package Marking – Add Flexibility – Save Board Space – Reduce Cost • Switching – Low Capacitance – Low Resistance at Low Current • Low Failure in Time (FIT) Rate[1] 1 3 GUx 2 6 • Matched Diodes for Consistent Performance 5 • Lead-free 4 Notes: 1. Package marking provides orientation, identification, and date code. 2. See “Electrical Specifications” for appropriate package marking. • Better Thermal Conductivity for Higher Power Dissipation Note: 1. For more information see the Surface Mount PIN Reliability Data Sheet. Package Lead Code Identification, SOT-23/143 (Top View) SINGLE Package Lead Code Identification, SOT-323 (Top View) SERIES Package Lead Code Identification, SOT-363 (Top View) SERIES SINGLE 6 #0 #2 B C COMMON ANODE COMMON CATHODE COMMON ANODE COMMON CATHODE #4 UNCONNECTED PAIR DUAL ANODE #5 4890 E 3 1 #7 2 L 4 6 3 1 LOW INDUCTANCE SINGLE 5 4 6 3 1 DUAL SWITCH MODEL 5 2 4 R SERIES– SHUNT PAIR 5 4 1 DUAL ANODE 6 2 T 2 U HIGH FREQUENCY SERIES 1 4 5 2 4 V 3 2 UNDER DEVELOPMENT Absolute Maximum Ratings[1] TC = +25°C Symbol Parameter Unit SOT-23/143 SOT-323/363 If Forward Current (1 µs Pulse) Amp 1 1 PIV Peak Inverse Voltage V 100 100 Tj Junction Temperature °C 150 150 Tstg Storage Temperature °C -65 to 150 -65 to 150 θjc Thermal Resistance[2] °C/W 500 150 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board. ESD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge.  3 F 489B RING QUAD 5 1 6 #3 UNCONNECTED TRIO 3 Electrical Specifications, TC = 25°C, each diode Part Number HSMP- Package Marking Lead Code Code Configuration 3890 3892 3893 3894 3895 389B 389C 389E 389F 389L 389R 389T 389U 389V G0 [1] G2[1] G3[1] G4[1] G5 [1] G0 [2] G2[2] G3[2] G4[2] GL[2] S [2] Z[2] GU[2] GV[2] 0 2 3 4 5 B C E F L R T U V    Test Conditions Minimum Breakdown Voltage VBR (V) Maximum Series Resistance RS (ý) Maximum Total Capacitance CT (pF) 100 2.5 0.30 VR = VBR Measure IR ­ 10 µA IF = 5 mA f = 100 MHz VR = 5 V f = 1 MHz Single Series Common Anode Common Cathode Unconnected Pair Single Series Common Anode Common Cathode Unconnected Trio Dual Switch Mode Low Inductance Single Series-Shunt Pair High Frequency Series Pair Notes: 1. Package marking code is white. 2. Package is laser marked. High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes Part Package Number Marking HSMP- Code[1] Configuration 489x   Test Conditions   Minimum Breakdown Voltage VBR (V) Maximum Series Resistance R S (ý) Typical Total Capacitance C T (pF) Maximum Total Capacitance CT (pF) Typical Total Inductance LT (nH) GA Dual Anode 100 2.5 0.33 0.375 1.0 VR = VBR Measure IR ­ 10 µA IF = 5 mA f = 1 MHz VR = 5 V VR = 5 V f = 1 MHz f=500 MHz– 3 GHz Note: 1. SOT-23 package marking code is white; SOT-323 is laser marked. Typical Parameters at TC = 25°C Part Number HSMP- Series Resistance R S (ý) Carrier Lifetime τ (ns) Total Capacitance C T (pF) 0.20 @ 5V 389x 3.8 200   Test Conditions   IF = 1 mA f = 100 MHz IF = 10 mA IR = 6 mA  HSMP-389x Series Typical Performance, TC = 25°C, each diode 1 0.1 1 10 0.50 0.45 0.40 0.35 0.30 1 MHz 0.25 0.20 100 1 GHz 0 Figure 1. Total RF Resistance at 25 C vs. Forward Bias Current. 8 12 16 110 Diode Mounted as a Series Attenuator in a 50 Ohm Microstrip and Tested at 123 MHz 105 100 95 90 85 20 1 10 30 IF – FORWARD BIAS CURRENT (mA) Figure 3. 2nd Harmonic Input Intercept Point vs. Forward Bias Current. Figure 2. Capacitance vs. Reverse Voltage. 200 100 160 IF – FORWARD CURRENT (mA) Trr – REVERSE RECOVERY TIME (nS) 4 115 VR – REVERSE VOLTAGE (V) IF – FORWARD BIAS CURRENT (mA) VR = –2V 120 80 VR = –5V 40 VR = –10V 0 10 INPUT INTERCEPT POINT (dBm) 10 0.1 0.01 120 0.55 TOTAL CAPACITANCE (pF) RF RESISTANCE (OHMS) 100 15 20 25 30 10 1 0.1 0.01 125 C 25 C –50 C 0 0.2 0.4 0.6 0.8 1.0 1.2 FORWARD CURRENT (mA) VF – FORWARD VOLTAGE (V) Figure 4. Typical Reverse Recovery Time vs. Reverse Voltage. Figure 5. Forward Current vs. Forward Voltage. Typical Applications for Multiple Diode Products 1 2 2 3 2 “ON” “OFF” 3 1 1 0 4 5 3 2 1 4 5 6 1 0 0 2 +V –V 1 6 b1 b2 b3 RF in RF out Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation Switch. Figure 6. HSMP-389L used in a SP3T Switch.  Typical Applications for Multiple Diode Products (continued) “ON” “OFF” 1 1 +V 0 2 0 +V RF out 1 6 5 4 1 2 3 RF out RF in 2 4 1 2 3 Figure 9. HSMP-389T used in a Low Inductance Shunt Mounted Switch. Bias Xmtr Ant 5 RF in Figure 8. HSMP-389L Unconnected Trio used in a Positive Voltage, High Isolation Switch. Bias 6 Ant λ 4 C C Rcvr Bias λ 4 Xmtr Rcvr Antenna bias Xmtr PA HSMP-389V λ 4 LNA λ 4 HSMP-389U Rcvr Figure 10. HSMP-389U Series/Shunt Pair used in a 900 MHz Transmit/Receive Switch.  Figure 11. HSMP-389V Series/Shunt Pair used in a 1.8 GHz Transmit/Receive Switch. Typical Applications for Multiple Diode Products (continued) RF COMMON RF COMMON RF 2 RF 1 RF 1 RF 2 BIAS 1 BIAS 2 BIAS Figure 12. Simple SPDT Switch, Using Only Positive Current. BIAS Figure 13. High Isolation SPDT Switch, Dual Bias. RF COMMON RF COMMON BIAS RF 1 RF 2 RF 2 RF 1 BIAS Figure 14. Switch Using Both Positive and Negative Bias Current.  Figure 15. Very High Isolation SPDT Switch, Dual Bias. Typical Applications for HSMP-489x Low Inductance Series Equivalent Circuit Model Microstrip Series Connection for HSMP-489x Series In order to take full advantage of the low inductance of the HSMP‑489x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 17. HSMP-389x Chip* Rs Rj 0.5 Ω Cj 3 1 2 HSMP-489x Figure 16. Internal Connections. Figure 16. Internal Connections. 0.12 pF* * Measured at -20 V RT = 0.5 + R j CT = CP + Cj 20 R j = 0.9 Ω I I = Forward Bias Current in mA * See AN1124 for package models Co-Planar Waveguide Shunt Connection for HSMP-489x Series Figure 17. Circuit17. Layout. Figure Circuit Layout. Microstrip Shunt Connections for HSMP-489x Series In Figure 18, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-489x diode are placed across the resulting gap. This forces the 1.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nH of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 20. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. Co-Planar Waveguide Groundplane Center Conductor Groundplane 50 OHM MICROSTRIP LINES 20. Circuit Layout. FigureFigure 20. Circuit Layout. 0.3 pF PAD CONNECTED TO GROUND BY TWO VIA HOLES 0.75 nH Figure 18.18. Circuit Layout.Layout. Figure Circuit 1.5 nH 1.5 nH 0.3 pF 0.3 nH 0.3 nH FigureFigure 19. Equivalent Circuit. 19. Equivalent Circuit.  Figure 21. Equivalent Circuit. Figure 21. Equivalent Circuit. A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime. Assembly Information 0.026 0.075 0.035 0.016 Figure 22. PCB Pad Layout, SOT-363. (dimensions in inches). 0.026 0.07 0.035 0.016 Figure 23. PCB Pad Layout, SOT-323. (dimensions in inches). 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 DIMENSIONS IN inches mm Figure 24. PCB Pad Layout, SOT-23. SOT-23 Footprint 0.112 2.85 0.079 2 0.033 0.85 0.075 1.9 0.071 1.8 0.041 1.05 0.108 2.75 0.033 0.85 0.047 1.2 0.031 0.033 0.8 0.85 DIMENSIONS IN inches mm Figure 25. PCB Pad Layout, SOT-143.  SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT package, will reach solder reflow temperatures faster than those with a greater mass. zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 260°C. Avago Technologies’ diodes have been qualified to the time-temperature profile shown in Figure 26. This profile is representative of an IR reflow type of surface mount assembly process. These parameters are typical for a surface mount assembly process for Avago Technologies diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat tp Tp Critical Zone T L to Tp Ramp-up Temperature TL Ts Ts tL max min Ramp-down ts Preheat 25 t 25° C to Peak Time Figure 26. Surface Mount Assembly Profile. Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C) Reflow Parameter Lead-Free Assembly Average ramp-up rate (Liquidus Temperature (TS(max) to Peak) 3°C/ second max Preheat Temperature Min (TS(min)) 150°C Temperature Max (TS(max)) 200°C Time (min to max) (tS) 60-180 seconds Ts(max) to TL Ramp-up Rate Time maintained above: 3°C/second max Temperature (TL) 217°C Time (tL) 60-150 seconds Peak Temperature (TP) 260 +0/-5°C Time within 5 °C of actual Peak temperature (tP) 20-40 seconds Ramp-down Rate 6°C/second max Time 25 °C to Peak Temperature 8 minutes max Note 1: All temperatures refer to topside of the package, measured on the package body surface  Package Dimensions Outline 23 (SOT-23) Outline SOT-323 (SC-70 3 Lead) e1 e2 e1 XXX E XXX E E1 E1 e e L B L C D B DIMENSIONS (mm) C DIMENSIONS (mm) D A A1 Notes: XXX-package marking Drawings are not to scale SYMBOL A A1 B C D E1 e e1 e2 E L MIN. 0.79 0.000 0.30 0.08 2.73 1.15 0.89 1.78 0.45 2.10 0.45 MAX. 1.20 0.100 0.54 0.20 3.13 1.50 1.02 2.04 0.60 2.70 0.69 Outline 143 (SOT-143) A A1 Notes: XXX-package marking Drawings are not to scale SYMBOL A A1 B C D E1 e e1 E L MIN. MAX. 0.80 1.00 0.00 0.10 0.15 0.40 0.08 0.25 1.80 2.25 1.10 1.40 0.65 typical 1.30 typical 1.80 2.40 0.26 0.46 Outline SOT-363 (SC-70 6 Lead) e2 e1 HE B1 E XXX E E1 L e c D DIMENSIONS (mm) L B e C A1 D A A1 Notes: XXX-package marking Drawings are not to scale 10 A2 DIMENSIONS (mm) SYMBOL A A1 B B1 C D E1 e e1 e2 E L MIN. 0.79 0.013 0.36 0.76 0.086 2.80 1.20 0.89 1.78 0.45 2.10 0.45 MAX. 1.097 0.10 0.54 0.92 0.152 3.06 1.40 1.02 2.04 0.60 2.65 0.69 b A SYMBOL E D HE A A2 A1 e b c L MIN. MAX. 1.15 1.35 1.80 2.25 1.80 2.40 0.80 1.10 0.80 1.00 0.00 0.10 0.650 BCS 0.15 0.30 0.08 0.25 0.10 0.46 Package Characteristics Lead Material Lead Finish Maximum Soldering Temperature Minimum Lead Strength Typical Package Inductance Typical Package Capacitance Copper (SOT-323/363); Alloy 42 (SOT-23/143) Tin 100% 260°C for 5 seconds 2 pounds pull 2 nH 0.08 pF (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 389x - xxx Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” Device Orientation For Outlines SOT-23, -323 REEL TOP VIEW END VIEW 4 mm CARRIER TAPE 8 mm USER FEED DIRECTION ABC For Outline SOT-143 TOP VIEW END VIEW TOP VIEW ABC END VIEW 4 mm ABC ABC Note: "AB" represents package marking code. "C" represents date code. 11 ABC For Outline SOT-363 4 mm ABC ABC Note: "AB" represents package marking code. "C" represents date code. COVER TAPE 8 mm ABC 8 mm ABC ABC ABC ABC Note: "AB" represents package marking code. "C" represents date code. Tape Dimensions and Product Orientation For Outline SOT-23 P P2 D E P0 F W D1 t1 Ko 9 MAX 13.5 MAX 8 MAX B0 A0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 3.15 ± 0.10 2.77 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.05 0.124 ± 0.004 0.109 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 ± 0.002 PERFORATION DIAMETER PITCH POSITION D P0 E 1.50 + 0.10 4.00 ± 0.10 1.75 ± 0.10 0.059 + 0.004 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 + 0.30 – 0.10 0.229 ± 0.013 0.315 + 0.012 – 0.004 0.009 0.0005 DISTANCE BETWEEN CENTERLINE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 For Outline SOT-143 P D P2 P0 E F W D1 t1 9° MAX 9° MAX K0 A0 B0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 3.19 ± 0.10 2.80 ± 0.10 1.31 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.126 ± 0.004 0.110 ± 0.004 0.052 ± 0.004 0.157 ± 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.50 + 0.10 4.00 ± 0.10 1.75 ± 0.10 0.059 + 0.004 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 + 0.30 –0.10 0.254 ± 0.013 0.315+ 0.012 –0.004 0.0100 0.0005 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 12 Tape Dimensions and Product Orientation For Outlines SOT-323, -363 P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) K0 An A0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.094 ± 0.004 0.094 ± 0.004 0.047 ± 0.004 0.157 ± 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 ± 0.30 0.254 ± 0.02 0.315 ± 0.012 0.0100 ± 0.0008 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 FOR SOT-323 (SC70-3 LEAD) An 8° C MAX FOR SOT-363 (SC70-6 LEAD) An B0 CAVITY ANGLE Tt (COVER TAPE THICKNESS) 10° C MAX For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-0486EN AV02-0813EN - June 2, 2009