HSMP-4820-BLKG

HSMP-382x, 482x Surface Mount RF PIN Switch and Limiter Diodes Data Sheet Description/Applications Features The HSMP-382x series is ­ optimized for switch­ing applications where ultra-low resistance is required. The HSMP-482x diode is ideal for limiting and low inductance switching applications up to 1.5 GHz. • Diodes Optimized for: Low Current Switching Low Distortion Attenuating A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime. • Surface Mount SOT-23 and SOT-323 Packages Single and Dual Versions Tape and Reel Options Available • Power Limiting /Circuit Protection • Low Failure in Time (FIT) Rate[1] • Lead-free Note: 1. For more information see the Surface Mount PIN Reliability Data Sheet. Package Lead Code Identification, SOT-23 (Top View) Package Lead Code Identification, SOT-323 (Top View) SINGLE SERIES DUAL ANODE #0 #2 HSMP-482B COMMON ANODE COMMON CATHODE #3 #4 DUAL ANODE HSMP-4820 Absolute Maximum Ratings[1] TC = +25°C Symbol Parameter Unit SOT-23 Amp 1 1 Peak Inverse Voltage V 50 50 Tj Junction Temperature °C 150 150 Tstg Storage Temperature °C -65 to 150 -65 to 150 θjc Thermal Resistance[2] °C/W 500 150 If Forward Current (1 µs Pulse) PIV SOT-323 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board. Electrical Specifications TC = 25°C Part Number HSMP- 3820 3822 3823 3824    Test Conditions Package Marking Lead Code Code Configuration Minimum Breakdown Voltage VBR (V) Maximum Series Resistance RS (Ω) Maximum Total Capacitance CT (pF) F0 F2 F3 F4 0 2 3 4 Single Series Common Anode Common Cathode 50 0.6 0.8 VR = VBR Measure IR ≤ 10 µA f = 100 MHz IF = 10 mA f = 1 MHz VR = 20 V High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes Part Package Number Marking Lead HSMP- Code Code Configuration 4820 482B FA FA   Test Conditions   A A Dual Anode Dual Anode Minimum Breakdown Voltage VBR (V) Maximum Series Resistance RS (Ω) Typical Total Capacitance CT (pF) Maximum Total Capacitance CT (pF) Typical Total Inductance LT (nH) 50 0.6 0.75 1.0 1.0 VR = VBR Measure IR ≤ 10 µA IF = 10 mA f = 1 MHz VR = 20 V f = 1 MHz VR = 0 V f = 500 MHz­­ – 3 GHz Typical Parameters at TC = 25°C Part Number HSMP- Series Resistance RS (Ω) Carrier Lifetime τ (ns) Reverse Recovery Time Trr (ns) Total Capacitance CT (pF) 382x 1.5 70 7 0.60 @ 20 V f = 100 MHz IF = 10 mA IF = 10 mA VR = 10 V IF = 20 mA 90% Recovery    Test Conditions  Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode 1 0.1 25C 125C 0 0.2 0.4 –50C 0.6 0.8 1.0 100 VR = 2V VR = 5V 10 VR = 10V 1 10 1.2 1 0.1 0.01 0.1 1 10 100 IF – FORWARD BIAS CURRENT (mA) 30 Figure 2. Reverse Recovery Time vs. Forward Current for Various Reverse Voltages. Figure 3. RF Resistance at 25C vs. Forward Bias Current. 120 1.4 1.0 0.8 0 10 20 30 40 105 100 95 50 25 15 85 0 10 30 1.0 GHz 10 5 1 1.5 GHz 20 90 VR – REVERSE VOLTAGE (V) Figure 4. Capacitance vs. Reverse Voltage. CW POWER OUT (dBm) 1.2 30 Diode Mounted as a Series Attenuator in a 115 50 Ohm Microstrip and Tested at 123 MHz 110 INPUT INTERCEPT POINT (dBm) CAPACITANCE (pF) 20 10 FORWARD CURRENT (mA) VF – FORWARD VOLTAGE (mA) Figure 1. Forward Current vs. Forward Voltage. 0.6 RF RESISTANCE (OHMS) 10 0.01 100 Trr – REVERSE RECOVERY TIME (ns) IF – FORWARD CURRENT (mA) 100 Measured with external bias return 0 5 Figure 5. 2nd Harmonic Input Intercept Point vs. Forward Bias Current. 10 15 20 25 30 35 40 CW POWER IN (dBm) IF – FORWARD BIAS CURRENT (mA) Figure 6. Large Signal Transfer Curve of the HSMP-482x Limiter. Typical Applications for Multiple Diode Products RF COMMON RF COMMON RF 1 BIAS 1 RF 2 BIAS 2 Figure 7. Simple SPDT Switch, Using Only Positive Current.  RF 1 BIAS Figure 8. High Isolation SPDT Switch, Dual Bias. RF 2 BIAS Typical Applications for Multiple Diode Products, continued RF COMMON RF COMMON BIAS RF 1 RF 2 RF 2 RF 1 BIAS Figure 9. Switch Using Both Positive and Negative Bias Current. Figure 10. Very High Isolation SPDT Switch, Dual Bias. BIAS 11.Isolation High Isolation SPST(Repeat SwitchCells as Required. FigureFigure 11. High SPST Switch (Repeat Cells as Required).  Figure 12. Power Limiter Using HSMP-3822 Figure 12.Diode Power Pair. Limiter Using HSMP-3822Note Diode1050 Pair. See Application See Application Note 1050 for details. for details. Typical Applications for HSMP-482x Low Inductance Series 1.5 nH 1.5 nH Microstrip Series Connection for HSMP-482x Series 0.8 pF In order to take full advantage of the low inductance of the HSMP‑482x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 14. 0.3 nH 3 0.3 nH 1 2 HSMP-482x Figure Internal Connections. Figure 13. 13. Internal Connections. Figure 16.16. Equivalent Circuit. Circuit. Figure Equivalent Co-Planar Waveguide Shunt Connection for HSMP-482x Series Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 17. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. See AN1050 for details. Figure 14. Circuit Layout. Figure 14. Circuit Layout. Co-Planar Waveguide Groundplane Microstrip Shunt Connections for HSMP-482x Series In Figure 15, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-482x diode are placed across the resulting gap. This forces the 0.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nH of shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. 50 OHM MICROSTRIP LINES Center Conductor Groundplane Figure17. 17.Circuit Circuit Layout. Figure Layout. 0.8 pF 0.75 nH Figure 18. Equivalent Circuit. Figure 18. Equivalent Circuit. PAD CONNECTED TO GROUND BY TWO VIA HOLES Figure 15. 15. CircuitCircuit Layout, HSMP-482x Figure Layout,Limiter. HSMP-482x Limiter.  Assembly Information SOT-323 PCB Footprint A recommended PCB pad layout for the miniature SOT323 (SC-70) package is shown in Figure 19 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.026 0.079 0.039 0.022 Dimensions in inches Figure 19. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products. SOT-23 PCB Footprint 0.039 1 0.039 1 0.079 2.0 0.035 0.9 0.031 0.8 Dimensions in inches mm Figure 20. Recommended PCB Pad Layout for Avago’s SOT-23 Products.  SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-323/-23 package, will reach solder reflow temperatures faster than those with a greater mass. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 260°C. Avago’s diodes have been qualified to the timetemperature profile shown in Figure 21. This profile is representative of an IR reflow type of surface mount assembly process. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. tp Tp Critical Zone T L to Tp Ramp-up Temperature TL Ts Ts tL max min Ramp-down ts Preheat 25 t 25° C to Peak Time Figure 21. Surface Mount Assembly Profile. Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C) Reflow Parameter Lead-Free Assembly Average ramp-up rate (Liquidus Temperature (TS(max) to Peak) 3°C/ second max Preheat Temperature Min (TS(min)) 150°C Temperature Max (TS(max)) 200°C Time (min to max) (tS) 60-180 seconds Ts(max) to TL Ramp-up Rate Time maintained above: 3°C/second max Temperature (TL) 217°C Time (tL) 60-150 seconds Peak Temperature (TP) 260 +0/-5°C Time within 5 °C of actual Peak temperature (tP) 20-40 seconds Ramp-down Rate 6°C/second max Time 25 °C to Peak Temperature 8 minutes max Note 1: All temperatures refer to topside of the package, measured on the package body surface  Package Dimensions Outline SOT-323 (SC-70) Outline 23 (SOT-23) e1 e2 e1 XXX E XXX E E1 e e DIMENSIONS (mm) A SYMBOL A A1 B C D E1 e e1 e2 E L MIN. 0.79 0.000 0.30 0.08 2.73 1.15 0.89 1.78 0.45 2.10 0.45 MAX. 1.20 0.100 0.54 0.20 3.13 1.50 1.02 2.04 0.60 2.70 0.69 A A1 Notes: XXX-package marking Drawings are not to scale Package Characteristics Lead Material........................................................ Copper (SOT-323); Alloy 42 (SOT-23) Lead Finish............................................................................. Tin 100% (Lead-free option) Maximum Soldering Temperature................................................ 260°C for 5 seconds Minimum Lead Strength............................................................................... 2 pounds pull Typical Package Inductance...........................................................................................2 nH Typical Package Capacitance.................................................. 0.08 pF (opposite leads) Ordering Information Specify part number followed by option. For example:   HSMP - 382x -  XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.”  DIMENSIONS (mm) C D C D B Notes: XXX-package marking Drawings are not to scale L B L A1 E1 SYMBOL A A1 B C D E1 e e1 E L MIN. MAX. 0.80 1.00 0.00 0.10 0.15 0.40 0.08 0.25 1.80 2.25 1.10 1.40 0.65 typical 1.30 typical 1.80 2.40 0.26 0.46 Device Orientation For Outlines SOT-23/323 REEL END VIEW TOP VIEW 4 mm 8 mm CARRIER TAPE USER FEED DIRECTION ABC ABC ABC ABC Note: "AB" represents package marking code. "C" represents date code. COVER TAPE Tape Dimensions and Product Orientation For Outline SOT-23 P P2 D E P0 F W D1 t1 Ko 9° MAX B0 A0 DESCRIPTION 13.5° MAX 8° MAX SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 3.15 ± 0.10 2.77 ± 0.10 1.22 ± 0.10 4.00 ± 0.10 1.00 + 0.05 0.124 ± 0.004 0.109 ± 0.004 0.048 ± 0.004 0.157 ± 0.004 0.039 ± 0.002 PERFORATION DIAMETER PITCH POSITION D P0 E 1.50 + 0.10 4.00 ± 0.10 1.75 ± 0.10 0.059 + 0.004 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 +0.30 –0.10 0.229 ± 0.013 0.315 +0.012 –0.004 0.009 ± 0.0005 DISTANCE BETWEEN CENTERLINE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002  Tape Dimensions and Product Orientation For Outline SOT-323 P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) K0 An A0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.094 ± 0.004 0.094 ± 0.004 0.047 ± 0.004 0.157 ± 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 ± 0.30 0.254 ± 0.02 0.315 ± 0.012 0.0100 ± 0.0008 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 FOR SOT-323 (SC70-3 LEAD) An 8°C MAX FOR SOT-363 (SC70-6 LEAD) An B0 CAVITY ANGLE Tt (COVER TAPE THICKNESS) 10°C MAX For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-4026EN AV02-1395EN - June 2, 2009