PEX8114-BD13BI

ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book Version 3.2 September 2010 Website www.plxtech.com Technical Support www.plxtech.com/support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved – Version 3.2 September, 2010 Data Book PLX Technology, Inc. Copyright Information Copyright © 2006 – 2010 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG). All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Document Number: 8114-BC/BD-SIL-DB-P1-3.2 ii ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Revision History Revision History Version Date 1.0 June, 2006 Description of Changes Initial production release, Silicon Revision BA. August, 2006 Added notes regarding NT mode errata. Revised Register 17-12, offset 30h Expansion ROM Base Address. Updated miscellaneous electrical specifications. Added pull-up information for JTAG_TCK, and removed pull-up information from EE_PR# and all Hot Plug outputs. Moved thermal resistance information to Chapter 20 (from Chapter 19) and added heat sink-related information. Applied miscellaneous corrections throughout the data book. 2.0 December, 2006 Production release, Silicon Revision BB. Removed support for Silicon Revision BA and Non-Transparent mode. Applied miscellaneous corrections and enhancements throughout the data book. 3.0 January, 2007 Production release, Silicon Revision BC. 3.1 February, 2008 Production release, Silicon Revision BD. Data book now supports Silicon Revisions BC and BD. Rewrote Chapters 1, 3, 12, and 15, and applied many updates to Chapter 14. Reorganized Tables 2-10 and 2-11. Renamed Chapter 17 to “Thermal and Mechanical Specifications.” (As a result, Table 17-1 is now Table 17-2, and Table 17-2 is now Table 17-1.) Added Note d to Table 17-1. Added new “Power Characteristics” section to Chapter 16 (Section 16.4), and renumbered all subsequent sections accordingly. Changed minimum serial EEPROM size referenced in Section 9.2. Updated Tables 15-2 and 15-3. Changed minimum storage temperature. Applied miscellaneous corrections and enhancements throughout the data book. 3.2 September, 2010 1.1 Production update, Silicon Revisions BC and BD. Added solder mask opening information to Table 17-2. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved iii Preface PLX Technology, Inc. Preface The information contained in this document is subject to change without notice. This document is periodically updated as new information is made available. Audience This data book provides the functional details of the PLX ExpressLane PEX 8114-BC/BD PCI Expressto-PCI/PCI-X Bridge, for hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the following documents: • PLX Technology, Inc. 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel: 800 759-3735 (domestic only) or 408 774-9060, Fax: 408 774-2169, www.plxtech.com The PLX PEX 8114 Toolbox includes this data book, as well as other PEX 8114 documentation, including the Errata. • PCI Special Interest Group (PCI-SIG) 3855 SW 153rd Drive, Beaverton, OR 97006 USA Tel: 503 619-0569, Fax: 503 644-6708, www.pcisig.com – PCI Local Bus Specification, Revision 2.3 – PCI Local Bus Specification, Revision 3.0 – PCI Express Card Electromechanical Specification, Revision 1.0a – PCI Express Card Electromechanical Specification, Revision 1.1 – PCI to PCI Bridge Architecture Specification, Revision 1.1 – PCI Bus Power Management Interface Specification, Revision 1.2 – PCI Hot Plug Specification, Revision 1.1 – PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 – PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b – PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a – PCI Express Base Specification, Revision 1.0a – PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 – PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a • The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 445 Hoes Lane, Piscataway, NJ 08854-4141 USA Tel: 800 701-4333 (domestic only) or 732 981-0060, Fax: 732 981-9667, www.ieee.org – IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture – IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture – IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions – IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions iv ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Supplemental Documentation Abbreviations Supplemental Documentation Abbreviations In this data book, shortened titles are associated with the previously listed documents. The following table defines these abbreviations. Abbreviation Document PCI r3.0 PCI Local Bus Specification, Revision 3.0 PCI Express CEM r1.0a PCI Express Card Electromechanical Specification, Revision 1.0a PCI Express CEM r1.1 PCI Express Card Electromechanical Specification, Revision 1.1 PCI-to-PCI Bridge r1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Power Mgmt. r1.2 PCI Bus Power Management Interface Specification, Revision 1.2 PCI Hot Plug r1.1 PCI Hot Plug Specification, Revision 1.1 PCI Standard Hot Plug Controller and Subsystem r1.0 PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 PCI-X r1.0b PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b PCI-X r2.0a PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a PCI Express r1.0a PCI Express Base Specification, Revision 1.0a PCI Express-to-PCI/PCI-X Bridge r1.0 PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard 1149.6-2003 IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions Data Assignment Conventions Data Width PEX 8114 Convention 1 byte (8 bits) Byte 2 bytes (16 bits) Word 4 bytes (32 bits) DWORD/DWord ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved v Terms and Abbreviations PLX Technology, Inc. Terms and Abbreviations The following table defines common terms and abbreviations used in this document. Terms and abbreviations defined in the PCI Express r1.0a are not included in this table. Terms and Abbreviations vi Definition # Active-Low signal. ACK Acknowledge Control Packet. A control packet used by a destination to acknowledge data packet receipt. A signal that acknowledges signal receipt. ADB Allowable Disconnect Boundary. ADQ Allowable Disconnect Quantity. In the PCI Express interface, the ADQ is a buffer size, which is used to indicate memory requirements or reserves. BAR Base Address Register. Bridge, Transparent Provides connectivity from the Conventional PCI or PCI-X Bus system to the PCI Express hierarchy or subsystem. The bridge not only converts the physical bus to PCI Express point-to-point signaling, it also translates the PCI or PCI-X Bus protocol to PCI Express protocol. The Transparent bridge allows the Address domain on one side of the bridge to be mapped into the CPU system hierarchy on the primary side of the bridge. Cold Reset A “Fundamental Reset” following the application of power. Completer Device addressed by a Requester. Cpl Completion Transaction. CRC Cyclic Redundancy Check CSR Configuration Status Register; Control and Status Register; Command and Status Register. DL_Down Data Link Layer is down (a PCI Express link/port status). DLLP Data Link Layer Packet (originate at the Data Link Layer); allow Flow Control (FCx DLLPs) to acknowledge packets (ACK and NAK DLLPs); and Power Management (PMx DLLPs). DW, DWord Double-word. ECC Error Checking and Correction. EEPROM Electrically Erasable Programmable Read-Only Memory. Endpoint Device, other than the Root Complex and switches that are Requesters or Completers of PCI Express transactions. • Endpoints can be PCI Express endpoints or Conventional PCI endpoints. • Conventional PCI endpoints support I/O and Locked transaction semantics. PCI Express endpoints do not. Fundamental Reset The mechanism of setting or returning all registers and state machines to default/initial conditions, as defined in all PCI Express, PCI, PCI-X and Bridge specifications. This mechanism is implemented by way of the PEX_PERST# Input ball/signal. Host A Host computer provides services to computers that connect to it on a network. It is considered in charge over the remainder of devices connected on the bus. Hot Reset A reset propagated in-band across a link, using a Physical Layer mechanism (Training Sequence). ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Terms and Abbreviations Terms and Abbreviations Definition I CMOS Input. I/O CMOS Bidirectional Input/Output. INCH Ingress Credit Handler. ITCH Internal Credit Handler. Lane Differential signal pair in each direction. Layers PCI Express defines three layers: • Transaction Layer – Provides assembly and disassembly of TLPs, the major components of which are Header, Data Payload, and an optional Digest field. • Data Link Layer – Provides link management and data integrity, including error detection and correction. Defines the data control for PCI Express. • Physical Layer – Appears to the upper layers as PCI. Connects the lower protocols to the upper layers. Physical connection between two devices that consists of xN lanes. • A x1 link consists of one Transmit and one Receive signal, where each signal is a differential pair. This is one lane. There are four lines or signals in a x1 link. • A x4 link contains four lanes or four differential signal pairs for each direction, for a total of 16 lines or signals. A Differential Pair One Differential Pair in each direction = one Lane. Link This is a x1 Link. There are four signals. Four Differential Pairs in each direction = four Lanes. This is a x4 Link. There are 16 signals. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved vii Terms and Abbreviations PLX Technology, Inc. Terms and Abbreviations Definition LLIST Link List. LVDSRn Differential low-voltage, high-speed, LVDS negative Receiver Inputs. LVDSRp Differential low-voltage, high-speed, LVDS positive Receiver Inputs. LVDSTn Differential low-voltage, high-speed, LVDS negative Transmitter Outputs. LVDSTp Differential low-voltage, high-speed, LVDS positive Transmitter Outputs. MSI Message Signaled Interrupt. NAK Negative Acknowledge. Non-Posted Request Packet Packet transmitted by a Requester that has a Completion packet returned by the associated Completer. O CMOS Output. OD Open Drain Output. Packet Types There are three packet types: • TLP, Transaction Layer Packet • DLLP, Data Link Layer Packet • PLP, Physical Layer Packet PCI Peripheral Component Interconnect. A PCI Bus is a high-performance, 32- or 64-bit bus. It is designed to use with devices that contain high-bandwidth requirements; for example, the display subsystem. A PCI Bus is an I/O bus that can be dynamically configured. PCI PCI/PCI-X Compliant. PCI-X Peripheral Component Interconnect Extended. An extension to PCI, designed to address the need for the increased bandwidth of PCI devices. PEX PCI Express. Port Interface between a PCI Express component and the link, and consists of Transmitters and Receivers. • An ingress port receives a packet. • An egress port that transmits a packet. Posted Request Packet Packet transmitted by a Requester that does have a Completion packet returned by the associated Completer. PRBS Pseudo-Random Bit Sequence. PU Signal is internally pulled up. RC Root Complex. Device that connects the CPU and Memory subsystem to the PCI Express fabric, which supports one or more PCI Express ports. RCB Read Completion Boundary. Requester Device that originates a transaction or places a transaction sequence into the PCI Express fabric. RoHS Restrictions on the use of certain Hazardous Substances (RoHS) Directive. Rx Receiver. viii ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Terms and Abbreviations Terms and Abbreviations Definition Sticky bits Status bits that are reset to default on a Fundamental Reset. Sticky bits are not modified nor initialized by a reset, except a Fundamental Reset. Devices that consume AUX power preserve register values when AUX power consumption is enabled (by way of AUX power or PME Enable). HwInit, ROS, RWCS, and RWS CSR types. (Refer to Table 14-2 for CSR type definitions.) STRAP Input Strapping pads must be tied High to VDD33 or Low to VSS on the board. STS PCI-X Sustained Three-State Output, driven High for One CLK before Float. Switch Device that appears to software as two or more logical PCI-to-PCI bridges. TC Traffic Class. TLP Translation Layer Packet. TP Totem Pole. Transparent Bridge Provides connectivity from the Conventional PCI or PCI-X Bus system to the PCI Express hierarchy or subsystem. The bridge not only converts the physical bus to PCI Express point-to-point signaling, it also translates the PCI or PCI-X Bus protocol to PCI Express protocol. The Transparent bridge allows the Address domain on one side of the bridge to be mapped into the CPU system hierarchy on the primary side of the bridge. TS Three-State Bidirectional. Tx Transceiver. VC Virtual Channel. VC&T Virtual Channel and Type [P (Posted), NP (Non-Posted), and Cpl (Completion)]. Warm Reset “Fundamental Reset” without cycling the supplied power. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved ix Data Book Notations and Conventions PLX Technology, Inc. Data Book Notations and Conventions Notation / Convention x Description Blue text Indicates that the text is hyperlinked to its description elsewhere in the data book. Left-click the blue text to learn more about the hyperlinked information. This format is often used for register names, register bit and field names, register offsets, chapter and section titles, figures, and tables. PEX_XXXn[3:0] PEX_XXXp[3:0] When the signal name appears in all CAPS, with the primary port description listed first, field [3:0] indicates the number associated with the signal balls/pads assigned to a specific SerDes module/Lane. The lowercase “p = positive” or “n = negative” suffix indicates the differential pair of signals, which are always used together. # = Active-Low signals Unless specified otherwise, Active-Low signals are identified by a “#” appended to the term (for example, PEX_PERST#). Program/code samples Monospace font (program or code samples) is used to identify code samples or programming references. These code samples are case-sensitive, unless specified otherwise. command_done Interrupt format. Command/Status Register names. Parity Error Detected Register parameter [field] or control function. Upper Base Address[31:16] Specific Function in 32-bit register bounded by bits [31:16]. Number multipliers k = 1,000 (103) is generally used with frequency response. K = 1,024 (210) is used for memory size references. KB = 1,024 bytes. M = meg. = 1,000,000 when referring to frequency (decimal notation) = 1,048,576 when referring to Memory sizes (binary notation) 1Fh h = suffix which identifies hex values. Each prefix term is equivalent to a 4-bit binary value (nibble). Legal prefix terms are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. 1010b b = suffix which identifies binary notation (for example, 01b, 010b, 1010b, and so forth). Not used with single-digit values of 0 or 1. 0 through 9 Decimal numbers, or single binary numbers. byte Eight bits – abbreviated to “B” (for example, 4B = 4 bytes) LSB Least-Significant Byte. lsb Least-significant bit. MSB Most-Significant Byte. msb Most-significant bit. DWord DWord (32 bits) is the primary register size in these devices. Reserved Do not modify reserved bits and words. Unless specified otherwise, these bits read as 0 and must be written as 0. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PCI Express to PCI/PCI-X Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.1 Introduction to PEX 8114 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.3 Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 Forward/Reverse Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.1 Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.1 PCI Express Adapter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.2 PCI Express Motherboard to PCI-X Expansion Slot . . . . . . . . . . . . . . . . . . . . . 10 1.5.3 PCI-X Host Supporting a PCI Express Expansion Slot . . . . . . . . . . . . . . . . . . . 11 1.5.4 PCI-X Add-In Board Created from PCI Express Native Silicon . . . . . . . . . . . . . 12 1.5.5 PCI-X Extender Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 2 Signal Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Pull-Up Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 PCI/PCI-X Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 PCI Express Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Hot Plug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Strapping Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Serial EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Ball Assignments by Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 Ball Assignments by Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 3 15 16 17 18 23 24 25 26 27 28 29 31 33 Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.1 Introduction to PEX 8114 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 PCI/PCI-X Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Clocking of PCI and PCI-X Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2.1 Clocking PCI and PCI-X Modules with External Clock . . . . . . . . . . . . . . . . 3.1.2.2 Clocking PCI and PCI-X Modules with Internal Clock Generator . . . . . . . . 3.1.3 Clocking External PCI/PCI-X Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Determining PCI Bus and Internal Clock Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Bridge Mode and Clocking Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Determining Bus Mode Capability and Maximum Frequency . . . . . . . . . . . . . . 3.3 PCI Clock Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Clock Master – Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . 3.3.2 Clock Master – Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 35 35 36 36 36 36 37 37 38 39 39 41 xi Contents PLX Technology, Inc. 3.4 PCI Clock Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Clock Slave – Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Clock Slave – Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Timing Diagrams – Forward or Reverse Transparent Bridge Mode . . . . . . . . . 3.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Fundamental Reset (Power-On, Hard, Cold, Warm Reset) . . . . . . . . . . . . . . . 3.5.1.1 PEX_PERST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1.2 Fundamental Reset – Forward Transparent Bridge Mode . . . . . . . . . . . . . 3.5.1.3 Fundamental Reset – Reverse Transparent Bridge Mode . . . . . . . . . . . . . 3.5.2 Hot Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2.1 Hot Reset – Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . 3.5.2.2 Hot Reset – Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . 3.5.3 Secondary Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3.1 Secondary Bus Reset – Forward Transparent Bridge Mode . . . . . . . . . . . 3.5.3.2 Secondary Bus Reset – Reverse Transparent Bridge Mode . . . . . . . . . . . 3.6 Serial EEPROM Load Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 4 Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.1 4.2 4.3 Chapter 5 Internal Data Path Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Credits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency and Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Data Flow-Through Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 PCI Transaction Initial Latency and Cycle Recovery Time . . . . . . . . . . . . . . . . 4.3.3 PCI-X Transaction Initial Latency and Cycle Recovery Time . . . . . . . . . . . . . . 4.3.4 Arbitration Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.2 I/O Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.3 ISA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1.4 VGA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Memory-Mapped I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2.2 Memory-Mapped I/O Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . 5.2.3 Prefetchable Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.1 Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.2 Prefetchable Base and Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3.3 64-Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Base Address Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 62 62 62 64 65 66 66 67 68 68 69 71 72 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6.1 6.2 6.3 6.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 0 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1-to-Type 0 Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Type 1-to-Type 1 Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 PCI Express Enhanced Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . xii 57 57 58 58 58 59 59 Address Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 5.1 5.2 Chapter 6 43 43 45 46 48 49 49 50 51 52 52 53 54 54 54 55 73 75 75 76 76 77 78 78 79 79 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Contents 6.7 Configuration Retry Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Configuration Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Configuration Methods Intent and Variations . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 PCI Express Extended Configuration Method . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 PCI Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.4 BAR0/1 Device-Specific Register Memory-Mapped Configuration . . . . . . . . . . 6.8.5 Address and Data Pointer Configuration Method . . . . . . . . . . . . . . . . . . . . . . . 6.8.6 Configuration Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.6.1 Forward Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.6.2 Reverse Transparent Bridge Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7 80 80 80 81 81 82 82 82 83 83 83 84 Bridge Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.1 7.2 7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI-to-PCI Express Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.1 PCI-to-PCI Express Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 PCI-to-PCI Express – PCI Posted Write Requests . . . . . . . . . . . . . . . . . . . . . . 7.3.3 PCI-to-PCI Express – PCI Non-Posted Requests . . . . . . . . . . . . . . . . . . . . . . . 7.3.4 PCI-to-PCI Express – PCI Non-Posted Transactions until PCI Express Completion Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5 PCI-to-PCI Express – PCI Requests Do Not Contain Predetermined Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.5.1 Memory Read Requests to Non-Prefetchable Space . . . . . . . . . . . . . . . . 7.3.5.2 Memory Read Requests to Prefetchable Space . . . . . . . . . . . . . . . . . . . . 7.3.5.3 Memory Read Line or Memory Read Line Multiple . . . . . . . . . . . . . . . . . . 7.3.5.4 Credits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.6 PCI-to-PCI Express Disposition of Unused Prefetched Data . . . . . . . . . . . . . . 7.3.7 PCI-to-PCI Express Pending Transaction Count Limits . . . . . . . . . . . . . . . . . . 7.3.8 PCI-to-PCI Express – PCI Write Transaction with Discontiguous Byte Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.9 PCI-to-PCI Express – PCI Write Transactions Larger than Maximum Packet Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 PCI-X-to-PCI Express Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 PCI-X-to-PCI Express Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 PCI-X-to-PCI Express – PCI-X Posted Requests . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 PCI-X-to-PCI Express – PCI-X Non-Posted Requests . . . . . . . . . . . . . . . . . . . 7.4.4 PCI-X-to-PCI Express – PCI-X Read Requests Larger than Maximum Read Request Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.5 PCI-X-to-PCI Express – PCI-X Transfer Special Case . . . . . . . . . . . . . . . . . . . 7.4.6 PCI-X-to-PCI Express – PCI-X Transactions that Require Bridge to Take Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.7 PCI-X-to-PCI Express – PCI-X Writes with Discontiguous Byte Enables . . . . . 7.4.8 PCI-X-to-PCI Express – PCI-X Writes Larger than Maximum Packet Size . . . . 7.5 PCI Express-to-PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 PCI Express-to-PCI Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 PCI Express-to-PCI – PCI Express Posted Transactions . . . . . . . . . . . . . . . . . 7.5.3 PCI Express-to-PCI – PCI Express Non-Posted Transactions . . . . . . . . . . . . . 7.5.4 PCI Express-to-PCI – PCI Bus Retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.5 PCI Express-to-PCI Transaction Request Size . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.6 PCI Express-to-PCI Transaction Completion Size . . . . . . . . . . . . . . . . . . . . . . ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 87 87 88 88 88 89 89 90 90 90 91 91 91 92 92 92 93 93 93 94 95 95 95 96 96 97 97 97 98 98 99 99 xiii Contents PLX Technology, Inc. 7.6 PCI Express-to-PCI-X Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 PCI Express-to-PCI-X Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 PCI Express-to-PCI-X Non-Posted Transactions . . . . . . . . . . . . . . . . . . . . . . 7.6.2.1 Non-Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2.2 Non-Posted Writes and Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.2.3 Transaction Concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Transaction Transfer Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 PCI Endpoint Fails to Retry Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 PCI-X Endpoint Fails to Transmit Split Completion . . . . . . . . . . . . . . . . . . . . . 7.7.3 PCI-X Endpoint Allows Infinite Retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.4 PCI Express Endpoint Fails to Return Completion Data . . . . . . . . . . . . . . . . . Chapter 8 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 8.1 Forward Transparent Bridge Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.1 Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.2 Received ECRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.3 PCI/PCI-X Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.4 PCI/PCI-X Address/Attribute Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.5 PCI/PCI-X Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . 8.1.1.6 PCI/PCI-X Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 8.1.1.7 PCI-X Master Abort on Split Completion . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.8 PCI/PCI-X Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . 8.1.1.9 PCI/PCI-X Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 8.1.1.10 PCI-X Target Abort on Split Completion . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.11 Completer Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.12 Unexpected Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.13 Receive Non-Posted Request Unsupported . . . . . . . . . . . . . . . . . . . . . . 8.1.1.14 Link Training Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.15 Data Link Protocol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.16 Flow Control Protocol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.17 Receiver Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1.18 Malformed TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2.1 Received PCI/PCI-X Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2.2 Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . . . . . . 8.1.2.3 Completer Abort (CA) Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2.4 Split Completion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 Forward Transparent Bridge Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3.1 PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3.2 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 Forward Transparent Bridge SERR# Forwarding . . . . . . . . . . . . . . . . . . . . . . 8.2 Reverse Transparent Bridge Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Reverse Transparent Bridge Forwarding System Errors and System Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1.1 Root Port Error Forwarding Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1.2 Conventional PCI Type 1 Error Forwarding Control . . . . . . . . . . . . . . . . . 8.2.1.3 Bridge-Detected Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv 100 100 101 101 101 102 103 104 104 104 105 107 107 108 109 109 112 113 113 114 114 115 115 116 116 117 117 118 118 119 119 120 121 127 127 128 132 132 132 133 134 134 135 136 136 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Contents 8.2.2 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.1 Received Poisoned TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.2 Received ECRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.3 PCI/PCI-X Uncorrectable Data Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.4 PCI/PCI-X Address/Attribute Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.5 PCI/PCI-X Master Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . 8.2.2.6 PCI/PCI-X Master Abort on Non-Posted Transaction . . . . . . . . . . . . . . . 8.2.2.7 PCI-X Master Abort on Split Completion . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.8 PCI/PCI-X Target Abort on Posted Transaction . . . . . . . . . . . . . . . . . . . . 8.2.2.9 PCI/PCI-X Target Abort on Non-Posted Transaction . . . . . . . . . . . . . . . . 8.2.2.10 PCI-X Target Abort on Split Completion . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.11 Unexpected Completion Received . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.12 Received Request Unsupported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.13 Link Training Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.14 Data Link Protocol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.15 Flow Control Protocol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.16 Receiver Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.17 Malformed TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.1 Received PCI/PCI-X Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.2 Unsupported Request (UR) Completion Status . . . . . . . . . . . . . . . . . . . . 8.2.3.3 Completer Abort Completion Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.4 Split Completion Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Reverse Transparent Bridge Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4.1 PCI Express Completion Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4.2 PCI Delayed Transaction Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Reverse Transparent Bridge PCI Express Error Messages . . . . . . . . . . . . . . Chapter 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Configuration Data Download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 10.1 10.2 10.3 10.4 10.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Handler Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Events that Cause Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTx# Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Signaled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.1 MSI Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5.2 MSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.6 Remapping INTA# Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 11 157 158 165 165 166 172 172 173 174 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.1 9.2 Chapter 10 137 138 139 140 144 144 145 146 147 148 149 150 151 152 153 154 155 156 179 179 180 181 182 182 183 183 PCI/PCI-X Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 11.1 11.2 11.3 11.4 11.5 11.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbiter Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbiter Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Bus Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.1 Bus Parking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.2 Hidden Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6.3 Address Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 185 185 186 187 188 188 189 189 189 xv Contents Chapter 12 PLX Technology, Inc. Hot Plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 12.1 Hot Plug Purpose and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.1 Hot Plug Controller Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.2 Hot Plug Port External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1.3 Hot Plug Typical Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 PCI Express Capability Registers for Hot Plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 Hot Plug Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Hot Plug Insertion and Removal Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 Operator Actions for Hot Plug Insertion/Removal . . . . . . . . . . . . . . . . . . . . . 12.3.2 Hot Plug Insertion – Hardware and Software Process . . . . . . . . . . . . . . . . . 12.3.3 Hot Plug Removal – Hardware and Software Process . . . . . . . . . . . . . . . . . Chapter 13 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 13.1 13.2 Chapter 14 Power Management Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capability Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 General Power Management Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Forward Bridge-Specific Power Management Capability . . . . . . . . . . . . . . . 13.2.3 Reverse Transparent Bridge-Specific Power Management Capability . . . . . 13.2.4 Device Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.4.1 D0 Device PM State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.4.2 D3hot Device PM State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.4.3 D3cold Device PM State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.5 Link Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.6 PCI Express Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . 197 197 197 197 198 198 198 198 198 199 200 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Type 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Type 1 Configuration Space Header Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 Message Signaled Interrupt Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . 14.7 PCI-X Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.8 PCI Express Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.9 Device-Specific Indirect Configuration Mechanism Registers . . . . . . . . . . . . . . . 14.10 Device Serial Number Extended Capability Registers . . . . . . . . . . . . . . . . . . . . 14.11 Power Budget Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14.12 Virtual Channel Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . 14.13 Device-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.13.1 Device-Specific Registers – Error Checking and Debug . . . . . . . . . . . . . . . 14.13.2 Device-Specific Registers – Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . 14.13.3 Device-Specific Registers – Content-Addressable Memory Routing . . . . . 14.13.3.1 Device-Specific Registers – Bus Number CAM . . . . . . . . . . . . . . . . . . 14.13.3.2 Device-Specific Registers – I/O CAM . . . . . . . . . . . . . . . . . . . . . . . . . . 14.13.3.3 Device-Specific Registers – Address-Mapping CAM . . . . . . . . . . . . . . 14.13.3.4 Device-Specific Registers – Transaction Layer Ingress Control . . . . . 14.13.3.5 Device-Specific Register – I/O CAM Base and Limit Upper 16 Bits . . . 14.13.4 Device-Specific Registers – Base Address Shadow . . . . . . . . . . . . . . . . . . 14.13.5 Device-Specific Registers – Ingress Credit Handler . . . . . . . . . . . . . . . . . . 14.13.5.1 Ingress Credit Handler Threshold Virtual Channel Registers . . . . . . . . xvi 191 191 191 192 193 193 193 193 194 195 209 210 212 213 230 233 235 242 257 258 259 261 265 266 275 286 287 287 288 289 289 291 292 293 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Contents 14.13.6 Internal Credit Handler Virtual Channel and Type Threshold Registers . . . 14.13.6.1 ITCH VC&T Threshold Registers – PCI Express Interface Device-Specific . . . . . . . . . . . . . . . . . . . . . . . . . . 14.13.6.2 ITCH VC&T Threshold Registers – PCI-X Interface Device-Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.14 PCI-X Device-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.15 Root Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.16 PCI-X-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.17 PCI Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.18 Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 15 Physical Layer Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2 Loopback Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2.1 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2.2 Analog Loopback Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2.3 Digital Loopback Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2.4 Analog Loopback Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2.5 Digital Loopback Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Pseudo-Random and Bit-Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 IEEE 1149.1 and 1149.6 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4 JTAG Reset Input TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Logic Interface Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5.1 SerDes/Lane Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6 SerDes Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix C 329 329 329 330 331 332 334 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 A.1 Appendix B 319 319 320 320 321 322 323 323 324 325 325 326 327 327 Thermal and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 17.1 17.2 17.3 Appendix A 296 298 301 303 306 307 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 16.1 16.2 16.3 16.4 16.5 Chapter 17 294 Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 15.1 Chapter 16 294 Serial EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Sample C Code Implementation of CRC Generator . . . . . . . . . . . . . . . . . . . . . 347 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 C.1 C.2 C.3 Product Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 United States and International Representatives and Distributors . . . . . . . . . . . . . . 350 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved xvii Contents PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. xviii ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Registers Type 1 Configuration Space Header Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14-1. 00h Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 14-2. 04h PCI Command/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 14-3. 08h Class Code and PCI Revision ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 14-4. 0Ch Miscellaneous Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 14-5. 10h Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 14-6. 14h Base Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 14-7. 18h Bus Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 14-8. 1Ch Secondary Status, I/O Limit, and I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 14-9. 20h Memory Base and Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 14-10. 24h Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 14-11. 28h Prefetchable Memory Base Upper 32 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14-12. 2Ch Prefetchable Memory Limit Upper 32 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14-13. 30h I/O Base and Limit Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 14-14. 34h New Capability Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 14-15. 38h Expansion ROM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 14-16. 3Ch Bridge Control and Interrupt Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 Power Management Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14-17. 40h Power Management Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14-18. 44h Power Management Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 Message Signaled Interrupt Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14-19. 14-20. 14-21. 14-22. 48h 4Ch 50h 54h Message Signaled Interrupt Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 MSI Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 MSI Upper Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 MSI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 PCI-X Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 14-23. 14-24. 14-25. 14-26. 58h 5Ch 60h 64h PCI-X Capability, Secondary Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 PCI-X Bridge Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 Upstream Split Transaction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 Downstream Split Transaction Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 PCI Express Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 14-27. 14-28. 14-29. 14-30. 14-31. 14-32. 14-33. 68h 6Ch 70h 74h 78h 7Ch 80h PCI Express Capability List and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 Device Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 Device Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 Link Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 Link Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 Slot Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 Slot Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 Device-Specific Indirect Configuration Mechanism Registers . . . . . . . . . . . . . . . . . . . . . . . . . 257 14-34. F8h Configuration Address Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 14-35. FCh Configuration Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 Device Serial Number Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 14-36. 100h Device Serial Number Extended Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14-37. 104h Serial Number (Lower DW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 14-38. 108h Serial Number (Higher DW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved xix Registers PLX Technology, Inc. Power Budget Extended Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14-39. 14-40. 14-41. 14-42. 138h 13Ch 140h 144h Power Budget Extended Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Budget Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Budget Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 259 260 260 Virtual Channel Extended Capability Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 14-43. 14-44. 14-45. 14-46. 14-47. 14-48. 14-49. 148h 14Ch 150h 154h 158h 15Ch 160h Virtual Channel Extended Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Capability 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Capability 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC0 Resource Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC0 Resource Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC0 Resource Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 262 262 263 263 264 264 Device-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Device-Specific Registers – Error Checking and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 14-50. 14-51. 14-52. 14-53. 14-54. 14-55. 14-56. 14-57. 14-58. 1C8h ECC Check Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1CCh Device-Specific Error 32-Bit Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1D0h Device-Specific Error 32-Bit Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1E0h Power Management Hot Plug User Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1E4h Egress Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1E8h Bad TLP Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ECh Bad DLLP Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1F0h TLP Payload Length Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1F8h ACK Transmission Latency Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 268 270 272 273 274 274 274 274 Device-Specific Registers – Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14-59. 14-60. 14-61. 14-62. 14-63. 14-64. 14-65. 14-66. 14-67. 14-68. 14-69. 14-70. 14-71. 14-72. 14-73. 210h 214h 218h 21Ch 220h 224h 228h 230h 234h 238h 248h 24Ch 254h 260h 264h Phy User Test Pattern 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phy User Test Pattern 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phy User Test Pattern 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phy User Test Pattern 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Layer Command and Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Layer Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Physical Layer Port Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SKIP Ordered-Set Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes[0-3] Quad Diagnostics Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes Nominal Drive Current Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes Drive Current Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SerDes Drive Equalization Level Select 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 276 276 276 277 277 278 280 280 281 281 281 282 283 285 Device-Specific Registers – Content-Addressable Memory Routing . . . . . . . . . . . . . . . . . . . . 286 Device-Specific Registers – Bus Number CAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 14-74. 2E8h Bus Number CAM 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Device-Specific Registers – I/O CAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 14-75. 318h I/O CAM_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Device-Specific Registers – Address-Mapping CAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 14-76. 14-77. 14-78. 14-79. xx 3C8h 3CCh 3D0h 3D4h AMCAM_8 Memory Limit and Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMCAM_8 Prefetchable Memory Limit and Base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . AMCAM_8 Prefetchable Memory Base[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMCAM_8 Prefetchable Memory Limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 288 288 288 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Registers Device-Specific Registers – Transaction Layer Ingress Control . . . . . . . . . . . . . . . . . . . . . . . . 289 14-80. 660h TIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 14-81. 668h TIC Port Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 Device-Specific Register – I/O CAM Base and Limit Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . 289 14-82. 6A0h I/OCAM_8 Base and Limit Upper 16 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 Device-Specific Registers – Base Address Shadow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 14-83. 700h BAR0_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 14-84. 704h BAR1_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 Device-Specific Registers – Ingress Credit Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14-85. 9F4h INCH FC Update Pending Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 14-86. 9FCh INCH Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 Ingress Credit Handler Threshold Virtual Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14-87. A00h INCH Threshold VC0 Posted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 14-88. A04h INCH Threshold VC0 Non-Posted. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 14-89. A08h INCH Threshold VC0 Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 Internal Credit Handler Virtual Channel and Type Threshold Registers . . . . . . . . . . . . . . . . . . 294 ITCH VC&T Threshold Registers – PCI Express Interface Device-Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 14-90. C00h PCI Express Interface ITCH VC&T Threshold_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 14-91. C04h PCI Express Interface ITCH VC&T Threshold_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 ITCH VC&T Threshold Registers – PCI-X Interface Device-Specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 14-92. F70h PCI-X Interface ITCH VC&T Threshold_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 14-93. F74h PCI-X Interface ITCH VC&T Threshold_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 PCI-X Device-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 14-94. F80h PCI-X Interface Device-Specific Error 32-Bit Error Status. . . . . . . . . . . . . . . . . . . . . . . .299 14-95. F84h PCI-X Interface Device-Specific Error 32-Bit Error Mask . . . . . . . . . . . . . . . . . . . . . . . .300 14-96. F88h PCI-X Interface Completion Buffer Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 Root Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 14-97. F8Ch Root Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 14-98. F90h Root Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 14-99. F94h Root Error Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 14-100. F98h Root Error Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 14-101. F9Ch Error Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 PCI-X-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 14-102. FA0h PCI Clock Enable, Strong Ordering, Read Cycle Value . . . . . . . . . . . . . . . . . . . . . . . .304 14-103. FA4h Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 PCI Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14-104. FA8h Arbiter 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 14-105. FACh Arbiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 14-106. FB0h Arbiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved xxi Registers PLX Technology, Inc. Advanced Error Reporting Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 14-107. 14-108. 14-109. 14-110. 14-111. 14-112. 14-113. 14-114. 14-115. 14-116. 14-117. 14-118. 14-119. 14-120. 14-121. 14-122. xxii FB4h PCI Express Enhanced Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FB8h Uncorrectable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FBCh Uncorrectable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FC0h Uncorrectable Error Severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FC4h Correctable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FC8h Correctable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FCCh Advanced Error Capabilities and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD0h Header Log_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD4h Header Log_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FD8h Header Log_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FDCh Header Log_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FE0h Secondary Uncorrectable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FE4h Secondary Uncorrectable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FE8h Secondary Uncorrectable Error Severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FECh Secondary Uncorrectable Error Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FF0h – FFCh Secondary Header Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 308 309 310 311 311 312 312 312 312 312 313 314 316 317 317 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 1 1.1 Introduction Features The PLX ExpressLaneTM PEX 8114 PCI Express-to-PCI/PCI-X Bridge supports the following features: • Forward and Reverse Transparent Bridge modes • PCI Express – Four full-duplex PCI Express Lanes – Four fully integrated SerDes – x1, x2, or x4 port lane width, established during link auto-negotiation – 2.5 Gbps bandwidth per lane – Lane reversal – Lane polarity inversion – Link Power Management states – L0, L0s, L1, L2/L3 Ready, and L3 – Data payload size per packet – 256 bytes (maximum) – One Virtual Channel (VC0) – Eight Traffic Classes (TC[7:0]) – Read Completion supported for all eight Traffic Classes – TLP Digest – End-to-end CRC checking – Data poisoning – Baseline and Advanced Error Reporting capability – ECC checking on destination packet RAM – Oversubscribe and Flood modes • PCI/PCI-X – PCI Bus Clock Master and Slave – Clock outputs for up to four external PCI/PCI-X devices – Conventional PCI Bus speeds – 25, 33, 50, and 66 MHz – PCI-X Bus speeds – 50, 66, 100, and 133 MHz – Internal arbiter (four REQ/GNT external pairs) that can be enabled or disabled – External arbitration accepted – Message Signaled Interrupts (MSI) – Dual Address Cycles (DAC) – 64-bit addressing as Master and Slave – 64-bit data width – Maximum 4-KB Master Writes and Reads on PCI-X Bus – Eight outstanding Split transactions on primary side, and eight outstanding Split transactions on secondary side – Address stepping and IDSEL stepping – Prefetchable Memory Address range – Transaction Ordering and Deadlock Avoidance rules ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 1 Introduction PLX Technology, Inc. • Package – 17 x 17 mm2, 256-ball Plastic Ball Grid Array (PBGA) package – Typical power – 1.67W – JTAG • SPI/serial EEPROM for initialization • Compliant to the following specifications: – PCI Local Bus Specification, Revision 2.3 (PCI r2.3) – PCI Local Bus Specification, Revision 3.0 (PCI r3.0) – PCI Express Card Electromechanical Specification, Revision 1.0a (PCI Express CEM r1.0a) – PCI Express Card Electromechanical Specification, Revision 1.1 (PCI Express CEM r1.1) – PCI to PCI Bridge Architecture Specification, Revision 1.1 (PCI-to-PCI Bridge r1.1) – PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2) – PCI Hot Plug Specification, Revision 1.1 (PCI HotPlug 1.1) – PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0 (Hot Plug r1.0) – PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b (PCI-X r1.0b) – PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a (PCI-X r2.0a) – PCI Express Base Specification, Revision 1.0a (PCI Express Base 1.0a) – PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 (PCI Express-to-PCI/PCI-X Bridge r1.0) – IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 (IEEE Standard 1149.1-1990) – IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Standard 1149.1-1993) – IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions (IEEE Standard 1149.1-1990) – IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions (IEEE Standard 1149.6-2003) 2 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 1.2 PCI Express to PCI/PCI-X Bridge PCI Express to PCI/PCI-X Bridge The PEX 8114 is a high-performance bridge that enables designers to migrate Conventional PCI and PCI-X Bus interfaces to the new advanced serial PCI Express protocol with an economical single-chip solution. This simple two-port device is equipped with a standard PCI Express port that scales to x1, x2, or x4 lanes in width, giving an effective bit rate scaling from 2.5 to 10 Gbps. Using LVDS PCI Express signaling, this bandwidth is achieved with the lowest possible ball count (16 balls for four lanes). The single parallel bus segment supports either Conventional PCI or the advanced PCI-X protocol. Using a 64-bit wide parallel data path at a clock frequency of 133 MHz, PCI-X can achieve a maximum bandwidth of 8 Gbps. In order to optimize throughput and traffic flow between the two bus protocols, the PEX 8114 supports internal queues with Flow Control (FC) features. The PEX 8114 is available in a standard 256-ball Plastic Ball Grid Array (PBGA) package. The small footprint and low-power consumption make the PEX 8114 an ideal bridge for use on adapter boards, daughter boards, add-on modules, and backplane designs, as well as on larger planar boards. Figure 1-1. PCI/PCI-X Bus Segment PEX 8114 – Two-Port Device PEX 8114 8104 PCI Express Link ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 3 Introduction 1.2.1 PLX Technology, Inc. Introduction to PEX 8114 Operation The PEX 8114 is a PCI Express-to-PCI-X bridge that provides a functional link from a PCI or PCI-X Bus segment to a PCI Express port. (The PCI Express port functions as a single port, and may not be bifurcated into multiple ports.) The port can be configured as x1, x2, or x4 lanes, each operating at 2.5 Gbps. The SerDes and all associated circuitry are integrated into each lane, thus the PEX 8114 requires no external interface components. The PCI Express port conforms to the PCI Express r1.0a. There are several Data Transfer modes that the PEX 8114 supports as it transfers data between PCI or PCI-X and PCI Express. The PEX 8114 can operate as a Forward Transparent or Reverse Transparent bridge (configured by way of ball strap). • Forward Transparent bridge - the Host resides on the PCI Express side of the bridge, and Configuration accesses originate in the PCI Express Root Complex • Reverse Transparent bridge - the Host resides on the PCI/PCI-X side of the bridge and Configuration accesses originate on the PCI/PCI-X Bus • In both Forward and Reverse modes, the PEX 8114 automatically converts and/or forwards Configuration accesses to downstream devices: – If a Type 1 Configuration access is received, and if its destination is a device residing on secondary bus, the PEX 8114 converts the Type 1 Configuration access to a Type 0 Configuration access and delivers it to the target device – If a Type 1 Configuration access targets a device on a subordinate bus beyond the PEX 8114 secondary bus, the Type 1 Configuration access is passed along unchanged Figure 1-2 provides a PEX 8114 top-level block diagram. Figure 1-2. PEX 8114 Top-Level Block Diagram Hot Plug (PCI Express Client only) Serial EEPROM Power Management PCI 4-Input Arbiter PCI or PCI-X Bus Segment PCI/PCI-X Bus 25, 33, 50, 66, 100, 133 MHz PCI/PCI-X Module PCI Express Module x1, x2, x4 PCI Express Port Multiple Lanes PEX 8114 4 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 1.3 Detailed Block Diagram Detailed Block Diagram Figure 1-3 illustrates PEX 8114 implementation, with the modules at the data transfer core. Other modules, such as the PCI-X Arbiter and Power Management, are not included in Figure 1-3. Figure 1-3. PEX 8114 Top-Level Detailed Block Diagram PCI/PCI-X Module Either Conventional PCI or a PCI-X Bus Segment Interface Interface PCI/PCI-X Bus Segment IS Crossing Source Source IS Crossing TLCi Crossbar DLL PHY Port TLCe TLCe DE Crossing Destination Destination DE Crossing PCI/PCI-X ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved PCI Express 5 Introduction 1.3.1 PLX Technology, Inc. Transaction Layer The Transaction Layer (TL) is responsible for receiving commands and data from the PEX 8114 PCI/ PCI-X section and creating a PCI Express Transaction Layer Packet (TLP). This layer creates a header that includes transaction type, address, Traffic Class and Virtual Channel numbers, interrupts, power management commands, and so forth, and prepends it to the TLP data payload (if any). The TLP to be transmitted on the PCI Express port is then delivered to the Data Link Layer. The receive section of the Transaction Layer takes the TLP delivered by the Data Link Layer, strips off the Header information, and delivers the commands and data to the PCI/PCI-X section of the PEX 8114 as PCI or PCI-X compatible information. Therefore, software written for PCI or PCI-X will run without modification on a PCI Express system. This is significant because it allows vendors to leverage their existing, proven PCI code to achieve not only a faster time to market, but also provide a more stable and mature platform. 1.3.2 Data Link Layer The Data Link Layer (DLL) is responsible for management of the link, including link data integrity (error detection and correction). This layer calculates and appends a Cyclic Redundancy Check (CRC) and Sequence Number to each transmitted Transaction Layer Packet (TLP). The receiver Data Link Layer checks every TLP received for errors, and will signal the transmitter to resend a TLP if an error is detected. 1.3.3 Physical Layer The Physical Layer (PHY) is responsible for the function and operation of each lane. The transmit section performs multiple functions in converting packets received from the Data Link Layer to the analog signals transmitted on the lanes. Each lane consists of two LVDS pairs of wires, with each pair simultaneously operating at 2.5 Gbps in each direction. When combined, each lane provides 2.5 Gbps full-duplex communication, with no transmission collisions. The receive section converts the analog signals received on the lanes back into packets, which are then delivered to the Data Link Layer. 6 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 1.4 Forward/Reverse Operating Modes Forward/Reverse Operating Modes One of the many characteristics of the PEX 8114 that offer the user great design flexibility is the ability to operate as either a Forward or Reverse bridge. Examples of each mode of operation are provided in the following sections. 1.4.1 Forward Transparent Bridge Mode In Forward Transparent Bridge mode, Configuration cycles originate from the Host (via the Root Complex) on the PCI Express fabric, and are delivered to the PCI/PCI-X Bus segment, by way of the PEX 8114. As shown in Figure 1-4, Forward mode allows the use of conventional PCI/PCI-X boards and components in a PCI Express system. Figure 1-4. PEX 8114 as a Forward Bridge PCI/PCI-X Configuration TLP Configuration HOST PEX 8114 PCI/PCI-X Device 0 PCI/PCI-X Device 1 O O O PCI Express PCI/PCI-X Bus Segment SWITCH PCI/PCI-X Device N ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved PCI Express Device PCI Express Device 7 Introduction 1.4.2 PLX Technology, Inc. Reverse Transparent Bridge Mode In Reverse Transparent Bridge mode, Configuration cycles originate from the Host on the PCI/PCI-X bus, and are delivered to the PCI Express fabric, by way of the PEX 8114. Figure 1-5 shows how the PEX 8114 allows PCI Express boards and components to be used in a Conventional PCI/PCI-X system. Figure 1-5. PEX 8114 as a Reverse Bridge PCI/PCI-X Configuration TLP Configuration PCI Express Device PEX 8114 HOST PCI Express PCI/PCI-X Device 1 PCI/PCI-X SWITCH PCI Express Device O O O PCI Express Device PCI/PCI-X Device N 8 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 1.5 Applications Applications The PEX 8114 is a feature-rich bridge offering the flexibility needed for a wide variety of applications, such as the following: • PCI Express Adapter Board • PCI Express Motherboard to PCI-X Expansion Slot • PCI-X Host Supporting a PCI Express Expansion Slot • PCI-X Add-In Board Created from PCI Express Native Silicon • PCI-X Extender Board 1.5.1 PCI Express Adapter Board Devices with a native PCI or PCI-X interface, such as network controllers, storage controllers, or ASICs, have been in the marketplace for many years. If a designer needs to convert a PCI/PCI-X design to a PCI Express adapter board, yet wants to continue to use the existing devices, the PEX 8114 offers a single-chip solution. This application is illustrated in Figure 1-6, and the PEX 8114 is configured as a Forward Transparent bridge. Figure 1-6. PCI Express Board Created from PCI/PCI-X Native Silicon Forward Transparent PCI Express Port PCI Express Adapter Board PCI-X Bus PEX 8114 PCI or PCI-X Native Design PCI Express Connector ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 9 Introduction 1.5.2 PLX Technology, Inc. PCI Express Motherboard to PCI-X Expansion Slot In a PCI Express Motherboard to PCI-X Expansion Slot application, the PEX 8114 is used on the motherboard to support standard PCI-X add-in board slots. It is similar to the PCI Express Adapter Board example, because it allows a PCI Express system to interface with conventional PCI or PCI-X silicon. The configuration is illustrated in Figure 1-7, wherein the PEX 8114 is operating as a Forward Transparent bridge. An entire PCI-X Bus segment with standard PCI-X add-in boards can be supported in this mode. The PEX 8114’s simple design and small footprint make it an ideal bridge solution for the motherboard, providing for PCI r3.0 or PCI-X r1.0b slot connectivity or interface to native PCI or PCI-X silicon I/O components on the motherboard. Figure 1-7. PEX 8114 on Motherboard Provides PCI/PCI-X Slots Motherboard HOST CPU Root Complex (PCI Express Native) PCI Express Ports PCI Express Native Component PCI Express Link Forward Transparent PCI or PCI-X PCI Express Link (x1, x2, x4) 10 P-BRIDGE PEX 8114 P-Bridge Add-in Board Slots ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 1.5.3 PCI-X Host Supporting a PCI Express Expansion Slot PCI-X Host Supporting a PCI Express Expansion Slot In an application where a PCI-X Host must support a PCI Express expansion slot, the PEX 8114 is used on a PCI-X motherboard to create a PCI Express interface. The configuration is illustrated in Figure 1-8, wherein the PEX 8114 is operating as a Reverse Transparent bridge. Figure 1-8. PCI-X Host Using PEX 8114 to Create PCI Express Board Slot Reverse Transparent PCI/PCI-X Host PCI-X Bus PEX 8114 PCI-X Host Board or Motherboard PCI Express Link Board Slot ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 11 Introduction 1.5.4 PLX Technology, Inc. PCI-X Add-In Board Created from PCI Express Native Silicon If an add-in board contains a device with a native PCI Express interface, yet the board must plug into a PCI-X slot, the PEX 8114 can be used as a Reverse Transparent bridge. This configuration is illustrated in Figure 1-9. Figure 1-9. PCI-X Adapter Board Created Using PEX 8114 and PCI Express Native Silicon Reverse Transparent PCI-X Bus 12 PEX 8114 PCI Express Link PCI Express Native Silicon ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 1.5.5 PCI-X Extender Board PCI-X Extender Board A PCI-X Extender Board application uses the PEX 8114 to create a bridge board, enabling PCI or PCI-X Bus expansion over standardized PCI Express cabling. The configuration is illustrated in Figure 1-10, wherein the PEX 8114 is operating as a Reverse Transparent bridge. Figure 1-10. PCI-X Adapter Board Acting as Bridge Board for Bus Expansion Reverse Transparent PCI Express Cable Connector PCI-X Bus PEX 8114 PCI Express Link ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 13 Introduction PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 14 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 2 2.1 Signal Ball Description Introduction This chapter provides descriptions of the 256 PEX 8114 signal balls. The signals are divided into the following groups: • PCI/PCI-X Bus Interface Signals • PCI Express Interface Signals • Hot Plug Signals • Strapping Signals • JTAG Interface Signals • Serial EEPROM Interface Signals • Power and Ground Signals The signal name, type, location, and a brief description are provided for each signal ball. Lists of signals, by location and signal name, and a map of the PEX 8114’s physical layout, are also provided. Note: If there is more than one ball per signal name, the ball numbers are ordered, in sequence, to follow Signal Name sequencing [n to 0]. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 15 Signal Ball Description 2.2 PLX Technology, Inc. Abbreviations The following abbreviations are used in the signal tables provided in this chapter. Table 2-1. Ball Assignment Abbreviations Abbreviation # Description Active-Low signal APWR 1.0V Power (VDD10A) balls for SerDes Analog circuits CPWR 1.0V Power (VDD10) balls for low-voltage Core circuits DPWR 1.0V Power (VDD10S) balls for SerDes Digital circuits GND I I/O Ground CMOS Input CMOS Bidirectional Input/Output I/OPWR 3.3V Power (VDD33) balls for Input and Output interfaces LVDSRn Differential low-voltage, high-speed, LVDS negative Receiver Inputs LVDSRp Differential low-voltage, high-speed, LVDS positive Receiver Inputs LVDSTn Differential low-voltage, high-speed, LVDS negative Transmitter Outputs LVDSTp Differential low-voltage, high-speed, LVDS positive Transmitter Outputs O CMOS Output OD Open Drain Output PCI PCI/PCI-X Compliant PLLPWR PU 3.3V Power (VDD33A) balls for PLL circuits Signal is internally pulled up STRAP Input Strapping balls must be tied to High to VDD33 or Low to VSS on the board STS PCI/PCI-X Sustained Three-State Output, driven High for one CLK before Float TP Totem Pole TS Three-State Bidirectional Note: Depending upon the strapping configuration, certain balls change type. This is indicated in the Type column and descriptive field for the associated balls. 16 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.2.1 Pull-Up Resistors Pull-Up Resistors The balls defined in Table 2-2 have weak internal pull-up resistor values. Therefore, it is strongly advised that an external pull-up resistor to VDD33 (3KΩ to 10KΩ is recommended) be used on those signal balls when implemented in a design. For the remaining balls listed in this section, depending upon the application, certain balls are driven, pulled or tied, High or Low. When the PCI_PME# ball is not used, it requires an external pull-up resistor. When the Internal PCI Arbiter is not used (disabled), the PCI_REQ[3:1]# inputs require external pull-up resistors. If the internal PCI Arbiter is used (enabled), the PCI_REQ[3:0]# balls must be driven, pulled, or tied to a known state. Because the PCI_GNT[3:0]# outputs are driven, regardless of whether the PCI Arbiter is enabled, they do not require external pull-up resistors, and can be connected or remain unconnected (floating). For information on Hot Plug systems, refer to the PCI Express-to-PCI/PCI-X Bridge r1.0 for ball connection and usage. For non-Hot Plug systems, the Hot Plug Input balls defined in Table 2-5 can remain unconnected, because each has its own internal pull-up resistor. Serial EEPROM interface balls EE_CS#, EE_DI, and EE_SK are outputs that are driven by the PEX 8114, and can be connected or remain unconnected (floating). Serial EEPROM interface balls, EE_DO is an input with an internal pull-up resistor. Drive, pull, or tie this input to a known state. For designs that do not implement JTAG, ground the JTAG_TRST# ball and drive, pull, or tie the JTAG_TCK input to a known value. JTAG_TDI, JTAG_TDO, and JTAG_TMS can remain unconnected. Table 2-2. Balls with Internal Pull-Up Resistors Ball Name EE_DO JTAG_TCK HP_BUTTON# JTAG_TDI HP_MRL# JTAG_TMS HP_PRSNT# JTAG_TRST# HP_PWRFLT# ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 17 Signal Ball Description 2.3 PLX Technology, Inc. PCI/PCI-X Bus Interface Signals The PCI balls defined in Table 2-3 do not contain internal resistors and are generic primary and secondary PCI/PCI-X interface balls. When producing motherboards, system slot boards, adapter boards, backplanes, and so forth, the termination of these balls must follow the guidelines detailed in the PCI r3.0 and PCI-X r1.0b. The following guidelines are not exhaustive; therefore, read them in conjunction with the appropriate PCI r3.0 and PCI-X r1.0b sections. PCI Control signals require a pull-up resistor on the motherboard to ensure that these signals are at valid values when a PCI Bus agent is not driving the bus. These Control signals include PCI_ACK64#, PCI_DEVSEL#, PCI_FRAME#, PCI_INT[D:A]#, PCI_IRDY#, PCI_PERR#, PCI_REQ64#, PCI_SERR#, PCI_STOP#, and PCI_TRDY#. The 32-bit point-to-point and shared bus signals do not require pull-up resistors, because bus parking ensures that these signals remain stable. The other 64-bit signals – PCI_AD[63:32], PCI_C/BE[7:4]#, and PCI_PAR64 – also require pull-up resistors, because these signals are not driven during 32-bit transactions. The PCI_INT[D:A]# balls require pull-up resistors, regardless of whether they are used. In Forward Transparent Bridge mode, PCI_IDSEL is not used and requires a pull-up resistor. Depending upon the application, PCI_M66EN can also require a pull-up resistor. The value of these pull-up resistors depends upon the bus loading. The PCI r3.0 provides formulas for calculating the resistor values. When making adapter board devices where the PEX 8114 port is wired to the PCI connector, pull-up resistors are not required because they are pre-installed on the motherboard. Based upon the above, in an embedded design, pull-up resistors can be required for PCI Control signals on the bus. The PEX 8114 includes 108 PCI/PCI-X signals, which are defined in Table 2-3. The categories included in the Type columns of certain of these signals are from the PCI Express-to-PCI/PCI-X Bridge r1.0, Tables 6-3 and 6-4. By convention, multiple balls are listed in high-to-low order (that is, PCI_AD63, PCI_AD62, … PCI_AD0). 18 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Table 2-3. PCI/PCI-X Bus Interface Signals PCI/PCI-X Bus Interface Signals (108 Balls) Symbol PCI_ACK64# PCI_AD[63:0] Type Location I/O STS PCI A13 I/O TS PCI A15, C15, A16, D14, B16, D15, C16, E13, D16, E14, E15, F13, E16, F14, F16, G13, G16, G14, H15, H13, H16, H14, J15, J13, J16, J14, K15, K13, K16, K14, L16, L14, F1, F3, E1, F4, D1, E3, D2, D3, B1, C2, A1, C3, A2, D4, B3, C4, C7, A7, D8, A8, C8, A9, D9, B10, A10, C10, B11, D11, A11, C11, A12, C12 PCI_C/BE[7:0]# I/O TS PCI PCI_CLK I PCI PCI_CLKO[3:0] O PCI Description 64-Bit Transfer Acknowledge Asserted by the PCI Slave in response to PCI_REQ64#, to acknowledge a 64-bit Data transfer. 0 = Acknowledges a 64-bit transfer 1 = No acknowledge C13, A14, D13, B14, C1, A3, B7, D10 Address and Data (64 Balls) PCI Multiplexed Address/Data Bus. Bus Command and Byte Enables (8 Balls) During the PCI and/or PCI-X Address phase, PCI_C/BE[3:0]# provide the Command type. During the Data phase of PCI and/or PCI-X Memory Write transactions, PCI_C/BE[7:0]# provide Byte Enables. During the PCI-X Attribute phase, PCI_C/BE[7:0]# provide a portion of the attribute information. J1 PCI/PCI-X Bus Clock Input Clock reference when STRAP_CLK_MST=0. Not the clock reference when STRAP_CLK_MST=1. (Refer to Chapter 3, “Clock and Reset,” for further details.) L1, L2, K1, K3 Clock Outputs (4 Balls) PCI/PCI-X Bus clocks for up to four devices. Derived from PEX_REFCLKn/p. (Refer to Chapter 3, “Clock and Reset,” for further details.) PCI_CLKO_DLY_FBK O PCI N3 PCI Clock Delayed Feedback PCI/PCI-X clock intended to be fed back to the PEX 8114 PCI_CLK input ball when STRAP_CLK_MST and STRAP_EXT_CLK_SEL are High. The trace length provides a time phase delay on the PCI clock that drives the internal PCI circuitry, thereby aligning the internal PCI_CLK rising edge with the clock edges of other PCI devices on the PCI Bus that can be sufficiently separated physically, such that Clock-phase alignment becomes necessary. PCI_DEVSEL# I/O STS PCI A4 Device Select When actively driven, indicates the driving device decoded its address as the Target of the current access. PCI_FRAME# I/O STS PCI D5 Frame Driven by the transaction Initiator to indicate an access start and duration. While PCI_FRAME# is asserted, Data transfers continue. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 19 Signal Ball Description Table 2-3. PLX Technology, Inc. PCI/PCI-X Bus Interface Signals (108 Balls) (Cont.) Symbol Type PCI_GNT# or PCI_GNT0# I/O TS PCI PCI_GNT[3:1]# O TP PCI Location Description G3 Grant or Internal PCI Arbiter Grant 0 PCI_GNT# (Input): When the PEX 8114 Internal PCI Arbiter is disabled, this is a PCI/PCI-X Bus grant from the External Arbiter. PCI_GNT0# (Output): When the PEX 8114 Internal PCI Arbiter is enabled, PCI_GNT0# is an output to an arbitrating Master. The PEX 8114 Arbiter asserts PCI_GNT0# to grant the PCI/PCI-X Bus to the Master. J3, J4, H3 Internal PCI Arbiter Grants 3 to 1 (3 Balls) When the PEX 8114 Internal PCI Arbiter is enabled, PCI_GNT[3:1]# are outputs (one each) to an arbitrating Master. The Internal PCI Arbiter asserts PCI_GNT[3:1]# to grant the PCI/PCI-X Bus to the corresponding Master. Device Select Forward Transparent Bridge mode: PCI_IDSEL is not used and requires a pull-up resistor. Reverse Transparent Bridge mode: Used as a Chip Select during Configuration Write and Read transactions. PCI_IDSEL I PCI PCI_INT[D:A]# I/O OD PCI PCI_IRDY# I/O OD PCI B4 Initiator Ready PCI/PCI-X Bus Initiator ready. Indicates initiating agent’s (Bus Master) ability to complete the current Data phase of the transaction. PCI_M66EN I PCI B9 PCI Bus Clock Speed Capability Indicator Refer to Table 3-3. D7 Parity Even parity across PCI_AD[31:0] and PCI_C/BE[3:0]#. PCI_PAR is stable and valid one clock after the Address phase. For Data phases, PCI_PAR is stable and valid one clock after PCI_IRDY# is asserted on a Write transaction or PCI_TRDY# is asserted on a Read transaction. After PCI_PAR is valid, it remains valid until one clock after the current Data phase completes. C14 Upper 32 Bits Parity Even parity across PCI_AD[63:32] and PCI_C/BE[7:4]#. PCI_PAR64 is stable and valid one clock after the Address phase. For Data phases, PCI_PAR64 is stable and valid one clock after PCI_IRDY# is asserted on a Write transaction or PCI_TRDY# is asserted on a Read transaction. After PCI_PAR64 is valid, it remains valid until one clock after the current Data phase completes. PCI_PAR PCI_PAR64 20 I/O TS PCI I/O TS PCI E4 M2, K4, M1, L3 Interrupts D, C, B, and A (4 Balls) Forward Transparent Bridge mode: PCI/PCI-X Bus interrupt inputs. Reverse Transparent Bridge mode: PCI/PCI-X Bus interrupt outputs. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Table 2-3. PCI/PCI-X Bus Interface Signals PCI/PCI-X Bus Interface Signals (108 Balls) (Cont.) Symbol PCI_PCIXCAP PCI_PCIXCAP_PU Type I O PCI_PERR# I/O STS PCI PCI_PME# I/O TS PCI PCI_REQ# or PCI_REQ0# PCI_REQ[3:1]# PCI_REQ64# I/O PCI I PCI I/O STS PCI Location Description A5 PCI-X Capability Used with PCI_PCIXCAP_PU to determine whether all devices running on the PCI/PCI-X Bus are capable of running PCI-X cycles and at which frequency. Clock Master mode: Connect the PCI_PCIXCAP_PU ball to the PCI_PCIXCAP ball through a 1KΩ resistor when operating at PCI 66, and PCI-X 66 and 133. A 56KΩ resistor between VDD33 and the PCI_PCIXCAP ball is also required. C5 PCI/PCI-X Bus PCI_PCIXCAP Pull-Up Driver Used with PCI_PCIXCAP to determine whether all agents on the PCI/PCI-X Bus are PCI-X-compatible in Clock Master mode. Clock Master mode: Connect the PCI_PCIXCAP_PU ball to the PCI_PCIXCAP ball through a 1KΩ resistor when operating at PCI 66, and PCI-X 66 and 133. B6 Parity Error PCI/PCI-X Bus parity error indicator. Reports and records Data Parity errors during all PCI transactions, except during a special cycle. G4 Power Management Event Forward Transparent Bridge mode: PCI/PCI-X Bus Power Management Event (PME) indicator input. Reverse Transparent Bridge mode: PCI/PCI-X Bus Power Management Event indicator output. G2 Request or Internal PCI Arbiter Request 0 PCI_REQ# (Output): When the PEX 8114 Internal PCI Arbiter is disabled, this is a PCI/PCI-X Bus request to the External Arbiter. PCI_REQ0# (Input): When the PEX 8114 Internal PCI Arbiter is enabled, PCI_REQ0# is an input from an arbitrating Master. The Internal PCI Arbiter asserts PCI_GNT0# to grant the PCI/PCI-X Bus to the Master. H1, H2, G1 Internal PCI Arbiter Requests 3 to 1 (3 Balls) When the PEX 8114 Internal PCI Arbiter is enabled, PCI_REQ[3:1]# are inputs (one each) from an arbitrating Master. The Internal PCI Arbiter asserts a PCI_GNT[3:1]# signal to grant the PCI/PCI-X Bus to the corresponding Master. D12 64-Bit Transfer Request Asserted (0) with PCI_FRAME# by a PCI Bus Master to request a 64-bit Data transfer. Forward Transparent Bridge or Clock Master mode: The PEX 8114 asserts PCI_REQ64# during PCI_RST# to configure a 64-bit backplane. Reverse Transparent Bridge mode and not Clock Master: The PEX 8114 samples PCI_REQ64# at PCI_RST# de-assertion to configure a 32- or 64-bit PCI backplane. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 21 Signal Ball Description Table 2-3. PCI/PCI-X Bus Interface Signals (108 Balls) (Cont.) Symbol PCI_RST# PCI_SEL100 PLX Technology, Inc. Type I/O PCI I Location Description H4 Reset Forward Transparent Bridge mode, Output: Provides the PCI/PCI-X Bus reset. The PEX 8114 drives PCI_RST# and asserts PCI_RST# during the initialization period. Reverse Transparent Bridge mode, Input: Receives the external Reset signal from the bus. (Refer to Chapter 3, “Clock and Reset,” for further details.) Input that receives reset from an upstream Host and is the equivalent of Hot Reset internally and causes the propagation of Hot Reset across the PCI Express link. M4 Bus 100-MHz Indicator When the PCI/PCI-X Bus is operating in PCI-X Clock Master mode in Forward or Reverse Transparent Bridge mode, or Clock Slave mode in Forward Transparent Bridge mode: 0 = 133-MHz PCI-X Bus capability 1 = 100-MHz PCI-X Bus capability In Clock Slave mode, pull PCI_SEL100 High or Low. PCI_SERR# I/O OD PCI A6 Bus System Error Indicator Input: Assertion detected by the Host, indicates that a PCI System error occurred. Output: Asserted by a Target, indicates that a Fatal or Non-Fatal PCI Express Parity error occurred. PCI_STOP# I/O STS PCI C6 Stop Asserted by the Target to signal to end the transaction on the current Data phase. PCI_TRDY# I/O STS PCI D6 Target Ready Driven by the Transaction Target to indicate its ability to complete the current Data phase. 22 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.4 PCI Express Interface Signals PCI Express Interface Signals The PEX 8114 includes 23 PCI Express port interface signals, which are defined in Table 2-4. The port signals are Low-Voltage Differential Signal format that requires two balls for each lane, in each direction. The four PEX_LANE_GOOD[3:0]# signals are used to drive LEDs, to indicate the status of each lane. Table 2-4. PCI Express Interface Signals (23 Balls) Symbol PEX_LANE_GOOD[3:0]# Type O Location Description PCI Express Lane Status Indicators (4 Balls) R16, T16, R15, T15 0 = Lane active (LED is On) 1 = Lane inactive (LED is Off) PEX_PERn[3:0] I(-) LVDSRn M11, M9, M7, M5 Negative Half of PCI Express Receiver Differential Signal Pairs (4 Balls) PEX_PERp[3:0] I(+) LVDSRp N11, N9, N7, N5 Positive Half of PCI Express Receiver Differential Signal Pairs (4 Balls) PEX_PETn[3:0] O(-) LVDSTn T11, T9, T7, T5 Negative Half of PCI Express Transmitter Differential Signal Pairs (4 Balls) PEX_PETp[3:0] O(+) LVDSTp R11, R9, R7, R5 Positive Half of PCI Express Transmitter Differential Signal Pairs (4 Balls) I T1 PCI Express Reset Used to cause a Fundamental Reset. In Forward Transparent Bridge mode, PEX_PERST# is a 3.3V input with a weak internal pull-up resistor. (Refer to Chapter 3, “Clock and Reset,” for further details.) PEX_REFCLKn I(-) LVDSn R3 Negative Half of 100-MHz PCI Express Reference Clock Signal Pair (Refer to Chapter 3, “Clock and Reset,” for details.) PEX_REFCLKp I(+) LVDSp T3 Positive Half of 100-MHz PCI Express Reference Clock Signal Pair (Refer to Chapter 3, “Clock and Reset,” for details.) PEX_PERST# ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 23 Signal Ball Description 2.5 PLX Technology, Inc. Hot Plug Signals The PEX 8114 includes nine Hot Plug signals for the PCI Express port, defined in Table 2-5. Table 2-5. Hot Plug Signals (9 Balls) Symbol Type Location Description Hot Plug Attention LED Slot Control Logic output used to drive the Attention Indicator. Set Low to turn On the LED. HP_ATNLED# O HP_BUTTON# I PU HP_CLKEN# HP_MRL# O I PU T14 High/Off = Standard Operation Low/On = Operational problem at this slot Blinking = Slot is identified at the user’s request Blinking Frequency = 2.0 Hz, 50% duty cycle T13 Hot Plug Attention Button Slot Control Logic input directly connected to the Attention Button, which is pressed to request Hot Plug operations. Can be implemented on the bridge or downstream device. R14 Hot Plug Clock Enable Reference Clock enable output. Enabled when the Slot Capabilities register Power Controller Present bit is set (offset 7Ch[1]=1), and controlled by the Slot Control register Power Controller Control bit (offset 80h[10]). The time delay from HP_PWREN# (and HP_PWRLED#) output assertion to HP_CLKEN# output assertion is programmable from 16 ms (default) to 128 ms, in the HPC Tpepv Delay field (offset 1E0h[4:3]). R13 Hot Plug Manually Operated Retention Latch Sensor Slot Control Logic and Power Controller input directly connected to the Manually operated Retention Latch (MRL) Sensor. MRL switch signal for inserting and extracting Hot Plug-capable boards. High = Board is not available or properly seated in slot Low = Board not properly seated in slot HP_PERST# O P14 Hot Plug Reset Hot Plug Reset for downstream link. Enabled by the Slot Control register Power Controller Control bit (offset 80h[10]). HP_PRSNT# I PU P13 Hot Plug PCI Present Input connected to external logic that directly outputs PRSNT# from the external combination of PRSNT1# and PRSNT2#. HP_PWREN# O N14 Hot Plug Power Enable Slot Control Logic output that controls the slot power state. When HP_PWREN# is Low, power is enabled to the slot. HP_PWRFLT# I PU N13 Hot Plug Power Fault Input Indicates that the Slot Power Controller detected a power fault on one or more supply rails. HP_PWRLED# O M13 Hot Plug Power LED Slot Control Logic output used to drive the Power Indicator. This output is set Low to turn On the LED. 24 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.6 Strapping Signals Strapping Signals The eight PEX 8114 Strapping signals, defined in Table 2-6, set the configuration of Forward and Reverse Transparent Bridge mode, Clock Master and Arbiter Master selection, as well as various Setup and Test modes. These balls must be tied High to VDD33 or Low to VSS. Table 2-6. Strapping Signals (8 Balls) Symbol STRAP_ARB Type STRAP Location Description L5 Arbiter Select Internal or external PCI/PCI-X Arbiter select. Strapping signal that enables and disables the PEX 8114 PCI/PCI-X Internal PCI Arbiter. 1 = Enables the Arbiter 0 = Disables the Arbiter (refer to Chapter 11, “PCI/PCI-X Arbiter”) STRAP_CLK_MST STRAP L4 Clock Master Select In Clock Master mode, the 100-MHz PEX_REFCLKn/p signals are used to generate a clock of 25, 33, 50, 66, 100, or 133 MHz on the PCI_CLKO[3:0] balls. The clock frequency is determined by the PCI_M66EN clock, PCI_PCIXCAP, and PCI_SEL100 ball states. (Refer to Table 3-3.) 1 = PEX 8114 is the PCI_CLK Generator (Clock Master mode) 0 = PEX 8114 is the PCI_CLK Receiver (Clock Slave mode) STRAP_EXT_CLK_SEL STRAP_FWD STRAP STRAP N6 P16 External PCI Clock Select When the PEX 8114 is in Clock Master mode and this ball is Low, the PCI clock is driven from the internal PCI clock frequency generator to the internal PCI module by way of a fed back Clock signal. In this case, the PCI_CLK ball need not be driven by a Clock signal, but pulled to a known level by external circuitry. When the STRAP_EXT_CLK_SEL and STRAP_CLK_MST balls are High, the PCI clock must be driven externally from the PCI_CLKO_DLY_FBK output to the PCI_CLK input. The trace length and delay from PCI_CLK must match the length of other PCB traces driven from PCI_CLKO[3:0] to external PCI devices. Forward Transparent Bridge Mode Select Strapping signal that selects between Forward and Reverse Transparent Bridge modes. 1 = Forward Transparent Bridge mode 0 = Reverse Transparent Bridge mode STRAP_PLL_BYPASS# STRAP P3 STRAP_TESTMODE[1:0] STRAP T2, R2 PLL Bypass Factory Test Only Tied High for standard operation. Test Mode Select (2 Balls) Factory Test Only Tied High for standard operation (Test modes are disabled). Transparent Mode Select Strapping signal that selects Transparent mode. STRAP_TRAN STRAP P15 1 = Transparent mode 0 = Reserved Note: Value is always 1. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 25 Signal Ball Description 2.7 PLX Technology, Inc. JTAG Interface Signals The PEX 8114 includes five signals for performing JTAG boundary scan, defined in Table 2-7. For further details, refer to Section 15.3, “JTAG Interface.” Table 2-7. JTAG Interface Signals (5 Balls) Symbol Type Location JTAG_TCK I PU P1 Test Clock Input JTAG Test Access Port (TAP) Controller clock source. Frequency can be from 0 to 10 MHz. JTAG_TDI I PU N2 Test Data Input Serial input to the JTAG TAP Controller, for test instructions and data. JTAG_TDO O N1 Test Data Output Serial output to the JTAG TAP Controller test instructions and data. JTAG_TMS I PU P2 Test Mode Select When High, JTAG Test mode is enabled. Input decoded by the JTAG TAP Controller, to control test operations. R1 Test Reset Active-Low input used to reset the Test Access Port. Tie to ground through a 1.5KΩ resistor, to hold the JTAG TAP Controller in the Test-Logic-Reset state, which enables standard logic operation. When JTAG functionality is not used, the JTAG_TRST# input should be pulled or driven Low, to place the JTAG TAP Controller into the Test-Logic-Reset state, which disables the test logic and enables standard logic operation. Alternatively, if JTAG_TRST# input is High, the JTAG TAP Controller can be placed into the Test-Logic-Reset state by initializing the JTAG TAP Controller’s Instruction register to contain the IDCODE instruction, or by holding the JTAG_TMS input High for at least five rising edges of the JTAG_TCK input. JTAG_TRST# 26 I PU Description ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.8 Serial EEPROM Interface Signals Serial EEPROM Interface Signals The PEX 8114 includes five signals for interfacing to a serial EEPROM, defined in Table 2-8. EE_DO requires a weak internal pull-up resistor. Table 2-8. Symbol EE_CS# Serial EEPROM Interface Signals (5 Balls) Type Location O N15 Serial EEPROM Active-Low Chip Select Output Weakly pulled up. Can remain floating if not used, or use a stronger pull-up resistor (5KΩ to 10KΩ). M16 Serial EEPROM Data In PEX 8114 output to the serial EEPROM Data input. Weakly pulled up. Can remain floating if not used, or use a stronger pull-up resistor (5KΩ to 10KΩ). N16 Serial EEPROM Data Out PEX 8114 input from the serial EEPROM Data output. Weakly pulled up. Can remain floating if not used, or use a stronger pull-up resistor (5KΩ to 10KΩ). L13 Serial EEPROM Active-Low Present Input When a serial EEPROM is not used, must be pulled up to VDD33. A 5KΩ to 10KΩ pull-up resistor is recommended. Must be connected to VSS if a serial EEPROM is present and used. M14 7.8-MHz Serial EEPROM Clock For a PCI-X clock greater than 66 MHz, a 10-MHz serial EEPROM is needed. For clock rates of 66 MHz and lower, a 5-MHz serial EEPROM is sufficient. Weakly pulled up. Can remain floating if not used, or use a stronger pull-up resistor (5KΩ to 10KΩ). EE_DI O EE_DO I PU EE_PR# EE_SK I O Description ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 27 Signal Ball Description 2.9 PLX Technology, Inc. Power and Ground Signals Table 2-9. Power and Ground Signals (98 Balls) Symbol Type Location VDD10 CPWR E6, E8, E9, E11, F5, F12, G5, G12, J5, J12, K5, K12, M6, M10, M12 VDD10A APWR M8 VDD10S DPWR P8, R4, R6, R8, R10, R12 SerDes Digital Supply Voltage (6 Balls) 1.0V Power for SerDes Digital circuits. VDD33 I/OPWR B2, B8, B12, B15, E5, E7, E10, E12, F2, G15, H5, H12, J2, L12, M3, M15, P12 I/O Supply Voltage (17 Balls) 3.3V Power for I/O logic functions VRING. VDD33A PLLPWR P4 VSS GND B5, B13, C9, E2, F6, F7, F8, F9, F10, F11, F15, G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K2, K6, K7, K8, K9, K10, K11, L6, L7, L8, L9, L10, L11, L15, N8, N10, N12, P5, P6, P7, P9, P10, P11, T4, T8, T12 VSSA GND N4 Supply T10, T6 VTT_PEX[1:0] a. Description Core Supply Voltage (15 Balls) 1.0V Power for Core Logic VCORE. SerDes Analog Supply Voltage 1.0V Power for SerDes Analog circuits. PLL Analog Supply Voltage 3.3V Power for PLL circuits. Digital Ground Connections (55 Balls) Analog Ground Connection SerDes Termination Supply (2 Balls) Tied to SerDes termination supply voltage (typically 1.5V).a PEX_PETn/p[x] SerDes termination supply voltage controls the transmitter Common mode voltage (VTX–CM) value and output voltage swing (VTX–DIFFp), per the following formula: VTX-CM = VTT – VTX–DIFFp 28 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.10 Ball Assignments by Location Ball Assignments by Location Table 2-10. Ball Assignments by Location Loc Signal Name Loc Signal Name Loc Signal Name Loc Signal Name A1 PCI_AD21 C1 PCI_C/BE3# E1 PCI_AD29 G1 PCI_REQ1# A2 PCI_AD19 C2 PCI_AD22 E2 VSS G2 PCI_REQ# or PCI_REQ0# A3 PCI_C/BE2# C3 PCI_AD20 E3 PCI_AD26 G3 PCI_GNT# or PCI_GNT0# A4 PCI_DEVSEL# C4 PCI_AD16 E4 PCI_IDSEL G4 PCI_PME# A5 PCI_PCIXCAP C5 PCI_PCIXCAP_PU E5 VDD33 G5 VDD10 A6 PCI_SERR# C6 PCI_STOP# E6 VDD10 G6 VSS A7 PCI_AD14 C7 PCI_AD15 E7 VDD33 G7 VSS A8 PCI_AD12 C8 PCI_AD11 E8 VDD10 G8 VSS A9 PCI_AD10 C9 VSS E9 VDD10 G9 VSS A10 PCI_AD7 C10 PCI_AD6 E10 VDD33 G10 VSS A11 PCI_AD3 C11 PCI_AD2 E11 VDD10 G11 VSS A12 PCI_AD1 C12 PCI_AD0 E12 VDD33 G12 VDD10 A13 PCI_ACK64# C13 PCI_C/BE7# E13 PCI_AD56 G13 PCI_AD48 A14 PCI_C/BE6# C14 PCI_PAR64 E14 PCI_AD54 G14 PCI_AD46 A15 PCI_AD63 C15 PCI_AD62 E15 PCI_AD53 G15 VDD33 A16 PCI_AD61 C16 PCI_AD57 E16 PCI_AD51 G16 PCI_AD47 B1 PCI_AD23 D1 PCI_AD27 F1 PCI_AD31 H1 PCI_REQ3# B2 VDD33 D2 PCI_AD25 F2 VDD33 H2 PCI_REQ2# B3 PCI_AD17 D3 PCI_AD24 F3 PCI_AD30 H3 PCI_GNT1# B4 PCI_IRDY# D4 PCI_AD18 F4 PCI_AD28 H4 PCI_RST# B5 VSS D5 PCI_FRAME# F5 VDD10 H5 VDD33 B6 PCI_PERR# D6 PCI_TRDY# F6 VSS H6 VSS B7 PCI_C/BE1# D7 PCI_PAR F7 VSS H7 VSS B8 VDD33 D8 PCI_AD13 F8 VSS H8 VSS B9 PCI_M66EN D9 PCI_AD9 F9 VSS H9 VSS B10 PCI_AD8 D10 PCI_C/BE0# F10 VSS H10 VSS B11 PCI_AD5 D11 PCI_AD4 F11 VSS H11 VSS B12 VDD33 D12 PCI_REQ64# F12 VDD10 H12 VDD33 B13 VSS D13 PCI_C/BE5# F13 PCI_AD52 H13 PCI_AD44 B14 PCI_C/BE4# D14 PCI_AD60 F14 PCI_AD50 H14 PCI_AD42 B15 VDD33 D15 PCI_AD58 F15 VSS H15 PCI_AD45 B16 PCI_AD59 D16 PCI_AD55 F16 PCI_AD49 H16 PCI_AD43 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 29 Signal Ball Description PLX Technology, Inc. Table 2-10. Ball Assignments by Location (Cont.) Loc Signal Name Loc Signal Name Loc Signal Name Loc Signal Name J1 PCI_CLK L1 PCI_CLKO3 N1 JTAG_TDO R1 JTAG_TRST# J2 VDD33 L2 PCI_CLKO2 N2 JTAG_TDI R2 STRAP_TESTMODE0 J3 PCI_GNT3# L3 PCI_INTA# N3 PCI_CLKO_DLY_FBK R3 PEX_REFCLKn J4 PCI_GNT2# L4 STRAP_CLK_MST N4 VSSA R4 VDD10S J5 VDD10 L5 STRAP_ARB N5 PEX_PERp0 R5 PEX_PETp0 J6 VSS L6 VSS N6 STRAP_EXT_CLK_SEL R6 VDD10S J7 VSS L7 VSS N7 PEX_PERp1 R7 PEX_PETp1 J8 VSS L8 VSS N8 VSS R8 VDD10S J9 VSS L9 VSS N9 PEX_PERp2 R9 PEX_PETp2 J10 VSS L10 VSS N10 VSS R10 VDD10S J11 VSS L11 VSS N11 PEX_PERp3 R11 PEX_PETp3 J12 VDD10 L12 VDD33 N12 VSS R12 VDD10S J13 PCI_AD40 L13 EE_PR# N13 HP_PWRFLT# R13 HP_MRL# J14 PCI_AD38 L14 PCI_AD32 N14 HP_PWREN# R14 HP_CLKEN# J15 PCI_AD41 L15 VSS N15 EE_CS# R15 PEX_LANE_GOOD1# J16 PCI_AD39 L16 PCI_AD33 N16 EE_DO R16 PEX_LANE_GOOD3# K1 PCI_CLKO1 M1 PCI_INTB# P1 JTAG_TCK T1 PEX_PERST# K2 VSS M2 PCI_INTD# P2 JTAG_TMS T2 STRAP_TESTMODE1 K3 PCI_CLKO0 M3 VDD33 P3 STRAP_PLL_BYPASS# T3 PEX_REFCLKp K4 PCI_INTC# M4 PCI_SEL100 P4 VDD33A T4 VSS K5 VDD10 M5 PEX_PERn0 P5 VSS T5 PEX_PETn0 K6 VSS M6 VDD10 P6 VSS T6 VTT_PEX0 K7 VSS M7 PEX_PERn1 P7 VSS T7 PEX_PETn1 K8 VSS M8 VDD10A P8 VDD10S T8 VSS K9 VSS M9 PEX_PERn2 P9 VSS T9 PEX_PETn2 K10 VSS M10 VDD10 P10 VSS T10 VTT_PEX1 K11 VSS M11 PEX_PERn3 P11 VSS T11 PEX_PETn3 K12 VDD10 M12 VDD10 P12 VDD33 T12 VSS K13 PCI_AD36 M13 HP_PWRLED# P13 HP_PRSNT# T13 HP_BUTTON# K14 PCI_AD34 M14 EE_SK P14 HP_PERST# T14 HP_ATNLED# K15 PCI_AD37 M15 VDD33 P15 STRAP_TRAN T15 PEX_LANE_GOOD0# K16 PCI_AD35 M16 EE_DI P16 STRAP_FWD T16 PEX_LANE_GOOD2# 30 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.11 Ball Assignments by Signal Name Ball Assignments by Signal Name Table 2-11. Ball Assignments by Signal Name Signal Name Loc Signal Name Loc Signal Name Loc Signal Name Loc EE_CS# N15 PCI_AD12 A8 PCI_AD44 H13 PCI_CLKO3 L1 EE_DI M16 PCI_AD13 D8 PCI_AD45 H15 PCI_CLKO_DLY_FBK N3 EE_DO N16 PCI_AD14 A7 PCI_AD46 G14 PCI_DEVSEL# A4 EE_PR# L13 PCI_AD15 C7 PCI_AD47 G16 PCI_FRAME# D5 EE_SK M14 PCI_AD16 C4 PCI_AD48 G13 PCI_GNT# or PCI_GNT0# G3 HP_ATNLED# T14 PCI_AD17 B3 PCI_AD49 F16 PCI_GNT1# H3 HP_BUTTON# T13 PCI_AD18 D4 PCI_AD50 F14 PCI_GNT2# J4 HP_CLKEN# R14 PCI_AD19 A2 PCI_AD51 E16 PCI_GNT3# J3 HP_MRL# R13 PCI_AD20 C3 PCI_AD52 F13 PCI_IDSEL E4 HP_PERST# P14 PCI_AD21 A1 PCI_AD53 E15 PCI_INTA# L3 HP_PRSNT# P13 PCI_AD22 C2 PCI_AD54 E14 PCI_INTB# M1 HP_PWREN# N14 PCI_AD23 B1 PCI_AD55 D16 PCI_INTC# K4 HP_PWRFLT# N13 PCI_AD24 D3 PCI_AD56 E13 PCI_INTD# M2 HP_PWRLED# M13 PCI_AD25 D2 PCI_AD57 C16 PCI_IRDY# B4 JTAG_TCK P1 PCI_AD26 E3 PCI_AD58 D15 PCI_M66EN B9 JTAG_TDI N2 PCI_AD27 D1 PCI_AD59 B16 PCI_PAR D7 JTAG_TDO N1 PCI_AD28 F4 PCI_AD60 D14 PCI_PAR64 C14 JTAG_TMS P2 PCI_AD29 E1 PCI_AD61 A16 PCI_PCIXCAP A5 JTAG_TRST# R1 PCI_AD30 F3 PCI_AD62 C15 PCI_PCIXCAP_PU C5 PCI_ACK64# A13 PCI_AD31 F1 PCI_AD63 A15 PCI_PERR# B6 PCI_AD0 C12 PCI_AD32 L14 PCI_C/BE0# D10 PCI_PME# G4 PCI_AD1 A12 PCI_AD33 L16 PCI_C/BE1# B7 PCI_REQ# or PCI_REQ0# G2 PCI_AD2 C11 PCI_AD34 K14 PCI_C/BE2# A3 PCI_REQ1# G1 PCI_AD3 A11 PCI_AD35 K16 PCI_C/BE3# C1 PCI_REQ2# H2 PCI_AD4 D11 PCI_AD36 K13 PCI_C/BE4# B14 PCI_REQ3# H1 PCI_AD5 B11 PCI_AD37 K15 PCI_C/BE5# D13 PCI_REQ64# D12 PCI_AD6 C10 PCI_AD38 J14 PCI_C/BE6# A14 PCI_RST# H4 PCI_AD7 A10 PCI_AD39 J16 PCI_C/BE7# C13 PCI_SEL100 M4 PCI_AD8 B10 PCI_AD40 J13 PCI_CLK J1 PCI_SERR# A6 PCI_AD9 D9 PCI_AD41 J15 PCI_CLKO0 K3 PCI_STOP# C6 PCI_AD10 A9 PCI_AD42 H14 PCI_CLKO1 K1 PCI_TRDY# D6 PCI_AD11 C8 PCI_AD43 H16 PCI_CLKO2 L2 PEX_LANE_GOOD0# T15 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 31 Signal Ball Description PLX Technology, Inc. Table 2-11. Ball Assignments by Signal Name (Cont.) Signal Name Loc Signal Name Loc Signal Name Loc Signal Name Loc PEX_LANE_GOOD1# R15 VDD10 E9 VDD33 J2 VSS J9 PEX_LANE_GOOD2# T16 VDD10 E11 VDD33 L12 VSS J10 PEX_LANE_GOOD3# R16 VDD10 F5 VDD33 M3 VSS J11 PEX_PERn0 M5 VDD10 F12 VDD33 M15 VSS K2 PEX_PERn1 M7 VDD10 G5 VDD33 P12 VSS K6 PEX_PERn2 M9 VDD10 G12 VDD33A P4 VSS K7 PEX_PERn3 M11 VDD10 J5 VSS B5 VSS K8 PEX_PERp0 N5 VDD10 J12 VSS B13 VSS K9 PEX_PERp1 N7 VDD10 K5 VSS C9 VSS K10 PEX_PERp2 N9 VDD10 K12 VSS E2 VSS K11 PEX_PERp3 N11 VDD10 M6 VSS F6 VSS L6 PEX_PERST# T1 VDD10 M10 VSS F7 VSS L7 PEX_PETn0 T5 VDD10 M12 VSS F8 VSS L8 PEX_PETn1 T7 VDD10A M8 VSS F9 VSS L9 PEX_PETn2 T9 VDD10S P8 VSS F10 VSS L10 PEX_PETn3 T11 VDD10S R4 VSS F11 VSS L11 PEX_PETp0 R5 VDD10S R6 VSS F15 VSS L15 PEX_PETp1 R7 VDD10S R8 VSS G6 VSS N8 PEX_PETp2 R9 VDD10S R10 VSS G7 VSS N10 PEX_PETp3 R11 VDD10S R12 VSS G8 VSS N12 PEX_REFCLKn R3 VDD33 B2 VSS G9 VSS P5 PEX_REFCLKp T3 VDD33 B8 VSS G10 VSS P6 STRAP_ARB L5 VDD33 B12 VSS G11 VSS P7 STRAP_CLK_MST L4 VDD33 B15 VSS H6 VSS P9 STRAP_EXT_CLK_SEL N6 VDD33 E5 VSS H7 VSS P10 STRAP_FWD P16 VDD33 E7 VSS H8 VSS P11 STRAP_PLL_BYPASS# P3 VDD33 E10 VSS H9 VSS T4 STRAP_TESTMODE0 R2 VDD33 E12 VSS H10 VSS T8 STRAP_TESTMODE1 T2 VDD33 F2 VSS H11 VSS T12 STRAP_TRAN P15 VDD33 G15 VSS J6 VSSA N4 VDD10 E6 VDD33 H5 VSS J7 VTT_PEX0 T6 VDD10 E8 VDD33 H12 VSS J8 VTT_PEX1 T10 32 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 2.12 Physical Layout Physical Layout Figure 2-1. PEX 8114 256-Ball PBGA Package Physical Ball Assignment (Underside View) 16 15 14 13 12 11 10 9 8 7 6 2 1 A PCI_AD61 PCI_AD63 PCI_C/BE6# PCI_ACK64# PCI_AD1 PCI_AD3 PCI_AD7 PCI_AD10 PCI_AD12 PCI_AD14 PCI_SERR# PCI_AD19 PCI_AD21 A B PCI_AD59 VDD33 PCI_C/BE4# VSS VDD33 PCI_AD5 PCI_AD8 PCI_M66EN VDD33 PCI_C/BE1# PCI_PERR# VSS PCI_IRDY# PCI_AD17 VDD33 PCI_AD23 B C PCI_AD57 PCI_AD62 PCI_PAR64 PCI_C/BE7# PCI_AD0 PCI_AD2 PCI_AD6 VSS PCI_AD11 PCI_AD15 PCI_STOP# PCI_PCIXCAP _PU PCI_AD16 PCI_AD20 PCI_AD22 PCI_C/BE3# C D PCI_AD55 PCI_AD58 PCI_AD60 PCI_C/BE5# PCI_REQ64# PCI_AD4 PCI_C/BE0# PCI_AD9 PCI_AD13 PCI_PAR PCI_TRDY# PCI_FRAME# PCI_AD18 PCI_AD24 PCI_AD25 PCI_AD27 D E PCI_AD51 PCI_AD53 PCI_AD54 PCI_AD56 VDD33 VDD10 VDD33 VDD10 VDD10 VDD33 VDD10 VDD33 PCI_IDSEL PCI_AD26 VSS PCI_AD29 E F PCI_AD49 VSS PCI_AD50 PCI_AD52 VDD10 VSS VSS VSS VSS VSS VSS VDD10 PCI_AD28 PCI_AD30 VDD33 PCI_AD31 F G PCI_AD47 VDD33 PCI_AD46 PCI_AD48 VDD10 VSS VSS VSS VSS VSS VSS VDD10 PCI_PME# PCI_GNT# or PCI_GNT0# PCI_REQ# or PCI_REQ0# PCI_REQ1# G H PCI_AD43 PCI_AD45 PCI_AD42 PCI_AD44 VDD33 VSS VSS VSS VSS VSS VSS VDD33 PCI_RST# PCI_GNT1# PCI_REQ2# PCI_REQ3# H J PCI_AD39 PCI_AD41 PCI_AD38 PCI_AD40 VDD10 VSS VSS VSS VSS VSS VSS VDD10 PCI_GNT2# PCI_GNT3# VDD33 PCI_CLK J K PCI_AD35 PCI_AD37 PCI_AD34 PCI_AD36 VDD10 VSS VSS VSS VSS VSS VSS VDD10 PCI_INTC# PCI_CLKO0 VSS PCI_CLKO1 K L PCI_AD33 VSS PCI_AD32 EE_PR# VDD33 VSS VSS VSS VSS VSS VSS STRAP_ARB STRAP_CLK_ MST PCI_INTA# PCI_CLKO2 PCI_CLKO3 L M EE_DI VDD33 EE_SK HP_PWRLED# VDD10 PEX_PERn3 VDD10 PEX_PERn2 VDD10A PEX_PERn1 VDD10 PEX_PERn0 PCI_SEL100 VDD33 PCI_INTD# PCI_INTB# M N EE_DO EE_CS# VSS PEX_PERp3 VSS PEX_PERp2 VSS PEX_PERp1 STRAP_EXT_ CLK_SEL PEX_PERp0 VSSA PCI_CLKO_DL Y_FBK JTAG_TDI JTAG_TDO N HP_PRSNT# VDD33 VSS VSS VSS VDD10S VSS VSS VSS VDD33A STRAP_PLL_ BYPASS# JTAG_TMS JTAG_TCK P HP_MRL# VDD10S PEX_PETp3 VDD10S PEX_PETp2 VDD10S PEX_PETp1 VDD10S PEX_PETp0 VDD10S PEX_REFCLK STRAP_TEST JTAG_TRST# n MODE0 R VSS PEX_PETn3 VTT_PEX1 PEX_PETn2 VSS PEX_PETn1 VTT_PEX0 PEX_PETn0 VSS PEX_REFCLK STRAP_TEST PEX_PERST# p MODE1 T 12 11 10 9 8 7 6 5 4 HP_PWREN# HP_PWRFLT# P STRAP_FWD STRAP_TRAN HP_PERST# R PEX_LANE_G PEX_LANE_G OOD3# OOD1# T PEX_LANE_G PEX_LANE_G HP_ATNLED# HP_BUTTON# OOD2# OOD0# 16 15 HP_CLKEN# 14 13 5 4 3 PCI_PCIXCAP PCI_DEVSEL# PCI_C/BE2# ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 3 2 1 33 Signal Ball Description PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 34 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 3 3.1 Clock and Reset Introduction to PEX 8114 Clocking Note: The PEX 8114 is compliant with the PCI-X r1.0b and PCI-X r2.0a. The PEX 8114 PCI/PCI-X clock domain PLL may be driven by either the 100-MHz PEX_REFCLKn/p input, or by the PCI_CLK input. When the PCI/PCI-X clock domain PLL is driven by PEX_REFCLKn/p, the PLL is used to synthesize the PCI system clock and the PEX 8114 is referred to as operating in Clock Master mode. When the PCI/PCI-X clock domain PLL is driven by PCI_CLK, the PEX 8114 is referred to as operating in Clock Slave mode. The PEX 8114 includes a PCI-X Bus Clock Generator and two internal clock domains – one each for PCI/PCI-X and PCI Express. In Clock Master mode, the Clock Generator is capable of synthesizing common PCI/PCI-X clock frequencies and driving four Clock Output balls, PCI_CLKO[3:0]. The PCI Express clock domain runs at a frequency that is compatible with 2.5-Gbps PCI Express data transmission rates, and is always a slave to the PEX_REFCLKn/p inputs. In Clock Slave mode, the PCI/PCI-X clock domain is driven by the PCI_CLK Input system clock and runs at the same frequency. 3.1.1 PCI/PCI-X Clock Generator The PEX 8114 PCI/PCI-X Clock Generator is used to synthesize PCI/PCI-X Bus clocks when operating in Clock Master mode. If the STRAP_CLK_MST ball is High when the PEX 8114 exits reset, the PCI_CLKO[3:0] and PCI_CLKO_DLY_FBK outputs drive active clocks. The PCI/PCI-X Clock Generator is driven by PEX_REFCLKn/p, and can generate PCI/PCI-X Bus system clocks to drive four external devices. These clocks are driven out of the PEX 8114, onto the PCI_CLKO[3:0] balls. In addition to PCI_CLKO[3:0], the Clock Master circuitry also provides a PCI_CLKO_DLY_FBK Clock Output ball. The PCI_CLKO_DLY_FBK output can optionally drive the PCI_CLK input to the PEX 8114, by way of a trace on the Printed Circuit Board (PCB). This trace length should be optimized to ensure that the PCI/PCI-X System Clock-phase alignment requirements are satisfied when other devices require long clock traces due to their placement on the PCB. More detail is provided in Section 3.1.3. When the PCI/PCI-X Clock Generator is enabled (STRAP_CLK_MST input ball High), the synthesized PCI/PCI-X clock frequency is determined by the PCI_M66EN, PCI_PCIXCAP, PCI_PCIXCAP_PU, and PCI_SEL100 balls. (Refer to Section 3.3.) When the PEX 8114 is the Clock Master, it sets the mode (PCI or PCI-X) and the clock frequency when Reset de-asserts. The Clock Generator is capable of synthesizing frequencies at 25. 33. 50, 66, 100, and 133 MHz. Additionally, the PCI_CLKO[3:0] signals can be individually disabled by writing 0 to the register bit associated with that specific output (PCI_CLKO_EN[3:0] field, offset FA0h[3:0]). When the PEX 8114 exits reset with STRAP_CLK_MST Low, the Clock Generator is disabled and the PCI_CLKO[3:0] and PCI_CLKO_DLY_FBK outputs are driven Low. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 35 Clock and Reset 3.1.2 PLX Technology, Inc. Clocking of PCI and PCI-X Modules The PEX 8114 PCI and PCI-X modules must be supplied a clock, from either the PEX 8114’s internal Clock Generator or a system-level Clock Generator. 3.1.2.1 Clocking PCI and PCI-X Modules with External Clock When the PEX 8114 is not used as the PCI System Clock Generator (Clock Slave mode), the PCI/PCI-X Bus clock must be supplied to the PEX 8114 PCI_CLK input ball. The External Clock Generator is required to supply a phase-aligned clock to each PCI/PCI-X device on the bus, allowing the devices to meet the phase-alignment requirements. The PCI-X module can be driven at PCI-X clock frequencies up to 133 MHz and down to DC, while the PCI module can be driven at frequencies up to 66 MHz and down to DC. The mode (PCI or PCI-X) and frequency is determined by reading the initialization pattern on the PCI-X Bus, as described in Section 3.2.2, which is compliant with the PCI-X r1.0b and PCI-X r2.0a. 3.1.2.2 Clocking PCI and PCI-X Modules with Internal Clock Generator When the PEX 8114 is operating in Clock Master mode (STRAP_CLK_MST is High), the internal clock generation circuitry is enabled. In addition, the STRAP_EXT_CLK_SEL ball must be Low. The clock generator will supply the internal PCI clock and drive out four PCI clocks for external devices on the PCI_CLKO[3:0] balls. 3.1.3 Clocking External PCI/PCI-X Devices When the PEX 8114 is operating in Clock Master mode, the PCI_CLKO[3:0] balls supply a PCI clock, for up to four external devices. To keep the external PCI clock within phase-alignment specifications, phase delays due to long PCB clock traces may be compensated for by using the PEX 8114’s PCI_CLKO_DLY_FBK output. Strap the STRAP_EXT_CLK_SEL ball High, to enable the clock feedback mode, and connect the PCI_CLKO_DLY_FBK ball to the PCI_CLK ball. Typically, the PCB trace length from the PCI_CLKO_DLY_FBK output to the PCI_CLK input is equal to the length of the clock traces from the PEX 8114’s PCI_CLKO[3:0] balls to the other external device’s clock inputs. This provides the ability to align the PEX 8114’s PCI_CLK input with the other device’s PCI_CLK inputs, although the other device’s clocks are driven across a long PCB trace. 36 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.2 Determining PCI Bus and Internal Clock Initialization Determining PCI Bus and Internal Clock Initialization Upon exiting reset, the state of the STRAP_FWD and STRAP_CLK_MST strapping balls are detected to configure the PEX 8114 as a Forward or Reverse Transparent bridge and as a Clock Slave or Master, respectively. The PEX 8114 is capable of operating as a Forward or Reverse PCI Express bridge, using its internal PLL to synthesize a PCI clock for the PCI Bus, or it can become a Slave to an incoming PCI Clock: • PCI mode – PEX 8114 is capable of operating as a Clock Master at 25, 33, 50, or 66 MHz, or Clock Slave, at frequencies from 66 MHz down to DC • PCI-X mode – PEX 8114 is capable of operating as a Clock Master at 50, 66, 100, or 133 MHz, or Clock Slave, at frequencies from 133 MHz down to DC The PEX 8114 must be able to determine a number of factors to properly initialize itself and the PCI/ PCI-X Bus. The following sections describe what determines this initialization. 3.2.1 Bridge Mode and Clocking Functions The following parameters must be initialized upon exiting reset: • Forward or Reverse Transparent Bridge – the STRAP_FWD ball determines the bridge mode • Clock Master or Slave – the STRAP_CLK_MST ball determines whether to initialize the internal PCI PLL to Clock Master or Clock Slave mode Table 3-1 defines how the PEX 8114 operates based upon whether it is configured to run as a Forward or Reverse PCI Express bridge, and as a Clock Master or Slave. Table 3-1. PEX 8114 Bridge Mode and Clocking Functions Mode Bus Capability Internal Clock Configuration Bus Initialization Pattern PCI_RST# Forward Transparent bridge as PCI Clock Master Detects Synthesize PCI clock and PCI_CLKO[3:0] balls Drive Drive Forward Transparent bridge as PCI Clock Slave Detects Slave to PCI clock Drive Drive Reverse Transparent bridge as PCI Clock Master Detects Synthesize PCI clock and PCI_CLKO[3:0] balls Drive Receive Reverse Transparent bridge as PCI Clock Slave Does not detect Slave to PCI clock Receive Receive ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 37 Clock and Reset 3.2.2 PLX Technology, Inc. Determining Bus Mode Capability and Maximum Frequency If the PEX 8114 is configured to operate as a Clock Master or a Forward PCI Express bridge in Clock Slave mode, it must determine the system’s PCI/PCI-X Bus mode capabilities and maximum frequency, using the PCI_PCIXCAP and PCI_PCIXCAP_PU balls. Table 3-2 defines how the bus mode (PCI or PCI-X) and the maximum clock frequency are determined by the state of the PCI_PCIXCAP ball. For the three clock frequencies listed in the table, connect the PCI_PCIXCAP_PU ball to the PCI_PCIXCAP ball, through a 1KΩ resistor. A 56KΩ resistor between 3.3V and the PCI_PCIXCAP ball is also required. Upon exit from reset, the PEX 8114 detects this circuitry to determine the bus mode and maximum clock frequency. • PCI mode – PEX 8114 is capable of operating as a Clock Master at 25, 33, 50, or 66 MHz, or Clock Slave, at frequencies from 66 MHz down to DC • PCI-X mode – PEX 8114 is capable of operating as a Clock Master at 50, 66, 100, or 133 MHz, or Clock Slave, at frequencies from 133 MHz down to DC Table 3-2. Bus Mode, Maximum Clock Frequency, and PCI_PCIXCAP Ball Circuitry Bus Mode Maximum Clock Frequency PCI_PCIXCAP Ball PCI 66 MHz Grounded 66 MHz Grounded through an RC network 133 MHz Connected to a capacitor PCI-X 38 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Clock Master Mode 3.3 PCI Clock Master Mode 3.3.1 Clock Master – Forward Transparent Bridge Mode When the PEX 8114 is strapped as the Clock Master (STRAP_CLK_MST is High), the PEX 8114 uses the PCI Express 100 MHz Reference Clock (PEX_REFCLKn/p) to synthesize the PCI_CLKO clock(s). It determines the frequency to synthesize, by sampling the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls during the clock initialization period. (Refer to Table 3-3.) The clock initialization period is the time following the de-assertion of the PCI Express Reset input (PEX_PERST#), and before PCI Reset (PCI_RST#) de-assertion. During the clock initialization period, the PEX 8114 runs a simple state machine to determine the frequency to be generated by the clock synthesizer. The state machine samples the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls to determine the correct PCI_CLKO frequency, initializes the clock synthesizer, drives the correct PCI-X bus initialization values on the PCI_DEVSEL#, PCI_STOP#, and PCI_TRDY# signals and, when the PLL locks, de-asserts PCI_RST# (Forward Transparent Bridge mode) or waits for PCI_RST# de-assertion (Reverse Transparent Bridge mode). When STRAP_FWD is High (Forward Transparent Bridge mode), PCI_RST# is an output, and the PEX 8114 asserts PCI_RST# during the initialization period. Table 3-3 defines the PLL divider frequency. Figure 3-1 through Figure 3-3 illustrate the pertinent signals and the clock initialization and reset sequence that the PEX 8114 follows when strapped in Clock Master mode. Table 3-3. Mode Clock Master Mode PLL Divider Frequency Clock Frequency 25 MHz PCI 33 MHz 50 MHz 66 MHz 50 MHz PCI-X 66 MHz 100 MHz 133 MHz PCI_PCIXCAP PCI_SEL100 GND GND 10KΩ to GND High 1 0 1 0 1 0 1 0 PCI_M66EN 0 1 X X Note: “X” indicates “Don’t Care.” ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 39 Clock and Reset PLX Technology, Inc. Figure 3-1 illustrates the PEX 8114 configured as a Clock Master in Forward Transparent Bridge mode. This configuration uses the 100 MHz Reference Clock (PEX_REFCLKn/p) to generate 25-, 33-, 50-, 66-, 100-, or 133-MHz PCI_CLKO[3:0] signals and a phase-advanced internal clock. PCI_RST# is an output in Forward Transparent Bridge mode. Figure 3-1. Clock Master Mode – Forward Transparent Bridge Mode Inputs Outputs STRAP_FW D=1 PCI_CLKO3 STRAP_CLK_MST=1 PCI_CLKO2 PEX_REFCLKn/p PEX_PERST# Clock Master / Forward Transparent Bridge Mode PCI_CLKO1 PCI_PCIXCAP PCI_CLKO0 PCI_SEL100 PCI_RST# PCI_M66EN PCI_DEVSEL# PCI_STOP# PCI_TRDY# PCI_PCIXCAP_PU The sequence of events for configuring the internal clock generation circuitry in Forward Transparent Bridge mode is as follows: 40 1. PEX_PERST# is de-asserted, and STRAP_CLK_MST and STRAP_FWD are detected as being High. 2. PEX 8114 reads the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls to determine clock frequency. 3. PEX 8114 loads its internal PLL values. 4. PEX 8114 internal PLL reports lock up. 5. PEX 8114 drives PCI_DEVSEL#, PCI_STOP#, and PCI_TRDY# initial values. 6. PEX 8114 de-asserts PCI_RST#. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.3.2 Clock Master – Reverse Transparent Bridge Mode Clock Master – Reverse Transparent Bridge Mode The PEX 8114 operation as a Clock Master in Reverse Transparent Bridge mode is identical in many respects to its operation as a Clock Master in Forward Transparent Bridge mode. Therefore, refer to the description in Section 3.3.1 for detailed information. Reverse Transparent Bridge mode differs from Forward Transparent Bridge mode in two ways – the STRAP_FWD ball is strapped Low and PCI_RST# becomes an input. Figure 3-2 illustrates the Clock Master in Reverse Transparent Bridge mode. Figure 3-2. Clock Master Mode – Reverse Transparent Bridge Mode Inputs Outputs STRAP_FWD=0 PCI_CLKO3 STRAP_CLK_MST=1 PEX_REFCLKn/p Clock Master / Reverse Transparent Bridge Mode PEX_PERST# PCI_CLKO2 PCI_CLKO1 PCI_CLKO0 PCI_RST# PCI_PCIXCAP PCI_DEVSEL# PCI_STOP# PCI_SEL100 PCI_TRDY# PCI_M66EN PCI_PCIXCAP_PU The sequence of events for configuring the internal clock generation circuitry in Reverse Transparent Bridge mode is as follows: 1. PEX_PERST# is de-asserted, STRAP_CLK_MST is High, and STRAP_FWD is Low. 2. PEX 8114 reads the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls to determine clock frequency. 3. PEX 8114 loads its internal PLL values. 4. PEX 8114 PLL reports lock up internally. 5. PEX 8114 drives PCI_DEVSEL#, PCI_STOP#, and PCI_TRDY# initial values. 6. PCI_RST# is de-asserted by external (system) logic. The external system logic must allow PCI_RST# to remain Low for 1 ms. As required by the PCI r3.0, the internal PLLs lock up during this 1-ms period. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 41 Clock and Reset PLX Technology, Inc. Figure 3-3 illustrates the Clock signal for Clock Master mode. Figure 3-3. 100 MHz ref Clock Signal for Clock Master Mode f PCI_CLKO[3:0] = (100 MHz) PCI_CLKO[3:0] Notes: PLL is driven by the 100-MHz PEX_REFCLKn/p, from which PCI_CLKO[3:0] frequency is synthesized. 2. PCI_CLK is unused, unless the PEX 8114 is configured in Clock Feedback mode by strapping STRAP_EXT_CLK_SEL input High. 1. 42 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.4 PCI Clock Slave Mode PCI Clock Slave Mode When the PEX 8114 is strapped as a Clock Slave (STRAP_CLK_MST is Low), a PLL is used to cancel the internal Clock Fan-Out delay for PCI clock frequencies above 33 MHz. When the PCI_CLK input frequency is 33 MHz or lower, the PLL is bypassed and the PCI_CLK input directly drives the PCI internal circuitry. 3.4.1 Clock Slave – Forward Transparent Bridge Mode When the Clock Slave state machine is run in Forward Transparent Bridge mode, the PEX 8114 receives a clock input, but takes responsibility for driving the PCI-X initialization pattern at reset. Because the PEX 8114 drives the initialization pattern, it detects the circuit connected to the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls to determine the PCI Bus maximum clock frequency and which PCI-X initialization pattern to drive. External clock generation circuitry must: 1. Determine and set the clock frequency, according to the values on PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100, or 2. Limit the system maximum clock frequency by driving values on PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100. This requires coordination of the Clock Generator frequency and the values that the PEX 8114 reads on the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 43 Clock and Reset PLX Technology, Inc. Figure 3-4 illustrates the pertinent signals and reset sequence that the PEX 8114 follows when in Clock Slave mode. The PEX 8114 supplies the bus initialization in Forward Transparent Bridge mode. Figure 3-4. Clock Slave Mode – Forward Transparent Bridge Mode Outputs Inputs STRAP_FWD=1 STRAP_CLK_MST=0 PCI_CLK Clock Slave / Forward Transparent Bridge Mode PCI_STOP# PEX_PERST# PCI_TRDY# PCI_PCIXCAP PCI_DEVSEL# PCI_M66EN PCI_RST# PCI_SEL100 The sequence of events for initializing the Clock Slave in Forward Transparent Bridge mode is: 44 1. PEX_PERST# is de-asserted, STRAP_CLK_MST is Low, and STRAP_FWD is High. 2. PEX 8114 reads the PCI_M66EN, PCI_PCIXCAP, and PCI_SEL100 balls, to determine the clock frequency at the PCI_CLK input driven by an external Clock Generator. 3. PEX 8114 sets up to use its internal PLL and waits until lock if the clock frequency is greater than 33 MHz. If the clock frequency is 33 MHz or lower, the internal PLL is bypassed. 4. PEX 8114 drives PCI_DEVSEL#, PCI_STOP#, and PCI_TRDY# during the initialization period, prior to de-asserting PCI_RST#. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.4.2 Clock Slave – Reverse Transparent Bridge Mode Clock Slave – Reverse Transparent Bridge Mode In Reverse Clock Slave mode, the PEX 8114 reads the initialization pattern at PCI_RST# de-assertion, to determine bus mode and clock frequency, then loads the internal PLL. When the PEX 8114 is a Reverse Clock Slave, it is not the central resource and as such, it must detect the PCI-X initialization pattern to determine protocol and frequency. For this mode, PCI_PCIXCAP, PCI_PCIXCAP_PU, and PCI_SEL100 can be pulled High or Low. Figure 3-5. Clock Slave Mode – Reverse Transparent Bridge Mode Inputs STRAP_FWD=0 STRAP_CLK_MST=0 PCI_CLK PCI_RST# Clock Slave / Reverse Transparent Bridge Mode PEX_PERST# PCI_STOP# PCI_TRDY# PCI_DEVSEL# The sequence of events for initializing the Clock Slave in Reverse Transparent Bridge mode is: 1. PEX_PERST# is de-asserted, and STRAP_CLK_MST and STRAP_FWD are Low. 2. PEX 8114 waits for PCI_RST# de-assertion and the initialization pattern (driven by a device other than the PEX 8114). 3. System PCI clock rate is indicated to the PEX 8114, by the initialization pattern at PCI_RST# de-assertion. If the PCI clock rate indicated by the initialization pattern is 33 MHz or lower, the internal PLL is bypassed. If the initialization pattern indicates a clock rate greater than 33 MHz, load the internal PLL with appropriate settings. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 45 Clock and Reset 3.4.3 PLX Technology, Inc. Timing Diagrams – Forward or Reverse Transparent Bridge Mode Figure 3-6. Phase Offset in Clock Slave Mode – Frequency > 33 MHz PCI_CLK pCLK phase Notes: PLL is driven by the PCI_CLK input. PLL input and output frequencies are equal to one another. The PLL is used to provide phase advance, to compensate for clock tree delay within the PEX 8114. 3. pCLK is equal to the PCI_CLK input in frequency and phase. 4. STRAP_CLK_MST is Low. 1. 2. Figure 3-7. Phase Offset in Clock Slave Mode – Frequencies < 33 MHz PCI_CLK pCLK phase Notes: PLL is bypassed. Internal pCLK is phase-delayed, with respect to the PCI_CLK input. 3. PCI_CLK must drive the PCI/PCI-X Bus and PEX 8114. Do not use PCI_CLKO[3:0] to drive the PCI/PCI-X Bus PCI_CLK traces. 4. STRAP_CLK_MST is Low. 1. 2. 46 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Timing Diagrams – Forward or Reverse Transparent Bridge Mode The PCI Express and PCI-X PLLs contain a signal that indicates to the PEX 8114 whether the PLL has lost the PLL lock. It is considered a serious error condition if the PCI Express or PCI-X PLL loses lock (that is, when not in PLL Bypass mode), and indicates potential data errors. Loss of PLL lock can be caused by one of the following: • Significant out-of-specification noise • Voltages on the PLL power inputs • Out-of-specification jitter on the input REFCLK Table 3-4 defines the options for handling loss of PLL lock. The options are selected by the PLL Lock Control 1 and PLL Lock Control 0 bits (offset FA0h[11:10], respectively). By default, these bits are cleared to 00b, which configures the PEX 8114 to ignore loss of PLL lock. Sticky bits are set when the PCI Express or PCI-X PLL loses PLL lock: • When the PCI Express PLL loses PLL lock, the Sticky PCI Express PLL Loss Lock bit is set (offset FA0h[15]=1) • When the PCI-X PLL loses PLL lock, the Sticky PCI-X PLL Loss Lock bit is set (offset FA0h[14]=1) Table 3-4. Methods for Handling Loss of PLL Lock Offset FA0h[11:10] Description 00b Default. Ignores loss of PLL lock. 01b Loss of PLL lock immediately causes the PEX 8114 to reset. 10b The PEX 8114 attempts to tolerate loss of PLL lock: • When lock is re-acquired in less than 200 µs, the PEX 8114 is not reset • When lock is not re-acquired within 200 µs, the PEX 8114 is reset 11b The PEX 8114 is not reset if loss of PLL lock occurs. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 47 Clock and Reset 3.5 PLX Technology, Inc. Resets This section explains the PEX 8114 Reset mechanisms and how the differences between PCI Express and PCI/PCI-X resets are incorporated in Forward and Reverse Transparent Bridge modes. Table 3-5 defines the various reset types and their impact on the PEX 8114. Table 3-5. Reset Types and Impact on PEX 8114 Reset Definition Reset Source Fundamental Reset • Cold Reset • Warm Reset (Forward Transparent Bridge mode only) PEX_PERST# Reset input assertion Hot Reset (Forward Transparent Bridge mode only) PCI_RST# (Reverse Transparent Bridge mode only) Impact to Various Internal Components (Upon De-Assertion) Impact to Internal Registers (No AUX and PME Enabled) • Initialize entire bridge, including Sticky registers • Serial EEPROM contents are loaded • HwInit types evaluated All registers initialized • Reset bit of the TS1 Ordered-Sets is set, at upstream port • Upstream port entering DL_Down state • Initialize ports • Initialize entire bridge except the Sticky registers • Serial EEPROM contents re-loaded (selectively) PCI_RST# is asserted on PCI/PCI-X Bus Forward Transparent Bridge mode • • • • Assert PCI_RST# on PCI-X Bus Drain traffic Drop request TLPs Redefine Bus mode and clock frequency in Clock Master mode All registers initialized, with following exceptions: • Port Configuration registers • All Sticky bits not affected by Hot Reset (HwInit, ROS, RWCS, RWS) No effect to CSRs • PCI Express propagates Hot Reset • PCI Express DL down • TLP layer initialized and exhibits Secondary Bus Reset Reverse Transparent Bridge mode DL_Down behavior • Drop request TLPs • Drain traffic corresponding to DL_Down No effect to CSRs (other than to initialize credits) behavior and initialize credits • Re-define Bus mode and clock frequency in Clock Master mode 48 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.5.1 Fundamental Reset (Power-On, Hard, Cold, Warm Reset) Fundamental Reset (Power-On, Hard, Cold, Warm Reset) The PCI Express r1.0a defines the Fundamental Reset as a Cold or Warm Reset. Cold Reset is equivalent to the traditional Power-On Reset, while a Warm Reset is a Fundamental Reset without the cycling of power. Reset assertion by the system (external to the PEX 8114) causes a reset of all internal PEX 8114 registers, including Sticky bits, and drives all state machines to known states. 3.5.1.1 PEX_PERST# The sideband PCI Express Reset signal (PEX_PERST#) is routed in parallel to all system PCI Express devices, and is used to initiate a Fundamental reset. Fundamental reset can be provided by the system Host or a central resource. For the PEX 8114, the PEX_PERST# signal is always an input, whether in Forward and Reverse Transparent Bridge modes. A Power Good signal, indicating whether the system power supply levels are within tolerances, is normally used in conjunction with the PEX_PERST# signal. In Forward Transparent Bridge mode, the PCI Express Root Complex supplies the PEX_PERST# signal to all devices. The reset is forwarded to the secondary bus as a Conventional PCI Reset. In Reverse Transparent Bridge mode, the PCI central resource, including power supply monitors, feeds the PEX_PERST# signal to all PCI Express devices. In Reverse Transparent Bridge mode, the PEX_PERST# signal is expected to function similarly to the pwr_good signal in the PCI r3.0 (Figure 4.11), and to follow the timing and functionality defined in the PCI r3.0, Section 4.3.2. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 49 Clock and Reset 3.5.1.2 PLX Technology, Inc. Fundamental Reset – Forward Transparent Bridge Mode When operating in Forward Transparent Bridge mode and the system asserts PEX_PERST# to the PEX 8114, the PCI_RST# signal is asserted on the PCI/PCI-X Bus. Figure 3-8 illustrates the timing relationship between PEX_PERST#, PCI_RST#, and the PEX 8114 internal reset in Forward Transparent Bridge mode. Figure 3-8. PEX_PERST# Input, PCI_RST# Output, and Internal Reset Timing in Forward Transparent Bridge Mode 1 ms PEX_PERST# Internal Reset PCI_RST# Timing Requirement When power is first applied, PEX_PERST# is asserted by the Root Complex or central resource and remains asserted until power is stable. The PCI r3.0 places a power-up timing requirement on the PCI_RST# Bus Reset signal, which is that PCI_RST# must remain asserted for 1 ms after power becomes stable. This applies to the PEX 8114 in Forward Transparent Bridge mode because the PEX 8114 asserts PCI_RST# in this mode. Manual Switches – Defining a Warm Reset in Forward Transparent Bridge Mode A Warm Reset can be applied to the PEX 8114 by an on-board manual switch, which controls the PEX_PERST# signal. This method supplies a Fundamental Reset without cycling the power supply. Note: Perform Warm Resets only in Forward Transparent Bridge mode. 50 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.5.1.3 Fundamental Reset (Power-On, Hard, Cold, Warm Reset) Fundamental Reset – Reverse Transparent Bridge Mode In Reverse Transparent Bridge mode, PCI_RST# is an input to the PEX 8114. It is a requirement that PCI_RST# be asserted during PEX_PERST# assertion and for an additional 1 ms after PEX_PERST# de-assertion. Figure 3-9 illustrates the PEX_PERST# and PCI_RST# timing waveforms during Fundamental Reset in Reverse Transparent Bridge mode. Figure 3-9. PEX_PERST# and PCI_RST# Timing in Reverse Transparent Bridge Mode 1 ms PEX_PERST# PCI_RST# Timing Requirement In Reverse Transparent Bridge mode, the Root Complex or a central resource asserts PEX_PERST# after power-on, and the PCI Host connected to the PEX 8114 asserts PCI_RST#. PEX_PERST# and PCI_RST# must remain asserted until power becomes stable. When power is stable, PEX_PERST# must de-assert first and, a minimum of 1 ms later, PCI_RST# can de-assert. There is no limit on the maximum PEX_PERST# assertion time; however, PCI_RST# must continue 1 ms longer, or the PEX 8114 might not function correctly. This requirement is associated with initialization pattern capture. Manual Switches – Defining a Warm Reset in Reverse Transparent Bridge Mode When PCI_RST# is asserted in Reverse Transparent Bridge mode, the initialization pattern is driven on the PCI/PCI-X Bus and the pattern is captured when PCI_RST# is de-asserted. When the PEX 8114 is strapped as the Clock Master in Reverse Transparent Bridge mode, it drives the initialization pattern on the PCI/PCI-X Bus, but not the PEX 8114 PCI_RST# signal. A PCI reset can be initiated with a manual switch. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 51 Clock and Reset 3.5.2 PLX Technology, Inc. Hot Reset The Hot Reset defined by the PCI Express r1.0a is an in-band message communicated across a link. Hot Reset affects internal registers and state machines, but not register Sticky bits. A Hot Reset propagates across the bridge and to the downstream devices by causing the assertion of the PCI_RST# signal. 3.5.2.1 Hot Reset – Forward Transparent Bridge Mode The Root Complex and central resource have the capability of resetting a specific PCI Express link using a Hot Reset. (This contrasts with a Fundamental Reset, which resets the entire system.) When operating in Forward Transparent Bridge mode, the PEX 8114 receives the Hot Reset command, using an in-band transaction (TS1 Ordered-Sets) from the upstream PCI Express device. The PEX 8114 propagates the reset downstream, by asserting the PCI_RST# signal. In addition, if the PCI Express port upstream of the PEX 8114 transitions to a DL_Down state, this is also treated as a Hot Reset. This reset is propagated downstream from the PEX 8114, by asserting the PCI_RST# signal, in an identical manner to the in-band Hot Reset command. The PCI r3.0 requires that PCI_RST# reset must have a minimum assertion time of 1 ms. In the case of a Hot Reset, the Root Complex or central resource must provide the 1-ms PCI_RST# duration, by transmitting the in-band Hot Reset for 1 ms. Figure 3-10 illustrates the timing of propagating PCI_RST# when a Hot Reset is received by the PCI Express interface. Figure 3-10. In-Band Hot Reset, PCI_RST#, and Internal Reset Timing in Forward Transparent Bridge Mode 1 ms PCI Express Hot Reset Receiving Hot Reset Messages PCI_RST# 52 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.5.2.2 Hot Reset Hot Reset – Reverse Transparent Bridge Mode In Reverse Transparent Bridge mode, Hot Reset is received by the PEX 8114 on the PCI/PCI-X interface PCI_RST# ball as an input, and propagated downstream as an in-band message on the PCI Express link (using the TS1 Ordered-Sets). During the time that PCI_RST# is asserted, in-band Hot Reset commands are continuously transmitted across the PCI Express link. Hot Reset in Reverse Transparent Bridge mode is the equivalent to a Hot Reset in Forward Transparent Bridge mode received on the PCI Express interface. It causes the reset of internal registers and state machines, but not register Sticky bits. The PCI r3.0 requires that PCI_RST# be asserted for a minimum of 1 ms. Hot Reset also causes the serial EEPROM re-load, bus mode re-check, and clock frequency re-check. Figure 3-11 illustrates the timing relationship between PCI_RST# and transmitting in-band Hot Reset messages. Figure 3-11. PCI_RST# and Hot Reset Message Timing in Reverse Transparent Bridge Mode 1 ms PCI_RST# PCI Express Hot Reset Sending Hot Reset Messages ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 53 Clock and Reset 3.5.3 PLX Technology, Inc. Secondary Bus Reset Secondary Bus Reset is provided by the internal Bridge Control register Secondary Bus Reset bit (offset 3Ch[22]). This reset drives the bridge state machines to a known state, but does not reset internal registers. This reset also propagates a reset to downstream devices in the same manner as a Hot Reset. The Secondary Bus Reset is used to reset all downstream devices, without resetting the bridge. Secondary Bus Resets are sustained until the Secondary Bus Reset bit is cleared. This bit is set and cleared by software, using Configuration Write accesses. 3.5.3.1 Secondary Bus Reset – Forward Transparent Bridge Mode When operating in Forward Transparent Bridge mode, the PEX 8114 propagates a Secondary Bus Reset downstream by asserting the PCI_RST# signal on the PCI/PCI-X Bus. This occurs when software sets the Bridge Control register Secondary Bus Reset bit to 1. The PEX 8114 internal state machines are forced to initial states and internal transaction queues are flushed, but the internal registers are not reset. The minimum duration for PCI_RST# assertion is 1 ms. Figure 3-12 illustrates the timing relationship between Secondary Bus Reset and PCI_RST# in Forward Transparent Bridge mode. Figure 3-12. Secondary Bus Reset and PCI_RST# Timing in Forward Transparent Bridge Mode 1 ms Secondary Bus Reset PCI_RST# 3.5.3.2 Secondary Bus Reset – Reverse Transparent Bridge Mode When operating in Reverse Transparent Bridge mode, the PEX 8114 can reset downstream PCI Express devices, using the Secondary Bus Reset. When software sets the Bridge Control register Secondary Bus Reset bit to 1, a Hot Reset command is propagated downstream through an in-band message on the PCI Express link. The PEX 8114 internal state machines are forced to initial states and internal transaction queues are flushed, but the internal registers are not reset. Figure 3-13 illustrates the relationship between the Secondary Bus Reset bit and transmitting in-band Hot Reset messages. Figure 3-13. Secondary Bus Reset and Hot Reset Message Timing in Reverse Transparent Bridge Mode Secondary Bus Reset Hot Reset Messages 54 Sending Hot Reset Messages ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 3.6 Serial EEPROM Load Sequence Serial EEPROM Load Sequence Serial EEPROM data is loaded into the PEX 8114 after the following events: • Power-on reset • PEX_PERST# assertion • Hot Reset (Forward Transparent Bridge mode) • PCI_RST# assertion (Reverse Transparent Bridge mode) After the reset (Fundamental or Hot Reset) is de-asserted, the PEX 8114 reads data from the serial EEPROM, then writes it into the Configuration registers. This process takes approximately 8,000 PCI Bus Clock cycles. When a serial EEPROM is present, as indicated by the EE_PR# ball, the Serial EEPROM Controller is triggered to perform a serial EEPROM load after reset is removed. Because all internal registers initialize to default values after a Fundamental Reset, and most internal registers initialize to default values after a Hot Reset, the serial EEPROM data is loaded to restore registers to customized values. Consider the usage model wherein the serial EEPROM contents are modified after a Fundamental Reset. It is possible for a system to change the serial EEPROM contents through the Serial EEPROM Controller after a Fundamental Reset and restore the modified values with a load upon a Hot Reset. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 55 Clock and Reset PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 56 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 4 4.1 Data Path Internal Data Path Description The PEX 8114 supports Data transfers from the PCI-X port to the PCI Express port. The PCI-X port operates in PCI or PCI-X mode, at clock rates up to 133 MHz and 32- or 64-bit bus widths. The PCI Express port is four lanes wide, and can be configured as a 1-, 2-, or 4-lane port. The PEX 8114 internal data path is based upon a central RAM. which holds and orders all data transferred through the bridge in three separate linked lists including Posted, Non-Posted and Completion data. There is a separate, central 8-KB RAM for data flowing in each direction. All transactions are held within the RAM in a double store-and-forward method. Separate link lists for Posted and Non-Posted transactions, as well as Completions, share space within the RAM and all link list accesses to the internal RAM output are governed, according to PCI Express Ordering rules. At least 2 KB of the 8-KB RAM are dedicated to Completions. Completions can optionally require as much as 6 KB of memory, according to demand. The remainder of the RAM is used for Posted and Non-Posted requests, or remains empty. In addition to the central RAM, there are eight, 256-byte buffers in the PCI modules that track and combine the data (for up to eight concurrent Non-Posted PCI requests) with their Completion data when the Completion returns from the PCI Express link. (Refer to Chapter 7, “Bridge Operations,” for further details.) Additionally, the PCI interface modules include eight data-holding register sets that are dedicated to tracking the Completion progress of eight PCI Express requests on the PCI Bus. These registers hold information that uniquely identifies the Target location and data quantity requested, for up to eight PCI Express requests. As the PCI module’s state machines supply the data requested by the PCI Express device, these registers track progress toward Completion. After a transaction completes, the internal resources dedicated to that transaction are recovered and readied to service a new transaction. 4.2 PCI Express Credits PCI Express credits are issued according to the PCI Express requirements to manage the internal 8-KB central RAM and ensure that no internal memory linked list is overrun. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 57 Data Path 4.3 PLX Technology, Inc. Latency and Bandwidth The PEX 8114 can be configured as a PCI or PCI-X device at up to 133 MHz and 64-bit data bus on the PCI-X side, transacting data with the PCI Express port configured as a 1-, 2-, or 4-lane port (x1, x2, or x4, respectively). It is anticipated that from a bandwidth-balancing perspective, the PCI Express port configured as a 4-lane device matches well with the PCI-X side operating at 133 MHz and 64 bits. In this matched configuration, expect full bandwidth utilization on the PCI Express lanes and PCI-X Bus, with throughput limitations being the external PCI Express and PCI-X ports’ bandwidth capability and not the PEX 8114’s internal bandwidth. A 66-MHz, 64-bit PCI-X port should match a x2 PCI Express port. It is anticipated that the PEX 8114 does not limit the bandwidth of those transactions. Bandwidth is affected by many parameters, including but not limited to arbitration latency, cycle startup latency, Retries, packet sizes, and external endpoint latency. Adjust the parameters within the PEX 8114, based upon the PCI Express-to-PCI/PCI-X Bridge r1.0. 4.3.1 Data Flow-Through Latency When the PEX 8114 is configured as a PCI-X device, operating at 133-MHz clock frequency with a 64-bit wide data bus, and the PCI Express port is configured as a 4-lane link, expect approximately 300 ns latency through the PEX 8114 for Header-only packets and approximately 850 ns for Headers with 256-byte Data packets. This is the latency of data driven from PCI-X to PCI Express. This latency is measured from the frame drop on the PCI-X Bus, when data is driven into the PEX 8114, until the starting symbol of data TLP appears on the PCI Express lanes. Internal latency of data driven from PCI Express to PCI-X is similar. 4.3.2 PCI Transaction Initial Latency and Cycle Recovery Time In PCI mode, when the PEX 8114 is a Read Cycle Target, the PEX 8114 supplies data or Retries the Master Read request. There are eight Clock cycles from when the Master asserts PCI_FRAME# until the PEX 8114 signals a Retry or is ready to supply data. This equates to an initial target latency of 8 clocks. When the PEX 8114 is the Write Cycle Master, there is one Clock cycle from when the Master drives PCI_FRAME# until the PEX 8114 drives PCI_IRDY# ready to supply data. This cycle is the Address phase, required by the PCI r3.0. There are no initial wait states added by the PEX 8114. The PEX 8114 is a slow-decode device and supports fast back-to-back addressing. The PEX 8114 requires certain Clock cycles after completion of a previous transaction before it can participate in another transaction. This period is comprised of the Clock cycles from the last Data phase of the preceding transaction until PCI_FRAME# is asserted on a new transaction, and is referred to as transaction cycle recovery time. The cycle recover time from mastering a PCI-X transaction is 10 Clock cycles. 58 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 4.3.3 PCI-X Transaction Initial Latency and Cycle Recovery Time PCI-X Transaction Initial Latency and Cycle Recovery Time In PCI-X mode, when the PEX 8114 is a Read Transaction Target, there are seven Clock cycles from when the Master asserts PCI_FRAME# until the PEX 8114 drives a Split Response to the PCI-X Read request. When the PEX 8114 is a PCI-X Write Cycle Target, there are seven Clock cycles from when the Master asserts PCI_FRAME# until the PEX 8114 drives PCI_IRDY# ready to accept data. This equates to an initial Target latency of 2 clocks. When the PEX 8114 is a Write or Read Completion Master, there are three Clock cycles from when the PEX 8114 asserts PCI_FRAME# until the PEX 8114 asserts PCI_IRDY# indicating that it is ready to drive data. These three Clocks cycles are the Address, Attribute, and Turnaround cycles required by the PCI-X r2.0a. There are no initial wait states added by the PEX 8114. The PEX 8114 is a slow-decode device and supports fast back-to-back addressing. The PEX 8114 requires certain Clock cycles after the completion of a previous transaction, before it can participate in another transaction. This period is comprised of the Clock cycles from the last Data phase of the preceding transaction until PCI_FRAME# is asserted on a new transaction, and is referred to as transaction cycle recovery time. The cycle recover time for mastering a PCI cycle is seven Clock cycles. 4.3.4 Arbitration Latency Arbitration latency is the number of PCI Clock cycles required for the bridge to be granted the bus when it is waiting to make a transfer. This time can vary and is a function of the number of devices on the PCI Bus and each device’s demand for bus control. At a minimum, the bus can be parked on the bridge and in that case, the arbitration latency is 0 clocks. If the bus is not parked on the bridge and not being used by another device, the latency is 1 clock after the request. If the bus is being used by another Master and hidden arbitration is enabled, the arbitration latency is 1 clock after the other users relinquish the bus. If the bus is being used by another Master and hidden arbitration is not enabled, the arbitration latency is 2 clocks after the other users relinquish the bus. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 59 Data Path PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 60 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 5 5.1 Address Spaces Introduction This chapter discusses the PEX 8114 Address spaces. 5.2 Supported Address Spaces The PEX 8114 supports the following Address spaces: • Conventional PCI-compatible Configuration (00h to FFh; 256 bytes) • PCI Express Extended Configuration (100h to FFFh) • I/O (32-bit; includes ISA and VGA modes) • Memory-Mapped I/O (32-bit non-prefetchable) • Prefetchable memory (64-bit) • Base Address register (BAR) access to internal registers The first two spaces, used for accessing Configuration registers, are described in Chapter 6, “Configuration.” The PCI Express Extended Configuration space (100h to FFFh) is supported only in Forward Transparent Bridge mode, and BARs are used to access Extended Configuration space in Reverse Transparent Bridge mode. Configuration registers set up for I/O, Memory-Mapped and Prefetchable Memory Address spaces determine which transactions are forwarded from the primary bus to the secondary bus and from the secondary bus to the primary bus. The I/O and Memory ranges are defined by a set of Base and Limit registers in the Configuration Header. Transactions falling within the ranges defined by the Base and Limit registers are forwarded from the primary bus to the secondary bus. Transactions falling outside these ranges are forwarded from the secondary bus to the primary bus. Table 5-1 defines the primary and secondary interfaces for the two PEX 8114 Bridge modes. Table 5-1. Bridge Mode Primary and Secondary Interfaces Bridge Mode Primary Interface/Bus Secondary Interface/Bus Forward Transparent Bridge PCI Express PCI Reverse Transparent Bridge PCI PCI Express ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 61 Address Spaces 5.2.1 PLX Technology, Inc. I/O Space The I/O Address space determines whether to forward I/O Read or I/O Write transactions across the bridge. PCI Express uses the 32-bit Short Address Format (DWord-aligned) for I/O transactions. 5.2.1.1 Enable Bits The following Configuration register bits control the PEX 8114’s response to I/O transactions: • PCI Command register I/O Access Enable bit • PCI Command register Bus Master Enable bit • Bridge Control register ISA Enable bit • Bridge Control register VGA Enable bit Set the I/O Access Enable bit to allow I/O transactions to be forwarded downstream. When this bit is cleared to 0, all I/O transactions on the secondary bus are forwarded to the primary bus: • Forward Transparent Bridge mode – All primary interface I/O requests are completed with Unsupported Request (UR) status • Reverse Transparent Bridge mode – All I/O transactions are ignored (no PCI_DEVSEL# assertion) on the primary (PCI) bus Set the Bus Master Enable bit to allow I/O transactions to forward upstream. When this bit is cleared to 0: • Forward Transparent Bridge mode – All I/O transactions on the secondary (PCI) bus are ignored • Reverse Transparent Bridge mode – All I/O requests on the secondary (PCI Express) bus are completed with Unsupported Request (UR) status Setting the ISA Enable or VGA Enable bit affects I/O transactions. (Refer to Section 5.2.1.3, “ISA Mode,” and Section 5.2.1.4, “VGA Mode,” respectively, for details.) 5.2.1.2 I/O Base and Limit Registers The PEX 8114 supports the optional 32-bit I/O Addressed access. The following I/O Base and Limit Configuration registers are used to determine whether I/O transactions can be forwarded across the bridge: • I/O Base (upper four bits of the 8-bit register correspond to Address bits [15:12]) • I/O Base Upper 16 Bits (16-bit register corresponds to Address bits [31:16]) • I/O Limit (upper four bits of the 8-bit register correspond to Address bits [15:12]) • I/O Limit Upper 16 Bits (16-bit register corresponds to Address bits [31:16]) The I/O Base address consists of one 8-bit register and one 16-bit register. The upper four bits of the 8-bit register define bits [15:12] of the I/O Base address. The lower four bits of the 8-bit register determine the I/O address capability of this device. The I/O Base Upper 16 Bits register define bits [31:16] of the I/O Base address. The I/O Limit address consists of one 8-bit register and one 16-bit register. The upper four bits of the 8-bit register define bits [15:12] of the I/O limit. The lower four bits of the 8-bit register determine the I/O address capability of this device, and reflect the value of the same field in the I/O Base register. The I/O Limit Upper 16 Bits register defines bits [31:16] of the I/O Limit address. Because Address bits [11:0] are not included in Address Space decoding, the I/O Address range has a granularity of 4 KB, and is always aligned to a 4-KB Address Boundary space. The maximum I/O range is 4 GB. 62 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 I/O Space I/O transactions on the primary bus that fall within the range defined by the Base and Limit addresses are forwarded downstream to the secondary bus. I/O transactions on the secondary bus that are within the range are ignored. I/O transactions on the primary bus that do not fall within the range defined by the Base and Limit addresses are ignored. I/O transactions on the secondary bus that do not fall within the range are forwarded upstream to the primary bus. Figure 5-1 illustrates I/O forwarding. When the I/O Base address specified by the I/O Base and I/O Base Upper 16 Bits registers have a value greater than the I/O Limit address specified by the I/O Limit and I/O Limit Upper 16 Bits registers, the I/O range is disabled. In this case, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. Figure 5-1. I/O Forwarding Downstream Upstream Primary Bus Secondary Bus I/O Limit 4 KB Multiple I/O Base I/O Address Space ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 63 Address Spaces 5.2.1.3 PLX Technology, Inc. ISA Mode The Bridge Control register ISA Enable bit supports I/O forwarding in systems that include an ISA Bus. The ISA Enable bit affects I/O addresses within the range defined by the I/O Base and I/O Limit registers, located within the first 64 KB of the I/O Address space. When the ISA Enable bit is set to 1, the bridge does not forward I/O transactions downstream on the primary bus, located within the top 768 bytes of each 1-KB block within the first 64 KB of Address space. Transactions in the lower 256 bytes of each 1-KB block are forwarded downstream. When the ISA Enable bit is cleared to 0, all addresses within the range defined by the I/O Base and I/O Limit registers are forwarded downstream. I/O transactions with addresses located above 64 KB are forwarded, according to the range defined by the I/O Base and I/O Limit registers. When the ISA Enable bit is set to 1, the bridge forwards I/O transactions upstream on the secondary bus, located within the top 768 bytes of each 1-KB block within the first 64 KB of Address space, when the address is within the range defined by the I/O Base and I/O Limit registers. All other transactions on the secondary bus are forwarded upstream if they fall outside the range defined by the I/O Base and I/O Limit registers. When the ISA Enable bit is cleared to 0, all secondary bus I/O addresses outside the range defined by the I/O Base and I/O Limit registers are forwarded upstream. As with all upstream I/O transactions, the PCI Command register Bus Master Enable bit must be set to enable upstream forwarding. Figure 5-2 illustrates I/O forwarding with the ISA Enable bit set. Figure 5-2. I/O Forwarding with ISA Enable Bit Set Downstream Primary Bus Upstream Secondary Bus 900h - BFFh 800h - 8FFh 500h - 7FFh 400h - 4FFh 100h - 3FFh 000h - 0FFh ISA I/O Address Space Example 64 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 5.2.1.4 I/O Space VGA Mode The Bridge Control register VGA Enable bit enables VGA Register accesses to forward downstream from the primary to secondary bus, independent of the I/O Base and I/O Limit registers. The Bridge Control register VGA 16-Bit Decode bit selects between 10- and 16-bit VGA I/O address decoding, and is applicable when the VGA Enable bit is set to 1. The VGA Enable and VGA 16-Bit Decode bits control the following VGA I/O addresses: • 10-bit VGA I/O addressing – Address bits [9:0]=3B0h through 3BBh, and 3C0h through 3DFh • 16-bit VGA I/O addressing – Address bits [15:0]=3B0h through 3BBh, and 3C0h through 3DFh These ranges only apply to the first 64 KB of I/O Address space. VGA Palette Snooping VGA Palette snooping is not supported by PCI Express-to-PCI bridges; however, the PEX 8114 supports VGA Palette snooping in Reverse Transparent Bridge mode. In Forward Transparent Bridge mode, the Bridge Control register VGA Enable bit determines whether VGA Palette accesses are forwarded from PCI Express-to-PCI. The PCI Command register VGA Palette Snoop bit is forced to 0 in Forward Transparent Bridge mode. The Bridge Control register VGA 16-Bit Decode bit selects between 10- and 16-bit VGA I/O Palette Snooping Address decoding, and is applicable when the VGA Palette Snoop bit is set to 1. The VGA Palette Snoop and VGA 16-Bit Decode bits control the following VGA I/O Palette Snoop addresses: • 10-bit VGA I/O addressing – Address bits [9:0]=3C6h, 3C8h, and 3C9h • 16-bit VGA I/O addressing – Address bits [15:0]=3C6h, 3C8h, and 3C9h The PEX 8114 supports the following three modes of VGA Palette snooping in Reverse Transparent Bridge mode: • Ignore VGA Palette accesses, when there are no graphic agents downstream that must snoop or respond to VGA Palette Access cycles (Writes or Reads) • Positively decode and forward VGA Palette Writes, when there are graphic agents downstream from the PEX 8114 that must snoop VGA Palette Writes (Reads are ignored) • Positively decode and forward VGA Palette Writes and Reads, when there are graphic agents downstream that must snoop or respond to VGA Palette Access cycles (Writes or Reads) The Bridge Control register VGA Enable bit and PCI Command register VGA Palette Snoop bit select the bridge response to VGA Palette accesses, as defined in Table 5-2. Table 5-2. Bridge Response to VGA Palette Accesses VGA Enable Bit (Offset 3Ch[19]) VGA Palette Snoop Bit (Offset 04h[5]) 0 0 Ignore all VGA Palette accesses 0 1 Positively decode VGA Palette Writes (ignore Reads) 1 X Positively decode VGA Palette Writes and Reads Bridge Response to VGA Palette Accesses Note: X is “Don’t Care.” ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 65 Address Spaces 5.2.2 PLX Technology, Inc. Memory-Mapped I/O Space The Memory-Mapped I/O Address space determines whether to forward Non-Prefetchable Memory Write or Read transactions across the bridge. Map devices with side effects during Reads, such as FIFOs, into this space. For PCI-to-PCI Express Reads, prefetching occurs in this space when Memory Read Line or Memory Read Line Multiple commands are issued on the PCI Bus. When the Memory Read Line command is used, the data quantity prefetched is determined by the Cache Line Size value. When a Memory Read Line Multiple is used, the data quantity prefetched is determined by the Cache Line Size field and Cache Line Prefetch Line Count bit (offsets 0Ch[7:0] and FA0h[4], respectively). For PCI-to-PCI Express transactions, the Prefetched data is flushed after the PCI device reading the data terminates its first successful Read transaction during which it receives data. For PCI-X-to-PCI Express Reads, the number of bytes to read is determined by the transaction size requested in the PCI-X attributes. For PCI Express-to-PCI or PCI-X Reads, the number of bytes to read is determined by the Memory Read Request TLP. Transactions that are forwarded using this Address space are limited to a 32-bit range. 5.2.2.1 Enable Bits The following Configuration register bits control the PEX 8114’s response to Memory-Mapped I/O transactions: • PCI Command register Memory Access Enable bit • PCI Command register Bus Master Enable bit Set the Memory Access Enable bit to allow Memory transactions to forward downstream. When this bit is cleared to 0, all Memory request transactions on the secondary bus are forwarded to the primary bus: • Forward Transparent Bridge mode – All Non-Posted Memory requests are completed with an Unsupported Request (UR) status. Posted Write data is discarded. • Reverse Transparent Bridge mode – All Memory transactions are ignored on the primary (PCI) bus. Set the Bus Master Enable bit to allow Memory transactions to forward upstream. When this bit is cleared: • Forward Transparent Bridge mode – Memory Request transactions on the secondary (PCI) bus are ignored. • Reverse Transparent Bridge mode – All Non-Posted Memory requests on the secondary (PCI Express) bus are completed with a UR status. Posted Write data is discarded. 66 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 5.2.2.2 Memory-Mapped I/O Space Memory Base and Limit Registers The following Memory Base and Limit Configuration registers are used to determine whether to forward Memory-Mapped I/O transactions across the bridge: • Memory Base (bits [15:4] of the 16-bit register correspond to Address bits [31:20]) • Memory Limit (bits [31:20] of the 16-bit register correspond to Address bits [31:20]) Memory Base register bits [15:4] define Memory-Mapped I/O Base Address bits [31:20]. Memory Limit register bits [31:20] define Memory-Mapped I/O Limit bits [31:20]. Bits [3:0] of both registers are hardwired to 0h. Because Address bits [19:0] are not included in the Address Space decoding, the Memory-Mapped I/O Address range has a granularity of 1 MB, and is always aligned to a 1-MB Address Boundary space. The maximum Memory-Mapped I/O range is 4 GB. Memory transactions that fall within the range defined by the Memory Base and Memory Limit are forwarded downstream from the primary to secondary bus, and Memory transactions on the secondary bus that are within the range are ignored. Memory transactions that do not fall within the range defined by the Memory Base and Memory Limit registers are ignored on the primary bus, and forwarded upstream from the secondary bus. Figure 5-3 illustrates Memory-Mapped I/O forwarding. When the Memory Base is programmed with a value greater than the Memory Limit, the Memory-Mapped I/O range is disabled. In this case, all Memory transaction forwarding is determined by the Prefetchable Memory Base and Prefetchable Memory Limit registers, described in the following section. Figure 5-3. Memory-Mapped I/O Forwarding Downstream Primary Bus Upstream Secondary Bus Memory Limit 1 MB Multiple Memory Base Memory-Mapped I/O Address Space ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 67 Address Spaces 5.2.3 PLX Technology, Inc. Prefetchable Space The Prefetchable Address space determines whether to forward Prefetchable Memory Write or Read transactions across the bridge. Map devices, without side effects during Reads, into this space. For PCI-to-PCI Express Reads, prefetching occurs in this space for all Memory Read commands issued on the PCI Bus, as defined in Table 5-3. For PCI Express-to-PCI, PCI-X, or PCI-X-to-PCI Express Reads, the number of bytes to read is determined by the Memory Read request. Therefore, prefetching does not occur. Table 5-3. PCI-to-PCI Express Read Prefetching Command 5.2.3.1 Prefetch Memory Read (MemRd) The PEX 8114 prefetches the number of bytes indicated in the Prefetch register Prefetch Space Count field (offset FA4h[13:8]). Memory Read Line (MemRdLine) The PEX 8114 prefetches the number of bytes indicated in the Cache Line Size (offset 0Ch[7:0]). Memory Read Line Multiple (MemRdLineMult) The PEX 8114 prefetches 1 or 2 Cache Lines, as indicated in the Cache Line Prefetch Line Count bit (offset FA0h[4]). Each line contains the number of bytes indicated in the Cache Line Size, up to a maximum of 128 bytes. Enable Bits The Prefetchable space responds to the Enable bits, as described in Section 5.2.2.1, “Enable Bits.” 68 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 5.2.3.2 Prefetchable Space Prefetchable Memory Base and Limit Registers The following Prefetchable Memory Base and Limit Configuration registers are used to determine whether Prefetchable Memory transactions can be forwarded across the bridge: • Prefetchable Memory Base (bits [15:4] of the 16-bit register correspond to Address bits [31:20]) • Prefetchable Memory Base Upper 32 Bits (32-bit register corresponds to Address bits [63:32]) • Prefetchable Memory Limit (bits [31:20] of the 16-bit register correspond to Address bits [31:20]) • Prefetchable Memory Limit Upper 32 Bits (32-bit register corresponds to Address bits [63:32]) Prefetchable Memory Base register bits [15:4] define Prefetchable Memory Base Address bits [31:20]. Prefetchable Memory Limit register bits [31:20] define Prefetchable Memory Limit bits [31:20]. Bits [3:0] of both registers are hardwired to 1h, indicating 64-bit addressing. The default 64-bit addressing bit can be cleared to 0h during serial EEPROM load for systems that must run in 32-Bit Addressing mode. For 64-bit addressing, the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are also used to define the space. Because Address bits [19:0] are not included in the Address Space decoding, the Prefetchable Memory Address range has a granularity of 1 MB, and is always aligned to a 1-MB Address Boundary space. The maximum Prefetchable Memory range is 4 GB with 32-bit addressing, and 264 with 64-bit addressing. Memory transactions that fall within the range defined by the Prefetchable Memory Base and Prefetchable Memory Limit registers are forwarded downstream from the primary to secondary bus, and Memory transactions on the secondary bus that are within the range are ignored. Memory transactions that do not fall within the range defined by the Prefetchable Memory Base and Prefetchable Memory Limit registers are ignored on the primary bus and forwarded upstream from the secondary bus (provided they are not in the Address range defined by the Memory-Mapped I/O Address register set). Figure 5-4 illustrates Memory-Mapped I/O and Prefetchable Memory forwarding. When the Prefetchable Memory Base is programmed with a value greater than the Prefetchable Memory Limit, the Prefetchable Memory range is disabled. In this case, all Memory transaction forwarding is determined by the I/O Base and I/O Limit registers. All four Prefetchable Base and Limit registers must be considered when disabling the Prefetchable Memory range. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 69 Address Spaces PLX Technology, Inc. Figure 5-4. Memory-Mapped I/O and Prefetchable Memory Forwarding Downstream Primary Bus Upstream Secondary Bus DAC DAC Prefetchable Memory Limit 1 MB Multiple DAC DAC 4-GB Address Boundary Space SAC SAC Prefetchable Memory Base SAC SAC Memory-Mapped I/O Limit SAC 1 MB Multiple SAC Memory-Mapped I/O Base SAC SAC Prefetchable Memory and Memory-Mapped I/O Space SAC = Single Address Cycle DAC = Dual Address Cycle 70 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 5.2.3.3 Prefetchable Space 64-Bit Addressing Unlike Memory-Mapped I/O memory that must reside below the 4-GB Address Boundary space, Prefetchable memory can reside below, above, or span the 4-GB Address Boundary space. Memory locations above the 4-GB Address Boundary space must be accessed using 64-bit addressing. PCI Express Memory transactions that use the Short Address (32-bit) format can target the Non-Prefetchable Memory space, or a Prefetchable Memory window located below the 4-GB Address Boundary space. PCI Express Memory transactions that use the Long Address (64-bit) format can target locations anywhere in 64-bit Memory space. PCI Memory transactions that use Single Address cycles can only target locations below the 4-GB Address Boundary space. PCI Memory transactions that use Dual Address cycles can target locations anywhere in 64-bit Memory space. The first Address phase of a Dual Address transaction contains the lower 32 bits of the address, and the second Address phase contains the upper 32 bits of the address. If the upper 32 bits of the address are 0, a Single Address transaction is performed. Forward Transparent Bridge Mode When the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both cleared to 0, addresses located above the 4-GB Address Boundary space are not supported. In Forward Transparent Bridge mode, if a PCI Express Memory transaction is detected with an address located above 4 GB, the transaction is completed with Unsupported Request status. All Dual Address transactions on the PCI Bus are forwarded upstream to the PCI Express interface. When the Prefetchable memory is located entirely above the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both set to non-zero values. If a PCI Express Memory transaction is detected with an address located below the 4-GB Address Boundary space, the transaction is completed with Unsupported Request status, and all Single Address transactions on the PCI Bus are forwarded upstream to the PCI Express interface (unless they fall within the Memory-Mapped I/O range). A PCI Express Memory transaction located above 4 GB, that falls within the range defined by the Prefetchable Memory Base, Prefetchable Memory Base Upper 32 Bits, Prefetchable Memory Limit, and Prefetchable Memory Limit Upper 32 Bits registers, is forwarded downstream and becomes a Dual Address cycle on the PCI Bus. If a Dual Address cycle is detected on the PCI Bus located outside the range defined by these registers, it is forwarded upstream to the PCI Express interface. If a PCI Express Memory transaction located above the 4-GB Address Boundary space does not fall within the range defined by these registers, it is completed with Unsupported Request status. If a PCI Dual Address cycle falls within the range determined by these registers, it is ignored. When the Prefetchable memory spans the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits register is cleared to 0, and the Prefetchable Memory Limit Upper 32 Bits register is set to a non-zero value. If a PCI Express Memory transaction is detected with an address located below 4 GB, and is greater than or equal to the Prefetchable Memory Base Address, the transaction is forwarded downstream. A Single Address transaction on the PCI Bus is forwarded upstream to the PCI Express interface if the address is less than the Prefetchable Memory Base Address. If a PCI Express Memory transaction located above 4 GB is less than or equal to the Prefetchable Memory Limit register, it is forwarded downstream to the PCI Bus as a Dual Address cycle. If a Dual Address cycle on the PCI Bus is less than or equal to the Prefetchable Memory Limit register, it is ignored. If a PCI Express Memory transaction located above 4 GB is greater than the Prefetchable Memory Limit register, it is completed with Unsupported Request status. If a Dual Address cycle on the PCI Bus is greater than the Prefetchable Memory Limit register, it is forwarded upstream to the PCI Express interface. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 71 Address Spaces PLX Technology, Inc. Reverse Transparent Bridge Mode When the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both cleared to 0, addresses located above the 4-GB Address Boundary space are not supported. In Reverse Transparent Bridge mode, if a Dual Address transaction on the PCI Bus is detected, the transaction is ignored. If a PCI Express Memory transaction is detected with an address located above the 4-GB Address Boundary space, it is forwarded upstream to the PCI Bus as a Dual Address cycle. When the Prefetchable memory is located entirely above the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits and Prefetchable Memory Limit Upper 32 Bits registers are both set to non-zero values. The PEX 8114 ignores all single address Memory transactions on the PCI Bus, and forwards all PCI Express Memory transactions with addresses located below the 4-GB Address Boundary space upstream to the PCI Bus (unless they fall within the Memory-Mapped I/O range). A Dual Address transaction on the PCI Bus that falls within the range defined by the Prefetchable Memory Base, Prefetchable Memory Base Upper 32 Bits, Prefetchable Memory Limit, and Prefetchable Memory Limit Upper 32 Bits registers is forwarded downstream to the PCI Express interface. If a PCI Express Memory transaction is located above the 4-GB Address Boundary space and falls outside the range defined by these registers, it is forwarded upstream to the PCI Bus as a Dual Address cycle. If a Dual Address transaction on the PCI Bus does not fall within the range defined by these registers, it is ignored. If a PCI Express Memory transaction located above 4 GB falls within the range defined by these registers, it is completed with Unsupported Request status. When the Prefetchable memory spans the 4-GB Address Boundary space, the Prefetchable Memory Base Upper 32 Bits register is cleared to 0, and the Prefetchable Memory Limit Upper 32 Bits register is set to a non-zero value. If a PCI Single Address cycle is greater than or equal to the Prefetchable Memory Base Address, the transaction is forwarded downstream to the PCI Express interface. If a PCI Express Memory transaction is detected with an address located below the 4-GB Address Boundary space, and is less than the Prefetchable Memory Base Address, the transaction is forwarded upstream to the PCI Bus. If a Dual Address PCI transaction is less than or equal to the Prefetchable Memory Limit register, it is forwarded downstream to the PCI Express interface. If a PCI Express Memory transaction located above the 4-GB Address Boundary space is less than or equal to the Prefetchable Memory Limit register, it is completed with Unsupported Request status. If a Dual Address PCI transaction is greater than the Prefetchable Memory Limit register, it is ignored. If a PCI Express Memory transaction located above the 4-GB Address Boundary space is greater than the Prefetchable Memory Limit register, it is forwarded upstream to the PCI Bus as a Dual Address cycle. 5.2.4 Base Address Register Addressing The Base Address Registers (BARs) provide Memory-Mapped access to internal Configuration registers. This method of accessing internal registers is used exclusively to access the PCI Express Extended register set when operating as a Reverse PCI bridge, which has no other method of accessing without access to the higher Configuration addresses. All accesses using the BARs return 1 DWord of data. The BARs do not affect data forwarding through the bridge that uses Memory I/O, Memory-Mapped, or Prefetchable Memory. The PEX 8114 defaults to a non-prefetchable 32-bit BAR access, using BAR0 and leaving BAR1 unused. The PEX 8114 can be configured by serial EEPROM to support 64-bit non-prefetchable BAR access, using both BAR0 and BAR1 to create a 64-bit BAR, by setting the Base Address 0 register Memory Map Type field (offset 10h[2:1]) to 10b. Addresses transmitted to the BAR window are linearly translated into register address accesses. The Nth location of the BAR maps to the Nth Configuration register. Access to BAR locations that do not contain registers corresponding to that address return UR in Forward Transparent Bridge mode and 0 in Reverse Transparent Bridge mode. For further details, refer to Chapter 6, “Configuration.” 72 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 6 6.1 Configuration Introduction Configuration requests are initiated by the Root Complex in a PCI Express system and by the PCI or PCI-X Host or Central Resource Function in a PCI system. All devices located within a PCI Express or PCI system include a Configuration space accessed using Configuration transactions to configure operational characteristics of the device. When the PEX 8114 operates as a Forward bridge, all configurations originate at the PCI Express Root Complex. The PEX 8114 is configured by the Root Complex. The PEX 8114 register set appears as a Type 1 PCI Express Bridge register set with a Device ID of 8114h and additional Device-Specific registers. The PCI Express Bridge register set is enumerated and configured by the BIOS according to PCI Express conventions. Configuration or changes to the additional Device-Specific registers is optional, because changes to the Device-Specific registers are not required to allow the PEX 8114 to function. PCI devices located downstream from the PEX 8114 are configured by the Root Complex through the PEX 8114. When the PEX 8114 operates as a Reverse bridge, all configurations originate at the PCI-X or PCI Host. The PCI-X Host configures the PEX 8114, using PCI transactions. The PCI-X Host also configures PCI Express devices, located downstream from the PEX 8114, by transmitting PCI transactions to the PEX 8114, which the bridge converts into PCI Express Configuration transactions and then forwards to the PCI Express devices downstream. In Reverse Transparent Bridge mode, the PEX 8114 register set appears as a Type 1 PCI Bridge register set with a Device ID of 8114h and additional Device-Specific registers. The PCI Bridge register set is enumerated and configured by the BIOS according to PCI Bridge conventions. Configuration or changes to the additional Device-Specific registers is optional, because changes to the Device-Specific registers are not required to allow the PEX 8114 to function. Type 0 Configuration transactions are used to access the internal PEX 8114 Configuration registers. When the PEX 8114 is configured as a Forward or Reverse bridge, Type 1 Configuration transactions are transmitted into the PEX 8114 to access devices downstream from the PEX 8114. These Type 1 configurations are converted to Type 0 transactions, if they are targeted to the device on the bus directly below the PEX 8114. If the transaction is a Target for a bus downstream from the bus located directly below the PEX 8114, the transaction is passed through the PEX 8114 as a Type 1 configuration. If the transaction is not targeted for the PEX 8114, or devices located downstream from the PEX 8114, the transaction is rejected. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 73 Configuration PLX Technology, Inc. The Configuration address is formatted as follows: PCI Express 31 24 23 19 18 Device Number Bus Number 16 15 Function Number 12 11 Reserved 8 7 Extended Register Address 2 1 Register Address 0 Reserved PCI Type 0 (At Initiator) 31 16 15 Single bit decoding of Device Number 11 10 Reserved 8 7 Function Number Register Number 2 1 0 0 0 2 1 0 0 0 2 1 0 0 1 PCI Type 0 (At Target) 31 11 10 8 7 Function Number Reserved Register Number PCI Type 1 31 24 23 Reserved 74 16 15 Bus Number 11 10 Device Number Function Number 8 7 Register Number ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 6.2 Type 0 Configuration Transactions Type 0 Configuration Transactions The PEX 8114 responds to Type 0 Configuration transactions on its primary bus that address the PEX 8114 Configuration space. A Type 0 Configuration transaction is used to configure the PEX 8114, and is not forwarded downstream to the secondary bus. The PEX 8114 ignores Type 0 Configuration transactions on its secondary bus. Type 0 Configuration transactions result in the transfer of 1 DWord. If Configuration Write data is poisoned, the data is discarded and a Non-Fatal Error message is generated, if enabled. 6.3 Type 1 Configuration Transactions Type 1 Configuration transactions are used for device configuration in a hierarchical bus system. Transparent bridges and switches are the only devices that respond to Type 1 Configuration transactions. Type 1 conversion to special cycles are not supported. When the PEX 8114 operates as a Type 1 Transparent bridge, Configuration transactions are used when the transaction is intended for a device residing on a bus other than the one that issued the Type 1 request. The Bus Number field in a Configuration transaction request specifies a unique bus in the hierarchy, on which the Transaction Target resides. The bridge compares the specified bus number with two PEX 8114 Configuration registers – Secondary Bus Number and Subordinate Bus Number – to determine whether to forward a Type 1 Configuration transaction across the bridge. When the primary interface receives a Type 1 Configuration transaction, the following tests are applied, in sequence, to the Bus Number field to determine how to handle the transaction: 1. When the Bus Number field is equal to the Secondary Bus Number register value, the PEX 8114 forwards the Configuration request to the secondary bus as a Type 0 Configuration transaction. 2. When the Bus Number field is not equal to the Secondary Bus Number register value, but is within the range of the Secondary Bus Number and Subordinate Bus Number (inclusive) registers, the Type 1 Configuration request is specifying a bus located behind the bridge. In this case, the PEX 8114 forwards the Configuration request to the secondary bus as a Type 1 Configuration transaction. 3. When the Bus Number field does not satisfy the above criteria, the Type 1 Configuration request is specifying a bus that is not located behind the bridge. In this case, the Configuration request is invalid. If the primary interface is PCI Express, a Completion with Unsupported Request (UR) status is returned. If the primary interface is PCI, the Configuration request is ignored, resulting in resulting in delivery of FFFF_FFFFh or a Target Abort. If the Bridge Control register Master Abort Mode bit is set (offset 3Ch[21]=1), the PEX 8114 replies to the PCI Requester’s follow-on Non-Posted requests with a Target Abort. If the Master Abort Mode bit is cleared (offset 3Ch[21]=0), the PEX 8114 replies to the PCI Requester’s follow-on Non-Posted requests with FFFF_FFFFh. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 75 Configuration 6.4 PLX Technology, Inc. Type 1-to-Type 0 Conversion The PEX 8114 performs a Type 1-to-Type 0 conversion when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. The PEX 8114 must convert the Type 1 Configuration transaction to Type 0, to allow the downstream device to respond to it. Type 1-to-Type 0 conversions are performed only in the downstream direction. The PEX 8114 generates Type 0 Configuration transactions only on the secondary interface. 6.4.1 Forward Transparent Bridge Mode The PEX 8114 forwards a Type 1 transaction on the PCI Express interface to a Type 0 transaction on the PCI Bus, if the Type 1 Configuration request Bus Number field is equal to the Secondary Bus Number register value. The PEX 8114 then performs the following steps on the secondary interface: 1. Clears Address bits AD[1:0] to 00b. 2. Derives Address bits AD[7:2] directly from the Configuration request Register Address field. 3. Derives Address bits AD[10:8] directly from the Configuration request Function Number field. 4. Clears Address bits AD[15:11] to 00h. 5. Decodes the Device Number field and sets a single Address bit within the range AD[31:16] during the Address phase. 6. Verifies that the Extended Register Address field in the Configuration request is 0h. If the value is non-zero, the PEX 8114 does not forward the transaction, and treats it as an Unsupported Request on the PCI Express interface, and a Received Master Abort on the PCI Bus. Type 1-to-Type 0 transactions are performed as Non-Posted transactions. 76 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 6.4.2 Reverse Transparent Bridge Mode Reverse Transparent Bridge Mode The PEX 8114 forwards a Type 1 transaction on the PCI Bus to a Type 0 transaction on the PCI Express interface, if the following are true during the PCI Address phase: • Address bits AD[1:0] are 01b. • The Type 1 Configuration request Bus Number field (AD[23:16]) is equal to the Secondary Bus Number register value. • The Bus command on PCI_C/BE[3:0]# (32-bit bus) or PCI_C/BE[7:0]# (64-bit bus) is a Configuration Write or Read. • The Type 1 Configuration request Device Number field is cleared (AD[15:11]=0h). If it is non-zero, the PEX 8114 ignores the transaction, resulting in a Master Abort. The PEX 8114 then creates a PCI Express Configuration request, according to the following: 1. Sets the request Type field to Configuration Type 0. 2. Derives the Register Address field [7:2] directly from the Configuration request Register Address field. 3. Clears the Extended Register Address field [11:8] to 0h. 4. Derives the Function Number field [18:16] directly from the Configuration request Function Number field. 5. Derives the Device Number field [23:19] directly from the Configuration request Device Number field (forced to 0h). 6. Derives the Bus Number field [31:24] directly from the Configuration request Bus Number field. Type 1-to-Type 0 transactions are performed as Non-Posted transactions. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 77 Configuration 6.5 PLX Technology, Inc. Type 1-to-Type 1 Forwarding Type 1-to-Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of bridges are used. When the PEX 8114 detects a Type 1 Configuration transaction intended for a PCI Bus downstream from the secondary bus, it forwards the transaction, unchanged, to the secondary bus. In this case, the Transaction Target does not reside on the PEX 8114’s secondary interface, but is located on a bus segment farther downstream. Ultimately, this transaction is converted to a Type 0 transaction by a downstream bridge. 6.5.1 Forward Transparent Bridge Mode The PEX 8114 forwards a Type 1 transaction on the PCI Express interface to a Type 1 transaction on the PCI Bus, if the following are true: • A Type 1 Configuration transaction is detected on the PCI Express interface • The value specified by the Bus Number field is within the range of Bus Numbers between the Secondary Bus Number (exclusive) and Subordinate Bus Number (inclusive) The PEX 8114 then performs the following steps on the secondary interface: 1. Generates Address bits AD[1:0] as 01b. 2. Generates PCI Register Number, Function Number, Device Number, and Bus Number directly from the PCI Express Configuration Request register Address, Function Number, Device Number, and Bus Number fields, respectively. 3. Generates Address bits AD[31:24] as 00h. 4. Verifies that the Extended Register Address field in the Configuration request is 0h. If the value is non-zero, the PEX 8114 does not forward the transaction, and returns a Completion with Unsupported Request status on the PCI Express interface, and a Received Master Abort on the PCI Bus. Type 1-to-Type 1 forwarding transactions are performed as Non-Posted transactions. 78 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 6.5.2 Reverse Transparent Bridge Mode Reverse Transparent Bridge Mode The PEX 8114 forwards a Type 1 transaction on the PCI Bus to a Type 1 transaction on the PCI Express interface, if the following are true during the PCI Address phase: • Address bits AD[1:0] are 01b. • The value specified by the Bus Number field is within the range of Bus Numbers between the Secondary Bus Number (exclusive) and Subordinate Bus Number (inclusive). • The Bus command on PCI_C/BE[3:0]# (32-bit bus) or PCI_C/BE[7:0]# (64-bit bus) is a Configuration Write or Read. The PEX 8114 then creates a PCI Express Configuration request, according to the following: 1. Sets the request Type field to Configuration Type 1. 2. Derives the Register Address field [7:2] directly from the Configuration request Register Address field. 3. Clears the Extended Register Address field [11:8] to 0h. 4. Derives the Function Number field [18:16] directly from the Configuration request Function Number field. 5. Derives the Device Number field [23:19] directly from the Configuration request Device Number field. 6. Derives the Bus Number field [31:24] directly from the Configuration request Bus Number field. Type 1-to-Type 1 forwarding transactions are performed as Non-Posted transactions. 6.6 PCI Express Enhanced Configuration Mechanism The PCI Express Enhanced Configuration Mechanism adds four additional bits to the Register Address field, thereby expanding the space to 4,096 bytes. The PEX 8114 forwards Configuration transactions only when the Extended Register Address bits are all 0. This prevents address aliasing on the PCI Bus that does not support Extended Register Addressing. When a Configuration transaction targets the PCI Bus and contains a non-zero value in the Extended Register Address field, the PEX 8114 treats the transaction as if it received a Master Abort on the PCI Bus. The PEX 8114 then performs the following steps: 1. Sets the appropriate status bits for the destination bus, as if the transaction executed and resulted in a Master Abort. 2. Generates a PCI Express Completion with Unsupported Request status. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 79 Configuration PLX Technology, Inc. 6.7 Configuration Retry Mechanism 6.7.1 Forward Transparent Bridge Mode Bridges must return a Completion for all Configuration requests that traverse the bridge from PCI Express-to-PCI prior to expiration of the Completion Timeout Timer in the Root Complex. This requires that bridges take ownership of all Configuration requests forwarded across the bridge. If the Configuration request to PCI successfully completes prior to the bridge Timer expiration, the bridge returns a Completion with Successful Status to PCI Express. If the Configuration request to PCI encounters an error condition prior to the bridge Timer expiration, the bridge returns an appropriate error Completion to PCI Express. If the Configuration request to PCI does not successfully complete or with an error prior to Timer expiration, the bridge returns a Completion with Configuration Retry Status (CRS) to the PCI Express interface. After the PEX 8114 returns a Completion with CRS to PCI Express, the PEX 8114 continues to allow the Configuration transaction to remain alive on the PCI Bus. The PCI r3.0 states that once a PCI Master detects a Target Retry, it must continue to Retry the transaction until at least 1 DWord is transferred. The PEX 8114 Retries the transaction until the transaction completes on the PCI Bus or until the PCI Express to PCI Retry Timer expires. When the Configuration transaction completes on the PCI Bus after the return of a Completion with CRS on the PCI Express interface, the PEX 8114 discards the Completion information. Bridges that implement this option are also required to implement the Device Control register Bridge Configuration Retry Enable bit [15]. If this bit is cleared, the bridge does not return a Completion with CRS on behalf of Configuration requests forwarded across the bridge. The lack of a Completion results in eventual Completion Timeout at the Root Complex. Bridges, by default, do not return CRS for Configuration requests to a PCI device located behind the bridge. This can result in lengthy completion delays that must be comprehended by the Completion Timeout value in the Root Complex. 6.7.2 Reverse Transparent Bridge Mode In Reverse Transparent Bridge mode, when the PEX 8114 detects a CRS, it resends the Configuration request to the PCI Express device to allow the configuration request to remain alive, and reset its Internal Timer. If the PEX 8114 is in PCI mode and the Internal Timer times out before receiving a CRS or Error message from the PCI Express device, the PEX 8114 replies with FFFF_FFFFh if the Bridge Control register Master Abort Mode bit is cleared (offset 3Ch[21]=0). Otherwise, it causes a Target Abort if the Master Abort Mode bit is set (offset 3Ch[21]=1). If the PEX 8114 is in PCI-X mode, it transmits a Split Completion with a Target Abort Error message. 80 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 6.8 Configuration Methods Configuration Methods The PEX 8114 supports the Standard Configuration methods and maintains several Device-Specific Configuration methods. The PEX 8114 supports Forward and Reverse Transparent Bridge modes. Each mode is slightly different from a configuration perspective. The basic configuration methods include: • PCI Express Extended Configuration cycles • PCI Configuration cycles • BAR0/1 Memory-Mapped configuration of Device-Specific registers • Address and Data Pointer method for register access The PCI Express Extended Configuration method provides a PCI Express r1.0a-compliant method for configuring PCI Express registers. The PCI Configuration method provides a PCI r3.0-compliant method for accessing PCI registers. The BAR0 and BAR1 configuration method provides 32- or 64-bit Memory-Mapped access to registers. This is typically used to access registers that cannot be accessed by PCI Express Extended or Conventional PCI configurations. In general, BAR0 and BAR1 point to 8 KB of Memory Cycle-Accessible Address space. This 8 KB of space is used to Write and Read registers within, or downstream from, the PEX 8114. The 8 KB of Memory-Mapped space accesses registers in a slightly different manner in Forward and Reverse Transparent Bridge modes. The differences are explained in the next section. The Address and Data Pointer method provides two registers within the Configuration space for Reverse Transparent Bridge mode. One register represents an address in the PCI/PCI Express hierarchy, the other is a data value register. By loading the Address register with a Target address, then writing or reading the Data register, a location in the Address space can be written or read. 6.8.1 Configuration Methods Intent and Variations Configuration register accesses must be supported in all primary operation modes. These modes include Forward and Reverse Transparent. Each supported Configuration method provides access to at least some of the Configuration registers. Certain Configuration methods provide access to Conventional PCI registers, while others provide easy access to Device-Specific registers. By providing a combination of configuration methods, the PEX 8114 allows Conventional PCI access to many registers and logical simple access to Device-Specific registers, as well as downstream device registers. Operation modes slightly vary; therefore, certain Configuration methods also vary. The following sections explain the basic capability differences. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 81 Configuration 6.8.2 PLX Technology, Inc. PCI Express Extended Configuration Method The PCI Express Extended Configuration method provides Forward Transparent bridges with access to the standard set of PCI Express registers. This configuration method provides PCI-SIG-compliant access to the PEX 8114 PCI-SIG-defined registers. It also provides access to PCI-SIG-compliant access to registers in downstream devices when the PEX 8114 is used in Forward Transparent Bridge mode. This method is, however, confined to accessing the PCI Express-defined registers and is not used to access the PEX 8114 Device-Specific registers. In Forward Transparent Bridge mode, Memory-Mapped access is supported to access Device-Specific PEX 8114 registers. Address and Data Pointer register access is not supported in Forward Transparent Bridge mode. Therefore, the PEX 8114 Device-Specific registers can only be accessed by Memory-Mapped access. 6.8.3 PCI Configuration Cycles PCI Configuration cycles are used in Reverse Transparent Bridge mode to access the standard 256-byte PCI-defined register space. This method provides Conventional PCI register access that functions with Conventional PCI BIOS; however, it does not provide access in the following: • Reverse Transparent Bridge mode to downstream devices’ PCI Express Extended registers • Reverse Transparent Bridge mode to downstream devices’ Device-Specific registers In Reverse Transparent Bridge mode, use the Memory-Mapped or Address and Data Pointer method to access the downstream devices’ PCI Express Extended registers or the Device-Specific registers. 6.8.4 BAR0/1 Device-Specific Register Memory-Mapped Configuration BAR0 and BAR1 are used to provide 32- or 64-bit Memory-Mapped access to the Device-Specific registers. The use of Memory-Mapped access is slightly different in Forward Transparent Bridge mode than it is in Reverse Transparent Bridge mode. • Forward Transparent Bridge mode – Memory-Mapped access provides access to PEX 8114 internal Device-Specific registers. • Reverse Transparent Bridge mode – Memory-Mapped access provides access to all PEX 8114 internal registers, as well as to downstream PCI Express device registers. This Memory-Mapped method allows PCI Hosts (which support only Conventional PCI Configuration registers) to access devices on the downstream PCI Express side of the bridge, using PCI Express Extended Configuration space. BAR0 and BAR1 Device-Specific Register Memory-Mapped configuration can be disabled by setting the Disable BAR0 bit (offset FA0h[7]). By default, this bit is cleared; however, it can be set by way of serial EEPROM load. When this bit is set, BAR0 is loaded with all zeros (0) at reset, and appears to the operating system as disabled. 82 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 6.8.5 Address and Data Pointer Configuration Method Address and Data Pointer Configuration Method In Reverse Transparent Bridge mode, the Address and Data Pointer Configuration method provides the PCI Host with access to all PEX 8114 extended registers, as well as all registers of PCI Express devices on links located downstream from the PEX 8114. Access to the Configuration registers through the Memory-Mapped or Address and Data Pointer Configuration method is intended; however, both methods cannot be used concurrently. Access to the Configuration registers by way of the Address and Data pointers, which were accessed by the BAR0/1 Memory-Map access (Double-Indirect access), results in undefined data. 6.8.6 Configuration Specifics This section details how Configuration cycles function in Forward and Reverse Transparent Bridge modes and defines the register Address ranges accessed by each cycle type. The three operational modes are described separately, and in each description a table is provided that defines the recommended method for accessing the register ranges, located within and downstream from the PEX 8114. Following the table of recommended access methods, the methods are described as they function in that mode. 6.8.6.1 Forward Transparent Bridge Mode In Forward Transparent Bridge mode, access to all registers located within and downstream from the PEX 8114 is provided according to Table 6-1. Table 6-1. Access to Registers during Forward Transparent Bridge Mode Target Register Type Register Location Intended Configuration Method PEX 8114 PCI Express-defined registers PEX 8114 registers 00h through 1C7h, FB4h through FFFh PCI Express Extended configuration PEX 8114 Device-Specific registers PEX 8114 registers FFFh to FB3h BAR0/1 Memory-Mapped configuration Downstream device PCI registers Downstream bus with register addresses 00h through FFh PCI Express Extended Configuration Accessing of PCI-defined registers – first 256 bytes Downstream device Device-Specific registers Downstream Device-Specific Not supported ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 83 Configuration PLX Technology, Inc. PCI Express Extended Configuration Access in Forward Transparent Bridge Mode In Forward Transparent Bridge mode (as in all other modes), the PCI Express Extended Configuration method functions, as described in the PCI Express r1.0a, and as previously described. The PEX 8114 makes no non-standard modifications to the standard PCI Express Extended Configuration method. Forward Transparent Memory-Mapped BAR0/1 Access to Internal Registers In Forward Transparent Bridge mode, BAR0 and BAR1 are used to provide 32- or 64-bit MemoryMapped access to internal Configuration registers. When BAR0 and BAR1 are enumerated according to PCI convention and the bridge operation description herein, access to a 4-KB Memory-Mapped window into the Configuration registers is provided. The 4-KB window provides access to all PCI Express Extended register addresses. The Memory-Mapped window locations are linearly mapped to Configuration register space, according to the following equation: for N = 0 through 4 KB-1; Memory-Mapped address BASE+N access register N All internal registers can be accessed through Memory-Mapped access in Forward Transparent Bridge mode. 6.8.6.2 Reverse Transparent Bridge Mode In Reverse Transparent Bridge mode, access to all registers located within and downstream from the PEX 8114 is provided according to Table 6-2. Table 6-2. Access to Registers during Reverse Transparent Bridge Mode Target Register Type Register Location Intended Configuration Method PEX 8114 PCI-defined registers PEX 8114 registers 00h through FFh Conventional PCI configuration PEX 8114 PCI and Device-Specific registers PEX 8114 registers 100h through FFFh BAR0/1 Memory-Mapped configuration Address and Data Pointer configuration Downstream device PCI Type 0 Bridge register set from register 00h through FFh for enumeration Downstream bus with register addresses 00h through FFh Conventional PCI configuration Downstream device PCI Express Extended registers PCI Express Extended registers (includes registers 100h through FFFh) BAR0/1 Memory-Mapped configuration Address and Data Pointer configuration Downstream device Device-Specific registers Downstream Device-Specific BAR0/1 Memory-Mapped configuration Address and Data Pointer configuration 84 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Configuration Specifics Conventional PCI Configuration Access In Reverse Transparent Bridge mode, the Conventional PCI configuration method functions, as described in the PCI r3.0, and as previously described. The PEX 8114 makes no non-standard modifications to the PCI Configuration method. Using the PCI Configuration method, accesses can be made to the PEX 8114 standard 256 bytes of PCI register space and the first 256 bytes of any downstream PCI Express device located on links downstream from the PEX 8114. Because of the limitation of having access to only the first 256-byte offsets of the 4-KB Extended Register space of the downstream PCI Express device, an extended Memory-Mapped method is used to access the additional PCI Express registers of the downstream devices. The extended Memory-Mapped access method is described in the next section. Reverse Transparent Memory-Mapped BAR0/1 Access to Internal Extended Registers and Downstream Device Registers In Reverse Transparent Bridge mode, BAR0 and BAR1 are used to provide 32- or 64-bit Memory-Mapped access to the PEX 8114 internal Configuration registers and 4-KB PCI Express Extended Configuration register space of PCI Express devices on link(s) located downstream from the PEX 8114. When BAR0 and BAR1 are enumerated, according to PCI convention and according to the bridge operation description herein, access is allowed to an 8-KB Memory-Mapped window into the Configuration registers of a device in the hierarchy that originates at the PEX 8114. The 8-KB window provides access to all PEX 8114 PCI Express Extended register addresses and the PCI Express Extended Address space of all downstream PCI Express devices. The lower 4 KB of Memory-Mapped space, locations 0 through 4 KB-1 (FFFh), is a 4-KB access window into Configuration space that allows writing and reading of registers. The Memory-Mapped location at 4 KB (1000h) is a pointer to a register set on the bus hierarchy, which indicates the start location in the access window. The pointer’s contents create an address, defined in Table 6-3. When a PEX 8114 internal register is accessed, the Memory-Mapped Access cycle causes an internal register Read. When the register accessed is in a device located downstream from the PEX 8114, the Memory-Mapped Access cycle is converted to a Configuration access, which is transmitted down the link. The Memory-Mapped window is linearly mapped to the Configuration Register space of the register set pointed to by the pointer, according to the following equation: for N = 0: 4 KB-1; Memory-Mapped address BASE+N access register N Set the Configuration Enable bit to 1, to enable downstream Memory-Mapped accesses. All PEX 8114 internal registers and downstream PCI Express devices can be accessed through the MemoryMapped method. Table 6-3. 31 30 Reverse Transparent Configuration Address Pointer at Memory-Mapped Location 1000h 28 27 20 19 15 14 12 11 0 | | | | | | | | | | | --------------------- Forced to 0 | | | | ----------------------------------------------- Function Number [2:0] | | | | | | -------------------------------------------------------------------------------------------------------- Not Used ------------------------------------------------------------- Device Number [4:0] ------------------------------------------------------------------------------------ Bus Number [7:0] --------------------------------------------------------------------------------------------------------------- Configuration Enable ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 85 Configuration PLX Technology, Inc. Reverse Transparent Address and Data Pointer Register Access to Internal and Extended Registers and Downstream Device Registers In Reverse Transparent Bridge mode, two registers in PEX 8114 Configuration space provide indirect access into any Configuration register in the PEX 8114 or any PCI Express device located downstream from the PEX 8114. The Address pointer register is a 32-bit register, located at offset F8h. This register points to the address of a unique register located within or downstream from the PEX 8114. The Address pointer bits are defined in Table 6-4. The Data register is a 32-bit register located at offset FCh. When this register is written or read, the 32-bit register value pointed to by the address pointer is written or read. Set the Configuration Enable bit to 1 to enable Address and Data Pointer accesses. When a PEX 8114 internal register is accessed using the Address and Data Pointer Access cycle, the PEX 8114 executes an internal register access. When the register accessed is in a device located downstream from the PEX 8114, the Address and Data Pointer Access cycle is converted to a Configuration access, which is transmitted down the link. All internal PEX 8114 registers and downstream PCI Express devices can be accessed through the Address and Data Pointer method in Reverse Transparent Bridge mode. Table 6-4. 31 30 Reverse Transparent Configuration Address Pointer at Offset F8h 26 25 16 15 8 7 3 2 0 | | | | | | | | | | | ----- Function Number [2:0] | | | | | | | ------------------------------------------ Bus Number [7:0] | | | | -------------------------------------------------------------------------- Register DWord Address | ---------------------------------------------------------------------------------------------------- Reserved -------------------- Device Number [4:0] [9:0] (32-bit access; LSBs = 00b) --------------------------------------------------------------------------------------------------------------- Configuration Enable 86 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 7 7.1 Bridge Operations Introduction The PEX 8114 supports PCI Express transaction bridging to a PCI Bus operating in PCI or PCI-X mode. To simplify the descriptions, the PEX 8114 operational description is divided into the following types: • PCI-to-PCI Express Transactions • PCI-X-to-PCI Express Transactions • PCI Express-to-PCI Transactions • PCI Express-to-PCI-X Transactions The following sections discuss these transactions. Transaction transfer failures and general compliance are also discussed. 7.2 General Compliance The PEX 8114 complies with the following specifications for the listed processes and modes: • PCI r3.0 – PCI mode • PCI-X r1.0b or PCI-X r2.0a – PCI-X mode • PCI Express r1.0a – PCI Express port • PCI Express-to-PCI/PCI-X Bridge r1.0 – PCI and PCI Express Transaction Ordering rules ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 87 Bridge Operations 7.3 PLX Technology, Inc. PCI-to-PCI Express Transactions When a PCI device attempts a Write from the PCI Bus to the PCI Express interface, the PEX 8114 translates PCI Burst Write transactions into PCI Express data TLPs. In the most basic transaction, the PEX 8114 receives a Data burst on the PCI Bus and transfers the data into a PCI Express TLP. 7.3.1 PCI-to-PCI Express Flow Control The PEX 8114 ensures that the internal resources for storing data are not overrun. If an internal data storage resource is full, or approaching full in certain cases, the PEX 8114 issues Retries to all new Request transactions and only accepts Completions or requests of types without depleted resources. 7.3.2 PCI-to-PCI Express – PCI Posted Write Requests When servicing Posted Writes, no Completion information is returned to the PCI device that originated the transaction, and when the TLP is transmitted to the PCI Express link, the transaction is considered complete. Table 7-1 defines PCI Posted Write requests and the resultant PCI Express transactions created in response to the Posted Write. Table 7-1. PCI Posted Write Requests Initial Posted PCI Transactions 88 Resultant PCI Express Transaction Interrupt ACK Not supported Special Cycle Not supported Dual Address Cycle MWr TLP, up to Maximum Packet Size; type=00000b, fmt=11b Memory Write MWr TLP, up to Maximum Packet Size; type=00000b, fmt=1Xb Memory Write and Invalidate MWr TLP, up to Maximum Packet Size; type=00000b, fmt=1Xb ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.3.3 PCI-to-PCI Express – PCI Non-Posted Requests PCI-to-PCI Express – PCI Non-Posted Requests On Non-Posted PCI transactions, the PEX 8114 issues a Retry to the PCI originator when it receives the first request. The Retry indicates that the Non-Posted transaction was not completed on the PCI Express port. In addition to transmitting the Retry in response to the first Non-Posted PCI request, the PEX 8114 also creates and issues a Non-Posted TLP on the PCI Express link. Table 7-2 defines all Non-Posted requests and their resultant PCI Express requests. Direct Non-Posted transactions to Prefetchable or Non-Prefetchable Memory space. Table 7-2. PCI Non-Posted Requests Initial Non-Posted PCI Transactions Resultant PCI Express Transaction I/O Write IOwr TLP; length=1; type=0010b, fmt=10b I/O Read IOrd TLP; length=1; type=0010b, fmt=00b Memory Read MemRd TLP, up to Prefetch Size; type=0000b, fmt=0Xb Configuration Write CfgWr0/1 TLP; length=1; type=00100b, fmt=10b Configuration Read CfgRd0/1 TLP; length=1; type=00100b, fmt=00b Configuration Type 1 Write CfgWr1 TLP; length=1; type=00100b, fmt=10b Configuration Type 1 Read CfgRd1 TLP; length=1; type=00100b, fmt=00b Dual Address Cycle fmt=01b for Memory Reads and Memory Writes Memory Read Line MemRd TLP, up to Cache Line Size; type=00000b, fmt=1Xb Memory Read Line Multiple One or more MemRd TLP, up to Cache Line Size; type=0000b, fmt=1Xb Note: “X” indicates “Don’t Care.” 7.3.4 PCI-to-PCI Express – PCI Non-Posted Transactions until PCI Express Completion Returns After the initial Non-Posted request that caused the resultant transaction is issued on the PCI Express interface, subsequent requests from the PCI device are Retried until the PEX 8114 detects that the PCI Express link transmitted a Completion TLP matching the request. The PEX 8114 supports up to eight parallel Non-Posted requests. If the internal state machines indicate that the link is down, and the Bridge Control register Master Abort Mode bit is set (offset 3Ch[21]=1), the PEX 8114 replies to the PCI Requester’s follow-on Non-Posted requests with a Target Abort. If the Master Abort Mode bit is cleared (offset 3Ch[21]=0), the PEX 8114 replies to the PCI Requester’s follow-on Non-Posted requests with FFFF_FFFFh. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 89 Bridge Operations 7.3.5 PLX Technology, Inc. PCI-to-PCI Express – PCI Requests Do Not Contain Predetermined Lengths PCI Read requests do not contain an indication of the quantity of data they require; however, the TLPs that the PEX 8114 issues to the PCI Express device must indicate Data request quantities. The PEX 8114 treats Memory Reads to Prefetchable space differently than it treats Memory Reads to Non-Prefetchable space, and differently than it treats Memory Read Lines and Memory Read Line Multiples. The PEX 8114 resolves the Data request quantity ambiguity, as discussed in the following sections. 7.3.5.1 Memory Read Requests to Non-Prefetchable Space When the PEX 8114 receives a Memory Read request to Non-Prefetchable Memory space, it generates a PCI Express Read request for 1 DWord, if the system is running a 32-bit bus, and 2 DWords, if the system is running a 64-bit bus. 7.3.5.2 Memory Read Requests to Prefetchable Space When the PEX 8114 receives a Memory Read Request to Prefetchable Memory space in PCI mode, it issues a Read request on the PCI Express interface for an amount of data that is determined by the Prefetch register Prefetch Space Count field (offset FA4h[13:8]) and the starting address of the request. The Prefetch Space Count field is not used in PCI-X mode because the Request size is provided in the PCI-X Read request. Use of the Prefetch Space Count field to determine Prefetch Size pertains only to PCI mode. The Prefetch Space Count field specifies the number of DWords to prefetch for Memory Reads originating on the PCI Bus that are forwarded to the PCI Express interface. Only Even values between 0 and 32 are allowed. When the PEX 8114 is configured as a Forward bridge, prefetching occurs for all Memory Reads of Prefetchable and Non-Prefetchable Memory space. This occurs because the BARs are not used for Memory Reads, making it impossible to determine whether the space is prefetchable. In Reverse Transparent Bridge mode, prefetching occurs only for Memory Reads that address Prefetchable Memory space. Prefetching is Quad-word aligned, in that data is prefetched to the end of a Quad-word boundary. The number of DWords prefetched is as follows: • PEX 8114 prefetches 2 DWords when the following conditions are met: – Prefetch Space Count field is cleared to 00h, and – PCI_AD0 or PCI_AD1 is High – PCI_REQ64# is asserted (Low) • PEX 8114 prefetches 1 DWord when the following conditions are met: – Prefetch Space Count field is cleared to 00h, and – PCI_AD0 or PCI_AD1 is High – PCI_REQ64# is de-asserted (High) • When the Prefetch Space Count field contains an Even value greater than 0 and PCI_AD2 is High, the number of Prefetched DWords is 1 DWord less than the value in the Prefetch Space Count field; otherwise, the number of DWords prefetched is equal to the value in the Prefetch Space Count field. Only Even values between 0 and 32 are allowed. Odd values provide unexpected results. 90 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.3.5.3 PCI-to-PCI Express Disposition of Unused Prefetched Data Memory Read Line or Memory Read Line Multiple When the Read request is a Memory Read Line or Memory Read Line Multiple, the TLP Read Request Size is determined by the Cache Line Prefetch Line Count and Cache Line Size. When a Memory Read Line command is issued, a single Cache Line of data is prefetched. The number of lines prefetched for a Memory Read Line Multiple command is one or two Cache Lines, and is controlled by the Cache Line Prefetch Line Count bit (offset FA0h[4]). The Cache Line Size is determined by the Miscellaneous Control register Cache Line Size field (offset 0Ch[7:0]), and can be 1, 2, 4, 8, 16, or 32 DWords. Regardless of the Cache Line Prefetch Line Count and Cache Line Size, the prefetched TLP can never be larger than 128 bytes. The PEX 8114 allows the Cache Line Size field to be written with any value; however, if they are written to with a value other than 1, 2, 4, 8, 16, or 32 DWords, they are treated as if the value was cleared to 0 during the calculation. When the Cache Line Size field is cleared to 00h, 1 DWord (if the system is running a 32-bit bus) or 2 DWords (if the system is running a 64-bit bus) are prefetched. When prefetching for a given Cache Line Size, the prefetching is done to the end of the Cache Line. This means that if the starting address of the Memory Read Line or Memory Read Line Multiple request is at the beginning of the Cache Line, then a full Cache Line of data is prefetched. If the starting address of the Memory Read Line or Memory Read Line Multiple request is not at the beginning of the Cache Line, some amount of data less than a full Cache Line is prefetched, such that data is prefetched up to the end of a Cache Line. When the Read request is a Memory Read Line Multiple and the Cache Line Prefetch Line Count bit is set, the bridge issues a PCI Express Memory Read TLP with a size such that data is prefetched up to the end of the next Cache Line, if the Cache Line Size is less than or equal to 16 DWords (64 bytes). This operation is executed in an attempt to prefetch data from the PCI Express endpoint. If the additional data (the data requested in an attempt to prefetch) remains unused, the bridge drops the data. 7.3.5.4 Credits The PEX 8114 power-on default settings in register offsets A00h, A04h, and A08h are values that advertise finite credits. 7.3.6 PCI-to-PCI Express Disposition of Unused Prefetched Data After the PCI Express device completes the request to the PEX 8114, the PEX 8114 completes one of the PCI device’s subsequent attempts to Read by supplying data until the PCI device: • Terminates the transaction normally, satisfying its need for data, –or– • Depletes the data that it transmitted from the PCI Express device If the PCI device terminates the Read, the PEX 8114 flushes the remaining data it prefetched from the PCI Express device. If the data is depleted by the PCI device’s Read, the PEX 8114 terminates the PCI transaction with a Disconnect-with-Data on the Data phase in which the last available data is read. The PEX 8114 does not store and combine data from TLPs in an attempt to support lengthening the PCI burst. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 91 Bridge Operations 7.3.7 PLX Technology, Inc. PCI-to-PCI Express Pending Transaction Count Limits The PEX 8114 is capable of accepting multiple Posted PCI Writes. Each Write is stored in the central RAM until it can be transmitted on the PCI Express link. Non-Posted transactions require Completion on the PCI Express side of the bridge, prior to completing the transaction on the PCI side of the bridge. When a Non-Posted transaction enters the PEX 8114, its context is saved until a PCI Express Completion with a matching Requester ID is received. Upon receipt of the Completion from the PCI Express interface, the Completion is relayed to the PCI Initiator, which completes the transaction. The transaction is defined as outstanding from the time that the bridge receives the initial PCI request until the bridge completes the transaction and returns it to the PCI Requester. Up to eight Non-Posted transactions can be outstanding at any given time. 7.3.8 PCI-to-PCI Express – PCI Write Transaction with Discontiguous Byte Enables PCI Express requires that all packet data beats, except the first and last, have all Byte Enables enabled. PCI has no such requirement. If the PCI data written to the PCI Express port disabled Byte Enables in the middle of a burst, the PEX 8114 continues to accept the PCI data and creates two or more TLPs, as necessary, to support long PCI bursts, while also honoring the PCI Express requirement for contiguously asserted bytes. 7.3.9 PCI-to-PCI Express – PCI Write Transactions Larger than Maximum Packet Size When a PCI Burst Write transaction is larger than the PCI Express Maximum Packet Size, the PEX 8114 creates two or more PCI Express TLPs, as necessary, to support long bursts, while also honoring the PCI Express Maximum Packet Size requirements. When a PCI Data burst is completed, the TLP is transmitted and no attempt is made to combine multiple PCI Burst Writes into a single TLP transaction. When the PEX 8114 PCI Express lanes cannot transmit PCI Express TLPs across the PCI Express interface because of posted credit depletion (which would result in the filling of 6-KB central memory within the bridge), the bridge starts issuing Retries on the PCI Bus to hold-off the PCI Bus initiator from sending additional data to the PEX 8114. 92 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.4 PCI-X-to-PCI Express Transactions PCI-X-to-PCI Express Transactions When a PCI-X device attempts a Write from the PCI-X Bus to the PCI Express lanes, the PEX 8114 translates PCI-X Burst transactions into PCI Express TLPs. In the most basic transaction, the PEX 8114 receives a Data burst on the PCI-X Bus and translates the data into a PCI Express TLP. The PCI-X protocol is more similar to PCI Express protocol than to PCI protocol. (That is, the PCI-X transaction size is included in the request and the PCI-X Bus supports Split Responses.) These two factors allow transactions from PCI-X-to-PCI Express to flow more efficiently than transactions from PCI-to-PCI Express. The following description of PCI-X transactions is similar to PCI transactions; however, it contains a few significant differences, as described in the following sections. 7.4.1 PCI-X-to-PCI Express Flow Control The PEX 8114 ensures that the internal resources for storing data are not overrun. If an internal data storage resource is full or approaching full in certain cases, the PEX 8114 issues Retries to all new request transactions and only accepts Completions or requests to types without depleted resources. There are several data buffers that must be managed and not allowed to overflow, including the eight PCI Completion buffers and internal 8-KB RAM. In general, the bridge tracks the outstanding data it requested and does not transmit more requests than it has space to receive Completions. There are two exceptions – Oversubscribe and Flood modes. In Oversubscribe mode, the PEX 8114 tracks the number of outstanding bytes requested and ensures that it limits the number to that allowed in the Upstream and Downstream Split Transaction Control register Split Transaction Commitment Limit fields (offsets 60h[31;16] and 64h[31;16], respectively). In Flood mode, the PEX 8114 accepts and forwards all Read requests. 7.4.2 PCI-X-to-PCI Express – PCI-X Posted Requests For Posted PCI-X Writes, no Completion information is returned to the PCI-X device that originated the transaction, and when the TLP is transmitted on the PCI Express link, the transaction is considered complete. Table 7-3 defines PCI-X Posted transactions and the resultant PCI Express transactions created in response to the Posted Write. Table 7-3. PCI-X Posted Requests Initial Posted PCI Transactions Resultant PCI Express Transaction Interrupt ACK Not supported Special Cycle Not supported Dual Address Cycle fmt=01b for Reads and 10b for Writes Memory Write MWr TLP, up to Maximum Packet Size; type=00000b, fmt=1Xb Memory Write Block MWr TLP, up to Maximum Packet Size; type=00000b, fmt=1Xb ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 93 Bridge Operations 7.4.3 PLX Technology, Inc. PCI-X-to-PCI Express – PCI-X Non-Posted Requests When the initial PCI-X request is a Non-Posted Write, the PEX 8114 completes the PCI-X transaction with a Completion message, indicating a successful or unsuccessful Completion following the Completion from PCI Express. If the Non-Posted request is a Read and the transaction data is successfully gathered, the Split Completion is accompanied by data. When servicing Non-Posted PCI-X transactions, the PEX 8114 issues a Split Response to the PCI-X originator when it receives the first request and creates and issues a Non-Posted TLP on the PCI Express link. When the PCI Express endpoint responds to the Non-Posted request with a Completion, a Split Completion is returned to the PCI-X Initiator. Non-Posted Reads return data along with the Completion status. Non-Posted Writes return a Completion with status only. There are no Retries and no subsequent attempts. Table 7-4 defines possible PCI-X Non-Posted transactions and the resultant PCI Express transaction. Table 7-4. PCI-X Non-Posted Requests Initial Non-Posted PCI-X Transactions Resultant PCI Express Transaction I/O Write IOwr TLP length=1; type=00000b fmt=10b I/O Read IOrd TLP length=1; type=00000b fmt=00b Memory Read DWord MemRd TLP length=1; type=00000b fmt=0Xb Configuration Write CfgWr0/1 TLP length=1; type=0010b fmt=10b Configuration Read CfgRd0/1 TLP length=1; type=0010b fmt=00b Configuration Type 1 Write CfgWr1 TLP; length=1; type=00100b, fmt=10b Configuration Type 1 Read CfgRd1 TLP; length=1; type=00100b, fmt=00b Dual Address Cycle fmt=01b Memory Read Block MemRd TLP length=up to maximum Read request; type=00000b fmt=0Xb Note: “X” indicates “Don’t Care.” 94 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.4.4 PCI-X-to-PCI Express – PCI-X Read Requests Larger than Maximum Read Request Size PCI-X-to-PCI Express – PCI-X Read Requests Larger than Maximum Read Request Size During a PCI-X-to-PCI Express Read request, the PCI-X Read request Byte Count is loaded into the PCI Express TLP Read request quantity, if the PCI-X Read request is less than the Maximum Read Request Size. If the Read request is larger than the PCI Express Maximum Read Request Size, the PEX 8114 issues multiple Read requests of Maximum Read Request Size or smaller, in the case of the last TLP to complete the total Request Size. Generation of multiple Read request TLPs is performed to honor the PCI Express Maximum Read Request Size and contiguous Byte Enable requirements, while supplying the entire data quantity requested by the PCI-X Requester. When the data is returned from the PCI Express device, it is returned in TLPs that are no larger than the Maximum Packet Size, nor larger than the maximum Read Completion Size. As TLPs arrive, they are aligned to the PCI-X Allowable Disconnect Boundary (ADB), and Writes with discontiguous Byte Enables are transmitted as Completions on the PCI-X Bus, followed by disconnects on the ADB until the original PCI-X Requester’s data request quantity is supplied. During long Data bursts, if the PCI Express Read Completion Boundary (RCB) is set to 64 bytes, the bridge must combine two 64-byte PCI Express packets into a single 128-byte PCI-X burst, to ensure that the PCI-X transfer ends on the PCI-X ADB boundary. The combining of the two 64-byte TLPs into a single 128-byte ADB is performed in parallel with transmission of the previous 128-byte burst, and is transmitted as a single 128-byte PCI-X burst, thereby maximizing the PCI-X Bus bandwidth. The PEX 8114 does not store and combine data from TLPs in an attempt to support lengthening the PCI burst length. 7.4.5 PCI-X-to-PCI Express – PCI-X Transfer Special Case This section documents the PCI-X transfer special case that exists when PCI-X Write requests are larger than the Maximum Packet Size, cross 4-KB Address Boundary spaces, or have discontiguous Byte Enables. When a PCI-X device issues Write requests that are larger than the Maximum Packet Size, if the Write Request burst crosses a 4-KB Address Boundary space or the data has internal discontiguous Byte Enables, the PEX 8114 must break up the transaction into two or more transactions, assign unique Transaction IDs, and store details about each transaction generated, to facilitate accounting for the transaction Completion. 7.4.6 PCI-X-to-PCI Express – PCI-X Transactions that Require Bridge to Take Ownership When the PCI-X transaction is broken into multiple PCI Express transactions, the PEX 8114 must ensure that all requested data is read. To track data from large requests that require multiple TLPs to generate, the PEX 8114 must track all transactions to completion. The PEX 8114 allows eight PCI-X Read Request transactions to be outstanding at any time. PCI-X Non-Posted Read transactions that are smaller than the Maximum Read Request Size, as well as PCI-X Read requests that do not cross a 4-KB Address Boundary space, without discontiguous Byte Enables, are not limited to eight outstanding transactions. Limiting the Read Request Size, as less than or equal to the Maximum Read Request Size, allows for higher performance. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 95 Bridge Operations 7.4.7 PLX Technology, Inc. PCI-X-to-PCI Express – PCI-X Writes with Discontiguous Byte Enables The PEX 8114 is capable of accepting multiple Posted PCI-X Writes. Each Write is stored in the central RAM until it can be transmitted on the PCI Express link. PCI Express requires that all packet data beats, except the first and last, have all Byte Enables enabled. PCI-X has no such requirement. If the PCI-X data has disabled Byte Enables in the middle of a burst, the PEX 8114 continues to accept the PCI-X data and creates two or more TLPs, as necessary, to support long PCI bursts, while also honoring the PCI Express requirement for contiguously asserted bytes. 7.4.8 PCI-X-to-PCI Express – PCI-X Writes Larger than Maximum Packet Size When a PCI-X Burst transaction is larger than the PCI Express Maximum Packet Size, the PEX 8114 creates two or more PCI Express TLPs, as necessary, to support long bursts, while also honoring the PCI Express Maximum Packet Size requirements. When a PCI-X Data burst is completed, the TLP is transmitted and no attempt is made to combine multiple small PCI-X Burst Writes into a single TLP transaction. When the PEX 8114 PCI Express lanes cannot transmit PCI Express TLPs across the PCI Express interface because of posted credit depletion (which would result in the filling of 6-KB central memory within the bridge), the bridge starts issuing Retries on the PCI Bus to hold-off the PCI Bus initiator from sending additional data to the PEX 8114. 96 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.5 PCI Express-to-PCI Transactions PCI Express-to-PCI Transactions In PCI mode, when a PCI Express device transmits a transaction from the PCI Express interface to the PEX 8114 PCI-X bus, the transaction is translated from a PCI Express TLP into a PCI Burst transaction. In the most basic transaction, the PEX 8114 receives a TLP on the PCI Express lanes and translates the data into one or more PCI bursts. 7.5.1 PCI Express-to-PCI Flow Control Credits for up to 6 KB of PCI Express Posted and Non-Posted transactions are issued. These transactions are queued, according to PCI Ordering Transaction rules in central memory, and are transmitted to the PCI-X modules as bandwidth allows, limited by the eight outstanding PCI transactions. Transmitting packets into the PCI Express side of the bridge is throttled by space remaining in the central RAM. The process of transmitting transactions onto the PCI Bus is throttled by the number of outstanding transactions transmitted to the PCI endpoints that did not complete. The PEX 8114 supports up to eight outstanding transactions on the PCI Bus. All transactions are driven through the bridge as quickly as possible, limited only by the PCI Express and PCI Bus bandwidths. 7.5.2 PCI Express-to-PCI – PCI Express Posted Transactions When servicing Posted transactions, no Completion information is returned to the PCI Express device that originated the transaction, and when the transaction is transmitted on the PCI Bus, the transaction is considered complete. Table 7-5 defines which PCI Express Posted transactions are supported and to which PCI transaction they are translated. Table 7-5. PCI Express Posted Transactions Initial PCI Express Posted Transaction Type Resultant PCI Transaction Memory Write PCI Memory Write. Message Request Messages that cause changes on the PCI side of the bridge are Interrupt messages, which are translated to INTA#. Internally, Power Management and error conditions can cause Error messages to generate to the PCI Express side of the bridge. Message Request with Payload Not supported ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 97 Bridge Operations 7.5.3 PLX Technology, Inc. PCI Express-to-PCI – PCI Express Non-Posted Transactions When servicing Non-Posted PCI Express transactions, the PEX 8114 accepts the PCI Express TLP and creates and issues a PCI request on the PCI Bus. The necessary data quantity is indicated in the TLP and the PEX 8114 executes as many transactions as required on the PCI Bus to Write or Read the requested data. After the PEX 8114 successfully transmits or receives all data, it issues a Completion TLP to the PCI Express original Requester. The PEX 8114 supports up to eight concurrent Non-Posted PCI requests. Table 7-6 defines the PCI Express Non-Posted requests and the resulting PCI transactions when the Non-Posted PCI Express request is received. Table 7-6. PCI Express Non-Posted Transactions Initial PCI Express Non-Posted Transaction Type 7.5.4 Resultant PCI Transaction I/O Write Request I/O Write I/O Read Request I/O Read Configuration Write Type 0 Configuration Write Type 0 Configuration Read Type 0 Configuration Read Type 0 Configuration Write Type 1 Configuration Write Type 1 Configuration Read Type 1 Configuration Read Type 1 Memory Read – Locked Not supported – returns a UR Memory Read Request PCI Memory Read, PCI Memory Read Line, or PCI Memory Read Line Multiple PCI Express-to-PCI – PCI Bus Retry Writes are serially processed on a first-come, first-served basis. Reads are attempted in parallel, that is, if one request receives a disconnect, the PEX 8114 attempts to gather data for another outstanding request, moving from request to request in an effort to complete as many transactions as possible, as soon as possible. If the Force Strong Ordering bit is set (offset FA0h[8]=1), after data is returned in response to a Read request, the PEX 8114 concentrates all requests on gathering the remaining data for that transaction until the transaction completes. By default, the bit is cleared at power-on reset. If the bit is set, only one outstanding Read is allowed at a time. All Posted and Non-Posted Write bursts on the PCI Bus cannot be larger than the PCI Express Maximum Packet Size. There is no internal combining of Write TLPs in an effort to increase the PCI Burst Size. 98 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.5.5 PCI Express-to-PCI Transaction Request Size PCI Express-to-PCI Transaction Request Size The PEX 8114 determines which type of PCI Read request to issue on the PCI Bus, based upon the size of the PCI Express Read request that the bridge receives. If a PCI Express Memory Read request enters the PEX 8114 Prefetchable Memory space, with a TLP length and starting address such that all requested data is within a single Cache Line and is less than an entire Cache Line, a Memory Read request is issued on the PCI Bus. If a PCI Express Memory Read request enters PEX 8114 Prefetchable Memory space, with a TLP length greater than or equal to the Cache Line Size, but less than two Cache Lines in size, the PEX 8114 issues a Memory Read Line request on the PCI Bus. When a PCI Express Memory Read request enters the PEX 8114’s Prefetchable Memory space, with a TLP length greater than or equal to two Cache Lines in size, the PEX 8114 issues a Memory Read Line Multiple request. Issuing of Memory Read Line Multiple requests can be disabled by clearing the Memory Read Line Multiple Enable bit. This method of determining whether to issue a Memory Read Line or Memory Read Line Multiple request applies only to PCI mode. In PCI-X mode, the Transaction Size is stated in the transaction and it is unnecessary to indicate the Transaction Size. 7.5.6 PCI Express-to-PCI Transaction Completion Size Read Completions are arranged according to the following description. If the data quantity requested in the initial PCI Express Read request is less than or equal to the size of the maximum Read Completion Size, the data is returned to the PCI Express Requester in a single TLP. If the data quantity requested in the initial PCI Express Read request is more than the maximum Read Completion Size, or if the Read crosses a 4-KB Address Boundary space, the Completion is constructed into more than one TLP. The TLPs are sized at the maximum Read Completion Size, except for the final TLP, which is sized to complete the remainder of the transaction. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 99 Bridge Operations 7.6 PLX Technology, Inc. PCI Express-to-PCI-X Transactions In PCI-X mode, when a PCI Express device attempts a transaction from the PCI Express interface to the PCI-X Bus, the PEX 8114 translates the PCI Express transaction TLP into a PCI-X Burst transaction. In the most basic transaction, the PEX 8114 receives a TLP on the PCI Express lanes and translates the data into one or more PCI-X bursts. Credits for up to 6 KB of PCI Express Posted and Non-Posted transactions are issued. These transactions are queued according to the PCI Ordering Transaction rules in central memory, and transmitted to the PCI-X modules, as bandwidth allows. 7.6.1 PCI Express-to-PCI-X Posted Writes For Posted Writes, typically including Memory Writes, no Completion information is returned to the PCI Express device that originated the transaction, and when the transaction is transmitted on the PCI-X Bus, the transaction is considered complete. If the PCI-X Bus is busy, the PEX 8114 can receive and retain many Posted PCI Express Write TLPs, limited only by the 6-KB central RAM’s capacity. These transactions are processed as quickly as possible, in the order received. Table 7-7 defines this process. Table 7-7. Posted Writes Initial PCI Express Posted Transaction Type 100 Resultant PCI Transaction Memory Write PCI Memory Write. Message Request Interrupt messages cause changes on the PCI side of the bridge, which are translated to IntA to IntD. Internally, Power Management and error conditions can cause Error messages to generate to PCI Express side of the bridge. Message Request with Payload Not supported ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.6.2 PCI Express-to-PCI-X Non-Posted Transactions PCI Express-to-PCI-X Non-Posted Transactions In the case of Non-Posted PCI Express transactions (which typically include Memory Reads and Configuration and I/O Writes and Reads), the PEX 8114 accepts the PCI Express TLP and creates and issues a PCI-X I/O or Configuration Write or Read request on the PCI-X Bus. 7.6.2.1 Non-Posted Writes When the transaction is a Write, the PEX 8114 is prepared to transfer the entire burst as a single transaction on the PCI-X Bus. 7.6.2.2 Non-Posted Writes and Reads When the Non-Posted PCI Express transaction is a Read request, the PEX 8114 issues a Read request on the PCI-X Bus, in an effort to fulfill the PCI Express Data request. The PCI-X Target of the request has the option of responding with a Split Completion or Immediate data – the PEX 8114 accepts either response: • If the PCI-X Target responds with a Split Response, the Target must complete the Split Response with a Split Completion, at least to the next ADB, at a later time. • If the PCI-X device replies to the PCI-X Read request with Immediate data, the PCI-X Target must continue supplying Immediate data, up to the next ADB. The PEX 8114 does not allow a device to respond with a single data disconnect, unless the device is prepared to respond with single data disconnects up to the next ADB or to the end of the transaction, whichever comes first. This requirement is supported by the PCI-X r1.0b and PCI-X r2.0a. After the PEX 8114 successfully transmits or receives all data, the PEX 8114 issues a Completion TLP to the PCI Express Requester. Table 7-8 defines PCI Express Non-Posted requests and the resultant PCI transactions when the Non-Posted PCI Express request is received. Table 7-8. Non-Posted Writes and Reads Initial PCI Express Non-Posted Transaction Type Resultant PCI Transaction Memory Read Request PCI-X Memory Read or Memory Read Line Multiple Memory Read – Locked Not supported – returns a UR I/O Write Request I/O Write I/O Read Request I/O Read Configuration Write Type 0 Configuration Write Type 0 Configuration Read Type 0 Configuration Read Type 0 Configuration Write Type 1 Configuration Write Type 1 or 0 Configuration Read Type 1 Configuration Read Type 1 or 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 101 Bridge Operations 7.6.2.3 PLX Technology, Inc. Transaction Concurrency The PEX 8114 supports up to eight Non-Posted PCI Express requests. Writes are serially processed on a first-come, first-served basis. Reads are attempted in parallel, that is, if one request receives a disconnect, the PEX 8114 attempts to gather data for another of the outstanding requests, moving from request to request in an effort to complete as many transactions as possible, as soon as possible. If the Force Strong Ordering bit is a value of 0 and then set (offset FA0h[8]=0, then 1), after data is returned in response to a Read request, the PEX 8114 concentrates all requests on gathering data to complete that transaction until the transaction completes. If the Force Strong Ordering bit is already set and then set again, only one outstanding Read is allowed at a time. All Posted and Non-Posted Write bursts on the PCI Bus can be no larger than the PCI Express Maximum Packet Size. There is no internal combining of Write TLPs in an effort to increase the PCI Burst Size. Read Completions are gathered from the PCI-X Bus as a single DWord Disconnect, Completions to the next ADB, or Completion of the entire requested data size. The Completion data is collected within the PEX 8114, then delivered to the PCI Express Requesters as TLP packets that are no larger than the Maximum Packet Size, until all data requested by the PCI Express device is satisfied. 102 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.7 Transaction Transfer Failures Transaction Transfer Failures The previously described transactions are the set of legal and expected transactions. Successful Data transfer is dependent upon the PCI-X and PCI Express devices connected to the PEX 8114 performing, as described in the PCI r3.0, PCI-X r2.0a, and PCI Express r1.0a. When a device fails to correctly perform, the transaction is likely to fail. These failures typically result in transaction timeouts and the setting of internal register bits. The PCI Express-to-PCI/PCI-X Bridge r1.0 anticipates most of the typical failures and specifies error handling procedures for error condition recovery. The PEX 8114 supports these error handling routines, recovers internal resources, and logs errors according to the specifications. For further details on error handling and recovery, refer to Chapter 8, “Error Handling,” and the PCI Express-to-PCI/PCI-X Bridge r1.0. The other side of this failure to flush a pending transaction from the bridge is that it is assumed that a transaction will not complete and quickly reclaim its internal buffers. To accommodate heavy traffic densities, the bridge has several selectable transaction timeout periods. These timeout periods are based upon PCI_CLK cycles and in PCI mode, can be selected as 210, 215, or 220 Clock cycles, or the timeout can be disabled. The following register bits are used to select these timeouts: • Bridge Control register Primary Discard Timer bit (offset 3Ch[24]) • Bridge Control register Secondary Discard Timer bit (offset 3Ch[25]) (discussed further in Section 7.7.1) • Disable Completion Timeout Timer (offset FA0h[5]) (discussed further in Section 7.7.2 and Section 7.7.4) • Enable Long Completion Timeout Timer (offset FA0h[6]) (discussed further in Section 7.7.2 and Section 7.7.4) Table 7-9 defines register bit Timer values as they apply to available timeouts. When Completions are not returned to the PEX 8114, or when the endpoint does not accept returned Completions held within the PEX 8114, the bridge’s internal resources remain reserved to those uncompleted transactions and cannot be used for future transactions. The following sections describe how the PEX 8114 controls slow or stalled transactions: • PCI Endpoint Fails to Retry Read Request • PCI-X Endpoint Fails to Transmit Split Completion • PCI-X Endpoint Allows Infinite Retries • PCI Express Endpoint Fails to Return Completion Data Table 7-9. Clock Cycle Timeout Period Selection Bridge Control Register Clock Cycle Timeout Disable Completion Timeout Timer (Offset FA0h[5]) Enable Long Completion Timeout Timer (Offset FA0h[6]) Primary Discard Timer (Offset 3Ch[24]) Secondary Discard Timer (Offset 3Ch[25]) Default 0 0 0 1 210 0 0 0 0 215 1 1 0 0 220 X X 0 1 No Timer (Disabled) X X 1 X Note: “X” indicates “Don’t Care.” ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 103 Bridge Operations 7.7.1 PLX Technology, Inc. PCI Endpoint Fails to Retry Read Request The Secondary Discard Timer monitors Completions located within the PEX 8114, waiting to return to the initial PCI Requester. This Timer applies in PCI mode, and only when the PCI device initiated the initial Read request. After the Completion returns from the PCI Express endpoint to the PEX 8114, if the original PCI Requester fails to Retry for the Read Completion, the data remains in the PEX 8114 and results in wasted resources. The Timer times Completions within the PEX 8114. If a Completion is not requested by the initial PCI Requester before the Secondary Discard Timer times out, the Completion is dropped and the PEX 8114 reclaims the internal resources. The Timer can be configured by the Bridge Control register Secondary Discard Timer bit to time out at 210 PCI_CLK clock periods when set (offset 3Ch[25]=1), or 215 PCI_CLK clock periods when cleared (offset 3Ch[25]=0). 7.7.2 PCI-X Endpoint Fails to Transmit Split Completion When the PEX 8114 receives and takes ownership of a PCI Express Read request, and successfully forwards that request to a PCI-X device and receives a Split Response, the PEX 8114 waits a specified length of time for a Split Completion from the PCI-X device. If that Split Completion fails to return within the specified time, the PEX 8114 reclaims its internal resources. Table 7-10 defines the three available Timer settings, selectable by way of the Enable Long Completion Timeout Timer and Disable Completion Timeout Timer bits (offset FA0h[6:5], respectively). Table 7-10. Timer Settings for Transmitting Split Completions Offset FA0h[6:5] 7.7.3 Timer Setting 00b 215 10b 220 PCI_CLK cycles timeout X1b No timeout PCI_CLK cycles timeout PCI-X Endpoint Allows Infinite Retries When the PEX 8114 attempts to master a PCI or PCI-X Read Request transaction onto the PCI-X Bus in response to a PCI Express endpoint Read request, it is expected that the PCI-X endpoint might not contain data that is immediately ready and can respond to the PEX 8114’s Read request with a Retry. In response to the Retry, the PEX 8114 re-attempts the Read request, and it is expected that a future Read attempt will be completed with data. If the endpoint infinitely replies to the PEX 8114 Read request with a Retry, the PEX 8114 terminates the transaction. To facilitate this, the number of Retries received for each Read request are counted. At which time, the PEX 8114 compares the value stored in the Maximum Read Cycle Value field (offset FA0h[26:16]). If the number of Retries received matches the number stored in the Maximum Read Cycle Value field, the Read request is dropped and the Retry Failure Status bit is set (offset FA0h[27]=1). If the Force Strong Ordering bit is cleared (offset FA0h[8]=0), the PEX 8114 attempts up to eight Read requests in a Round-Robin scheme. A Retry Count for each of the eight Read requests is maintained, and compared, as it takes its turn at the PCI Bus. 104 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 7.7.4 PCI Express Endpoint Fails to Return Completion Data PCI Express Endpoint Fails to Return Completion Data The PEX 8114 holds internal resources reserved to receive Completions. If the PCI Express endpoint responsible for a Completion fails to transmit a Completion, the PEX 8114’s internal resources are at risk of remaining reserved, waiting for a Completion that might never occur. The PEX 8114 contains an Internal Timer used to trigger the bridge to reclaim internal resources reserved for Completions that might never occur. Table 7-11 defines the three available Timer settings, selectable by way of the Enable Long Completion Timeout Timer and Disable Completion Timeout Timer bits (offset FA0h[6:5], respectively). When PCI Non-Posted requests and Completions from PCI Express-to-PCI are executed and no timeout is selected (offset FA0h[6:5]=X1b), the buffer holding Completions for the PCI requests are not automatically reclaimed. However, after 220 clocks transpire without a Completion, the Completion Buffer Timeout status bit for that buffer (offset F88h) is set to indicate that the buffer is reserved for an extremely late Completion. When the timeout setting is set to 215 or 220 (offset FA0h[6:5]=00b or 10b, respectively) and the Completion fails to return before the timeout, the buffer is reclaimed after the timeout and reused. If after a transaction times out, and the buffer is scheduled for reuse, and the PCI endpoint Retries the Read request for the transaction that timed out, the PEX 8114 returns a Target Abort or FFFF_FFFFh, as selected by the Bridge Control register Master Abort Mode bit (offset 3Ch[21]) to indicate that a timeout occurred to the PCI endpoint. Each buffer can timeout and be reclaimed three times. After three reclaims and four timeouts, the Completion Buffer Timeout Status bit for that buffer is set, to indicate that the buffer can no longer be reclaimed. When a buffer times out, if a user or operating system confirms that no stale Completions are pending, the buffer can be re-initialized by writing 1 to the offset F88h bit representing that buffer. There is a degree of risk involved in re-initializing buffers. If a stale Completion is pending, and the software is not aware of this, and the associated Completion Buffer Timeout Status bit is mistakenly cleared, the stale Completion can be mistaken for a Completion to a more-recent request, resulting in incorrect data being used for the Completion. If 32 PCI Read requests fail to complete by the PCI Express endpoint, all eight buffers timeout four times and all resources are consumed. To prevent a lockup condition, the PEX 8114 automatically clears the Completion Buffer Timeout Status bits for all eight registers, allowing it to continue to accept Non-Posted requests. If a lockup condition occurs, the PEX 8114 can no longer accept Non-Posted PCI-X requests, which precludes Configuration Writes. It therefore becomes impossible to clear the buffer timeouts after all buffers time out. Table 7-11. Timer Settings for Receiving Completions Offset FA0h[6:5] Timer Setting 00b 215 PCI_CLK cycles timeout 10b 220 PCI_CLK cycles timeout X1b No timeout Note: “X” indicates “Don’t Care.” ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 105 Bridge Operations PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 106 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 8 8.1 Error Handling Forward Transparent Bridge Error Handling For all errors detected by the bridge, the bridge sets the appropriate error status bit [both Conventional PCI/PCI-X Error bit(s) and PCI Express error status bit(s)], and generates an Error message on the PCI Express interface, if enabled. Each error condition has an error severity level programmable by software, and a corresponding Error message generated on the PCI Express interface. Four bits control PCI Express interface Error message generation: • PCI/PCI-X Command register SERR# Enable bit • PCI Express Device Control register Correctable Error Reporting Enable bit • PCI Express Device Control register Non-Fatal Error Reporting Enable bit • PCI Express Device Control register Fatal Error Reporting Enable bit ERR_COR messages are enabled for transmission if the Correctable Error Reporting Enable bit is set. ERR_NONFATAL messages are enabled for transmission if the SERR# Enable or Non-Fatal Error Reporting Enable bit is set. ERR_FATAL messages are enabled for transmission if the SERR# Enable or Fatal Error Reporting Enable bit is set. The Device Status register Correctable Error Detected, Non-Fatal Error Detected, and Fatal Error Detected status bits are set for the corresponding errors on the PCI Express interface, regardless of the Error Reporting Enable bit values. 8.1.1 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) This section describes error support for transactions that cross the bridge if the originating side is the PCI Express interface, and the destination interface is operating in Conventional PCI/PCI-X modes. If a Write Request or Read Completion is received with a Poisoned TLP, consider the entire Data Payload of the PCI Express transaction as corrupt. Parity is inverted for all Data phases when completing the transaction on the PCI/PCI-X Bus. If a TLP is received and an ECRC error is detected, consider the entire TLP as corrupt and not forwarded, but dropped by the bridge. Table 8-1 defines the translation a bridge must perform when forwarding a Non-Posted PCI Express request (Write or Read) to the PCI/PCI-X Bus, and the request is immediately completed on the PCI/ PCI-X Bus, normally or with an error condition. Table 8-1. Translation Bridge Action when Forwarding Non-Posted PCI Express Request to PCI/PCI-X Bus Immediate PCI/PCI-X Termination PCI Express Completion Status Data Transfer with Parity error (Non-Posted Writes) Unsupported Request Data Transfer with Parity error (Reads) Successful (Poisoned TLP) Master Abort Unsupported Request Target Abort Completer Abort ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 107 Error Handling 8.1.1.1 PLX Technology, Inc. Received Poisoned TLP When the PCI Express interface receives a Write Request or Read Completion with poisoned data, the following occurs: 1. PCI Status register Detected Parity Error bit is set. 2. PCI Status register Master Data Parity Error bit is set if the Poisoned TLP is a Read Completion and the PCI Command register Parity Error Response Enable bit is set. 3. Uncorrectable Error Status register Poisoned TLP Status bit is set. 4. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared and the First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Poisoned TLP Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared and the SERR# Enable bit is set. 8. Parity bit associated with each DWord of data on the PCI/PCI-X Bus is inverted. 9. When a Poisoned TLP Write Request is forwarded to the PCI/PCI-X Bus and the bridge detects PCI_PERR# asserted, the following occurs: – Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set – Secondary Uncorrectable Error Status register PERR# Assertion Detected bit is set – Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the First Error Pointer is inactive 10. No Error message is generated when a Poisoned TLP is forwarded to the PCI/PCI-X Bus with inverted parity and PCI_PERR# is detected asserted by the PCI/PCI-X Target device. 108 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.1.2 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) Received ECRC Error When a TLP is received and the bridge detects an ECRC error, the following occurs: 1. Transaction is dropped. 2. PCI Status register Detected Parity Error bit is set. 3. Uncorrectable Error Status register ECRC Error Status bit is set. 4. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register ECRC Error Mask bit is cleared and the First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register ECRC Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register ECRC Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 8.1.1.3 PCI Status register Signaled System Error bit is set if the Uncorrectable Error Mask register ECRC Error Mask bit is cleared and the SERR# Enable bit is set. PCI/PCI-X Uncorrectable Data Errors The following sections describe error handling when forwarding Non-Poisoned PCI Express transactions to the PCI/PCI-X Bus, and an Uncorrectable PCI/PCI-X error is detected. Posted Writes When the PEX 8114 detects PCI_PERR# asserted on the PCI/PCI-X secondary interface while forwarding a Non-Poisoned Posted Write transaction from the PCI Express interface, the following occurs: 1. Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. 2. Secondary Uncorrectable Error Status register PERR# Assertion Detected Status bit is set. 3. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable First Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. PCI Status register Signaled System Error bit is set if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. 7. After the error is detected, the remainder of the data is forwarded. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 109 Error Handling PLX Technology, Inc. Non-Posted Writes When the PEX 8114 detects PCI_PERR# asserted on the PCI/PCI-X secondary interface while forwarding a Non-Poisoned Non-Posted Write transaction from the PCI Express interface, the following occurs: 1. Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. 2. PCI Express Completion with Unsupported Request status is generated. 3. Secondary Uncorrectable Error Status register PERR# Assertion Detected Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. When the Target signals Split Response, the bridge terminates the transaction as it would for a Split Request that does not contain an error and takes no further action. If the returned Split Completion is a Split Completion Error message, the bridge returns a PCI Express Completion with Unsupported Request status to the Requester. 110 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) Immediate Reads When the PEX 8114 forwards a Read request (I/O, Memory, or Configuration) from the PCI Express interface and detects an Uncorrectable Data error on the secondary bus while receiving an Immediate or Split Response from the Completer, the following occurs: 1. Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. 2. Secondary Status register Secondary Detected Parity Error bit is set. 3. PCI_PERR# is asserted on the secondary interface if the Bridge Control register Secondary Parity Error Response Enable bit is set. 4. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. After detecting an Uncorrectable data error on the destination bus for an Immediate Read transaction, the PEX 8114 continues to fetch data until the Byte Count is satisfied or the Target ends the transaction. When the bridge creates the PCI Express Completion, it forwards the Completion with Successful Completion and poisons the TLP. For PCI-X, an Uncorrectable Data error on a Split Response does not affect handling of subsequent Split Completions. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 111 Error Handling PLX Technology, Inc. PCI-X Split Read Completions When the bridge forwards a Non-Poisoned Read Completion from PCI Express to PCI-X and detects PCI_PERR# asserted by the PCI-X Target, the following occurs: 1. Bridge continues to forward the remainder of the Split Completion. 2. Secondary Uncorrectable Error Status register PERR# Assertion Detected Status bit is set. 3. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. 8.1.1.4 PCI Status register Signaled System Error bit is set if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. PCI/PCI-X Address/Attribute Errors When the PEX 8114 forwards transactions from PCI Express to PCI/PCI-X, PCI Address errors are reported by SERR# Target assertion. When the PEX 8114 detects SERR# asserted, the following occurs: 1. Secondary Status register Secondary Received System Error bit is set. 2. Secondary Uncorrectable Error Status register SERR# Assertion Detected bit is set. 3. FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable First Error Pointer is inactive and the Secondary Uncorrectable Error Mask register SERR# Assertion Detected Mask bit is cleared. No Header is logged. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register SERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register SERR# Assertion Detected Mask bit is cleared –or– the Bridge Control register SERR# Enable bit is set, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. 112 PCI Status register Signaled System Error bit is set if the PCI Command and Bridge Control register SERR# Enable bits are set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.1.5 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) PCI/PCI-X Master Abort on Posted Transaction When a Posted Write transaction forwarded from PCI Express to PCI/PCI-X results in a Master Abort on the PCI/PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. Secondary Status register Secondary Received Master Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Master Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared –or– the Bridge Control register Master Abort Mode bit is set, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 8.1.1.6 PCI Status register Signaled System Error bit is set if the Master Abort Mode bit is set or the Received Master Abort Mask bit is cleared and the SERR# Enable bit is set. PCI/PCI-X Master Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express to PCI/PCI-X results in a Master Abort on the PCI/PCI-X Bus, the following occurs: 1. Completion with Unsupported Request status is returned on the PCI Express interface. 2. Secondary Status register Secondary Received Master Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Master Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI express interface, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the Received Master Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 113 Error Handling 8.1.1.7 PLX Technology, Inc. PCI-X Master Abort on Split Completion When a Split Completion forwarded from PCI Express to PCI-X results in a Master Abort on the PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. Secondary Status register Secondary Received Master Abort bit is set. 3. PCI-X Secondary Status register Split Completion Discarded bit is set. 4. Secondary Uncorrectable Error Status register Master Abort on Split Completion Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Master Abort on Split Completion Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Master Abort on Split Completion Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Master Abort on Split Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. 8.1.1.8 PCI Status register Signaled System Error bit is set if the Master Abort on Split Completion Mask bit is cleared and the SERR# Enable bit is set. PCI/PCI-X Target Abort on Posted Transaction When a Posted Write transaction forwarded from PCI Express to PCI/PCI-X results in a Target Abort on the PCI/PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. Secondary Status register Secondary Received Target Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Target Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 114 PCI Status register Signaled System Error bit is set if the Received Target Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.1.9 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) PCI/PCI-X Target Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express to PCI/PCI-X results in a Target Abort on the PCI/PCI-X Bus, the following occurs: 1. Completion with Completer Abort status is returned on the PCI Express interface. 2. Secondary Status register Secondary Received Target Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Target Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 8.1.1.10 PCI Status register Signaled System Error bit is set if the Received Target Abort Mask bit is cleared and the SERR# Enable bit is set. PCI-X Target Abort on Split Completion When a Split Completion forwarded from PCI Express to PCI-X results in a Target Abort on the PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. Secondary Status register Secondary Received Target Abort bit is set. 3. PCI-X Secondary Status register Split Completion Discarded bit is set. 4. Secondary Uncorrectable Error Status register Target Abort on Split Completion Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Target Abort on Split Completion Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Target Abort on Split Completion Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Target Abort on Split Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Target Abort on Split Completion Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 115 Error Handling 8.1.1.11 PLX Technology, Inc. Completer Abort CSR registers internal to the PEX 8114 can be accessed through BAR0 Memory-Mapped accesses. These Read/Write accesses are limited to single DWord transactions. If a Memory-Mapped CSR access is received with a TLP length field greater than 1 DWord, the following occurs: 1. When the transaction is a Write Request, the transaction is dropped. When the transaction is a Read request, a Completion with Completer Abort status is returned to the Requester and the PCI Status register Signaled Target Abort bit is set. 2. Uncorrectable Error Status register Completer Abort Status bit is set. 3. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register ECRC Error Mask bit is cleared and the First Error Pointer is inactive. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Completer Abort Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Completer Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. 8.1.1.12 PCI Status register Signaled System Error bit is set if the Uncorrectable Error Mask register Completer Abort Mask bit is cleared and the SERR# Enable bit is set. Unexpected Completion When a Completion, targeted at the bridge, is received on the PCI Express interface that does not contain a corresponding outstanding request, the following occurs: 1. Entire transaction is discarded. 2. PCI-X Bridge Status register Unexpected Split Completion bit is set. 3. Uncorrectable Error Status register Unexpected Completion Status bit is set. 4. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register Unexpected Completion Mask bit is cleared and the First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Unexpected Completion Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Unexpected Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 116 PCI Status register Signaled System Error bit is set if the Uncorrectable Error Mask register Unexpected Completion Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.1.13 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) Receive Non-Posted Request Unsupported When a Non-Posted request, targeted to the PEX 8114, is received on the PCI Express interface and the bridge cannot complete the request, the following occurs: 1. Completion with Unsupported Request Completion status is returned to the Requester. 2. Uncorrectable Error Status register Unsupported Request Error Status bit is set. 3. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register Uncorrectable First Error Pointer is updated if the Uncorrectable Error Mask register Unsupported Request Error Mask bit is cleared and the Uncorrectable First Error Pointer is inactive. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Unsupported Request Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Unsupported Request Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. 8.1.1.14 PCI Status register Signaled System Error bit is set if the Unsupported Request Error Mask bit is cleared and the SERR# Enable bit is set. Link Training Error When a PCI Express Link Training error is detected, the following occurs: 1. Uncorrectable Error Status register Training Error Status bit is set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Training Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Training Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. PCI Status register Signaled System Error bit is set if the Training Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 117 Error Handling 8.1.1.15 PLX Technology, Inc. Data Link Protocol Error When a PCI Express Data Link Protocol error is detected, the following occurs: 1. Uncorrectable Error Status register Data Link Protocol Error Status bit is set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Data Link Protocol Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Data Link Protocol Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. 8.1.1.16 PCI Status register Signaled System Error bit is set if the Data Link Protocol Error Mask bit is cleared and the SERR# Enable bit is set. Flow Control Protocol Error When a PCI Express Flow Control Protocol error is detected, the following occurs: 1. Uncorrectable Error Status register Flow Control Protocol Error Status bit is set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Flow Control Protocol Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Flow Control Protocol Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. 118 PCI Status register Signaled System Error bit is set if the Flow Control Protocol Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.1.17 Forward Transparent Bridge PCI Express Originating Interface (Primary to Secondary) Receiver Overflow When a PCI Express Receiver Overflow is detected, the following occurs: 1. Uncorrectable Error Status register Receiver Overflow Status bit is set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Receiver Overflow Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Receiver Overflow Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. 8.1.1.18 PCI Status register Signaled System Error bit is set if the Receiver Overflow Mask bit is cleared and the SERR# Enable bit is set. Malformed TLP When a PCI Express Malformed TLP is received, the following occurs: 1. Uncorrectable Error Status register Malformed TLP Status bit is set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Malformed TLP Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Malformed TLP Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. PCI Status register Signaled System Error bit is set if the Malformed TLP Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 119 Error Handling 8.1.2 PLX Technology, Inc. Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) This section describes error support for transactions that cross the bridge if the originating side is the PCI/PCI-X Bus, and the destination side is PCI Express. The PEX 8114 supports TLP poisoning as a transmitter to permit proper forwarding of Parity errors that occur on the PCI/PCI-X interface. Posted Write data received on the PCI/PCI-X interface with bad parity is forwarded to the PCI Express interface as Poisoned TLPs. Table 8-2 defines the error forwarding requirements for Uncorrectable Data errors that the PEX 8114 detects when a transaction targets the PCI Express interface. Table 8-3 defines the bridge behavior on a PCI/PCI-X Delayed transaction forwarded by a bridge to the PCI Express interface as a Memory Read or I/O Read/Write Request, and the PCI Express interface returns a Completion with UR or CA status for the request. Table 8-2. Error Forwarding Requirements for Uncorrectable Data Errors Received PCI/PCI-X Error Forwarded PCI Express Error Write with Parity error Write Request with Poisoned TLP Read Completion or Split Read Completion with Parity error in Data phase Read Completion with Poisoned TLP Configuration or I/O Completion with Parity error in Data phase Split Completion message with Uncorrectable Data error in Data phase Table 8-3. Bridge Behavior on PCI/PCI-X Delayed Transaction Forwarded by Bridge PCI Express Completion Status Unsupported Request (on Memory or I/O Read) Unsupported Request (on I/O Write) Completer Abort 120 Read/Write Completion with Completer Abort Status PCI/PCI-X Immediate Response Master Abort Mode = 1 Master Abort Mode = 0 Normal Completion, returns FFFF_FFFFh Target Abort Normal Completion Target Abort ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.2.1 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Received PCI/PCI-X Errors Uncorrectable Data Error on Posted Write When the PEX 8114 detects an Uncorrectable Data error on the PCI/PCI-X secondary interface for a Posted Write transaction that crosses the bridge, the following occurs: 1. PCI_PERR# is asserted if the Bridge Control register Secondary Parity Error Response Enable bit is set. 2. Secondary Status register Secondary Detected Parity Error bit is set. 3. Posted Write transaction is forwarded to PCI Express as a Poisoned TLP. 4. PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. 5. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 6. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 7. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 121 Error Handling PLX Technology, Inc. Uncorrectable Data Error on Non-Posted Write in Conventional PCI Mode When a Non-Posted Write is addressed allowing it to cross the bridge, and the PEX 8114 detects an Uncorrectable Data error on the PCI interface, the following occurs: 1. Secondary Status register Secondary Detected Parity Error bit is set. 2. When the Bridge Control register Secondary Parity Error Response Enable bit is set, the transaction is discarded and not forwarded to the PCI Express interface, and PCI_PERR# is asserted on the PCI Bus. When the Secondary Parity Error Response Enable bit is cleared, the data is forwarded to PCI Express as a Poisoned TLP. The PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. PCI_PERR# is not asserted on the PCI Bus. 3. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 122 PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Uncorrectable Data Error on Non-Posted Write in PCI-X Mode When a Non-Posted Write is addressed allowing it to cross the bridge, and the PEX 8114 detects an Uncorrectable Data error on the PCI-X interface, the following occurs: 1. Secondary Status register Secondary Detected Parity Error bit is set. 2. PEX 8114 signals Data Transfer for Non-Posted Write transactions, and if there is an Uncorrectable Data error, the transaction is discarded. 3. When the Bridge Control register Secondary Parity Error Response Enable bit is set, PCI_PERR# is asserted on the PCI-X Bus. 4. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 123 Error Handling PLX Technology, Inc. Uncorrectable Data Error on PCI Delayed Read Completions When the PEX 8114 forwards a Non-Poisoned Read Completion from PCI Express to PCI, and it detects PCI_PERR# asserted by the PCI Master, the following occurs: 1. Remainder of the Completion is forwarded. 2. Secondary Uncorrectable Error Status register PERR# Assertion Detected bit is set. 3. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. When the PEX 8114 forwards a Poisoned Read Completion from PCI Express to PCI, the PEX 8114 proceeds with the listed actions when it detects PCI_PERR# asserted by the PCI Master; however, an Error message is not generated on the PCI Express interface. 124 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Uncorrectable Data Error on PCI-X Split Read Completions When the PEX 8114 detects an Uncorrectable Data error on the PCI-X secondary interface while receiving a Split Read Completion that crosses the bridge, the following occurs: 1. PCI_PERR# is asserted if the Bridge Control register Secondary Parity Error Response Enable bit is set. 2. Secondary Status register Secondary Detected Parity Error bit is set. 3. Split Read Completion transaction is forwarded to PCI Express as a Poisoned TLP. 4. Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. 5. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 6. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 7. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 125 Error Handling PLX Technology, Inc. Uncorrectable Address Error When the PEX 8114 detects an Uncorrectable Address error, and Parity error detection is enabled by way of the Bridge Control register Secondary Parity Error Response Enable bit, the following occurs: 1. Transaction is terminated with a Target Abort and discarded. 2. Secondary Status register Secondary Detected Parity Error bit is set, independent of the Bridge Control register Secondary Parity Error Response Enable bit value. 3. Secondary Status register Secondary Signaled Target Abort bit is set. 4. Secondary Uncorrectable Error Status register Uncorrectable Address Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Address Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Address Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Address Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Uncorrectable Address Error Mask bit is cleared and the SERR# Enable bit is set. Uncorrectable Attribute Error When the PEX 8114 detects an Uncorrectable Attribute error, and Parity error detection is enabled by way of the Bridge Control register Secondary Parity Error Response Enable bit, the following occurs: 1. Transaction is terminated with a Target Abort and discarded. 2. Secondary Status register Secondary Detected Parity Error bit is set, independent of the Bridge Control register Secondary Parity Error Response Enable bit value. 3. Secondary Status register Secondary Signaled Target Abort bit is set. 4. Secondary Uncorrectable Error Status register Uncorrectable Attribute Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Attribute Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Attribute Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Attribute Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. 126 PCI Status register Signaled System Error bit is set if the Uncorrectable Attribute Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.2.2 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Unsupported Request (UR) Completion Status The PEX 8114 provides two methods for handling a PCI Express Completion received with Unsupported Request (UR) status in response to requests originated by the PCI/PCI-X interface. The Bridge Control register Master Abort Mode bit controls the response. In either case, the PCI Status register Received Master Abort bit is set. Master Abort Mode Bit Cleared This is the default PCI compatibility mode, and an Unsupported Request is not considered an error. When a Read transaction initiated on the PCI/PCI-X Bus results in the return of a Completion with Unsupported Request status, the PEX 8114 returns FFFF_FFFFh to the originating Master and asserts PCI_TRDY# to terminate the Read transaction normally on the originating interface. When a Non-Posted Write transaction results in a Completion with Unsupported Request status, the PEX 8114 asserts PCI_TRDY# to complete the Write transaction normally on the originating bus, and discards the Write data. Master Abort Mode Bit Set When the Master Abort Mode bit is set, the PEX 8114 signals a Target Abort to the originating Master of an upstream Read or Non-Posted Write transaction when the corresponding request on the PCI Express interface results in a Completion with UR Status. Additionally, the Secondary Status register Secondary Signaled Target Abort bit is set. 8.1.2.3 Completer Abort (CA) Completion Status When the PEX 8114 receives a Completion with Completer Abort status on the PCI Express primary interface in response to a forwarded Non-Posted PCI/PCI-X transaction, the PCI Status register Received Target Abort bit is set. A CA response results in a Delayed Transaction Target Abort or a Split Completion Target Abort Error message on the PCI/PCI-X Bus. The PEX 8114 provides data to the requesting PCI/PCI-X agent, up to the point where data was successfully returned from the PCI Express interface, then signals Target Abort. The Secondary Status register Secondary Signaled Target Abort bit is set when signaling Target Abort to a PCI/PCI-X agent. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 127 Error Handling 8.1.2.4 PLX Technology, Inc. Split Completion Errors Split Completion Message with Completer Errors A transaction originating from the PCI Express interface and requiring a Completion can be forwarded to the PCI-X interface, where the Target (Completer) responds with Split Response. If the Completer encounters a condition that prevents the successful execution of a Split transaction, the Completer must notify the Requester of the abnormal condition, by returning a Split Completion message with the Completer Error class. If the bridge responds with Completer Abort status, it sets the PCI Status register Signaled Target Abort bit. Table 8-4 defines the abnormal conditions and the bridge’s response to the Split Completion message. Each is described in the sections that follow. Table 8-4. Abnormal Conditions and Bridge Response to Split Completion Messages PCI-X Split Completion Message Completer Error Code Bit Set in Secondary Status Register Bit Set in Secondary Uncorrectable Error Status Register PCI Express Completion Status Class Index Master Abort 1h 00h Received Master Abort Received Master Abort Unsupported Request Target Abort 1h 01h Received Target Abort Received Target Abort Completer Abort Uncorrectable Write Data Error 1h 02h Master Data Parity Error PERR# Assertion Detected Unsupported Request Byte Count Out of Range 2h 00h None None Unsupported Request Uncorrectable Split Write Data Error 2h 01h Master Data Parity Error PERR# Assertion Detected Unsupported Request Device-Specific Error 2h 8Xh None None Completer Abort 128 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Split Completion Message with Master Abort When a bridge receives a Split Completion message indicating Master Abort, the following occurs: 1. Completion with Unsupported Request status is returned to the Requester. 2. Secondary Status register Received Master Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Master Abort Status bit is set. 4. TLP Header of the original request is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the Received Master Abort Mask bit is cleared and the SERR# Enable bit is set. Split Completion Message with Target Abort When a bridge receives a Split Completion message indicating Target Abort, the following occurs: 1. Completion with Completer Abort status is returned to the Requester. 2. Secondary Status register Received Target Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Target Abort Status bit is set. 4. PCI Status register Signaled Target Abort bit is set. 5. TLP Header of the original request is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Received Target Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 129 Error Handling PLX Technology, Inc. Split Completion Message with Uncorrectable Write Data Error or Uncorrectable Split Write Data Error When a bridge receives a Split Completion message indicating an Uncorrectable Write Data error or Uncorrectable Split Write Data error, the following occurs: 1. Completion with Unsupported Request status is returned to the Requester. 2. Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. 3. Secondary Uncorrectable Error Status register PERR# Assertion Detected bit is set. 4. TLP Header of the original request is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. Split Completion Message with Byte Count Out of Range When a bridge receives a Split Completion message indicating a Byte Count Out of Range error, a Completion with Unsupported Request status is returned to the Requester. Split Completion Message with Device-Specific Error When a bridge receives a Split Completion message indicating a Device-Specific error, a Completion with Completer Abort status is returned to the Requester. 130 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Forward Transparent Bridge PCI/PCI-X Originating Interface (Secondary to Primary) Corrupted or Unexpected Split Completion When a bridge receives a corrupted or unexpected Split Completion, the following occurs: 1. PCI-X Secondary Status register Unexpected Split Completion Status bit is set. 2. Secondary Uncorrectable Error Status register Unexpected Split Completion Error Status bit is set. 3. TLP Header of the corrupt or unexpected Split Completion is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Unexpected Split Completion Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Unexpected Split Completion Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Unexpected Split Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. PCI Status register Signaled System Error bit is set if the Unexpected Split Completion Mask bit is cleared and the SERR# Enable bit is set. Data Parity Error on Split Completion Messages When a bridge detects a Data error during the Data phase of a Split Completion message, the following occurs: 1. Secondary Uncorrectable Error Status register Uncorrectable Split Completion Message Data Error Status bit is set. 2. TLP Header of the Split Completion is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Split Completion Message Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 3. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Split Completion Message Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Split Completion Message Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. PCI Status register Signaled System Error bit is set if the Uncorrectable Split Completion Message Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 131 Error Handling PLX Technology, Inc. 8.1.3 Forward Transparent Bridge Timeout Errors 8.1.3.1 PCI Express Completion Timeout Errors The PCI Express Completion Timeout mechanism allows Requesters to abort a Non-Posted request if a Completion does not arrive within a reasonable time. Bridges, when acting as Initiators on the PCI Express interface on behalf of internally generated requests, or when forwarding requests from a secondary interface, behave as endpoints for requests of which they assume ownership. If a Completion timeout is detected and the link is up, the PEX 8114 responds as if a Completion with Unsupported Request status was received, and the following occurs: 1. Uncorrectable Error Status register Completion Timeout Status bit is set. 2. TLP Header of the original request is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register Completion Timeout Mask bit is cleared and the First Error Pointer is inactive. 3. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Uncorrectable Error Severity register Completion Timeout Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Completion Timeout Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. 8.1.3.2 PCI Status register Signaled System Error bit is set if the SERR# Enable bit is set. PCI Delayed Transaction Timeout Errors The PEX 8114 contains Delayed Transaction Discard Timers for each queued Delayed transaction. If a Delayed Transaction timeout is detected, the following occurs: 1. Bridge Control register Discard Timer Status bit and Secondary Uncorrectable Error Status register Delayed Transaction Discard Timer Expired Status bit are set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the Secondary Uncorrectable Error Severity register Delayed Transaction Discard Timer Expired Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Delayed Transaction Discard Timer Expired Mask bit is cleared –or– Bridge Control register Discard Timer SERR# Enable bit is set, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. 132 PCI Status register Signaled System Error bit is set if the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.1.4 Forward Transparent Bridge SERR# Forwarding Forward Transparent Bridge SERR# Forwarding PCI devices can assert SERR# when detecting errors that compromise system integrity. When the PEX 8114 detects SERR# asserted on the secondary PCI/PCI-X Bus, the following occurs: 1. Secondary Status register Received System Error bit and Secondary Uncorrectable Error Status register SERR# Assertion Detected Status bit are set. 2. ERR_FATAL/ERR_NONFATAL message is generated on the PCI Express interface, depending upon the severity of the Secondary Uncorrectable Error Severity register SERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register SERR# Assertion Detected Mask bit is cleared –or– Bridge Control register SERR# Enable bit is set, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set 3. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 4. PCI Status register Signaled System Error bit is set if the PCI Command and Bridge Control register SERR# Enable bits are set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 133 Error Handling PLX Technology, Inc. 8.2 Reverse Transparent Bridge Error Handling 8.2.1 Reverse Transparent Bridge Forwarding System Errors and System Error Messages PCI Express Error Reporting messages are not compatible with PCI/PCI-X interfaces. There are three types of error levels, each reported by a unique Error message: • Correctable (ERR_COR) • Non-Fatal (ERR_NONFATAL) • Fatal (ERR_FATAL) Error messages received from the PCI Express hierarchy are forwarded upstream, through the PCI_INTA# or PCI_SERR# balls or a Message Signaled interrupt (MSI). To control error reporting and forwarding by the PEX 8114, use one of the following: • Root Port registers • Conventional PCI Type 1 register set For all errors detected by the bridge, the bridge sets the appropriate error status bit [both Conventional PCI/PCI-X error bit(s) and PCI Express error status bit(s)]. If reporting for an error is not masked, the bridge also reports to the Root Port registers. The Root Port registers Forward bridge-detected errors in the same manner as Error messages received from the hierarchy, as if the bridge transmitted an Error message to itself. 134 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.1.1 Reverse Transparent Bridge Forwarding System Errors and System Error Messages Root Port Error Forwarding Control The Root Port registers provide control, to enable forwarding of each error type, independently of the others. The Root Control register enables reporting of error events through Conventional PCI system errors. PCI_SERR# is asserted when the PEX 8114 detects errors that are not masked, or an Error message is received and the corresponding Reporting Enable bit is set. Three bits control PCI_SERR# assertion for Correctable, Non-Fatal, and Fatal errors: • System Error on Correctable Error Enable • System Error on Non-Fatal Error Enable • System Error on Fatal Error Enable The Root Error Command register enables forwarding of error events through Interrupt requests: • PCI_INTA# is asserted when the PEX 8114 detects errors that are not masked, the corresponding Reporting Enable bit is set, and the Command register Interrupt Disable bit is cleared • An MSI is transmitted, and PCI_INTA# is not asserted, when the PEX 8114 detects errors that are not masked, the corresponding Reporting Enable bit is set, the Command register Interrupt Disable bit is cleared, and the MSI Control register MSI Enable bit is set • PCI_INTA# is asserted when the PEX 8114 receives an Error message on the PCI Express interface, and the corresponding Reporting Enable bit is set • An MSI is transmitted, and PCI_INTA# is not asserted, when the PEX 8114 receives an Error message on the PCI Express interface, the corresponding Reporting Enable bit is set, and the MSI Control register MSI Enable bit is set Three Root Error Command register bits control PCI_INTA# assertion or MSI signaling for Correctable, Non-Fatal, and Fatal errors: • Correctable Error Reporting Enable • Non-Fatal Error Reporting Enable • Fatal Error Reporting Enable ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 135 Error Handling 8.2.1.2 PLX Technology, Inc. Conventional PCI Type 1 Error Forwarding Control Two Conventional PCI bits control reporting and forwarding of bridge-detected errors and Error messages received from the PCI Express hierarchy: • PCI Command register SERR# Enable bit • Bridge Control register SERR# Enable bit Fatal and Non-Fatal errors detected by the bridge are forwarded to the Host by PCI_SERR# assertion, if the PCI Command register SERR# Enable bit is set. Fatal and Non-Fatal Error messages received from the PCI Express hierarchy are forwarded to the Host by PCI_SERR# assertion if the PCI Command and Bridge Control register SERR# Enable bits are set. 8.2.1.3 Bridge-Detected Error Reporting Errors detected by the PEX 8114 that are not masked must be enabled to report to the Root Port registers. The following four bits control error reporting to the Root Port registers: • PCI Command register SERR# Enable bit • PCI Express Device Control register Correctable Error Reporting Enable bit • PCI Express Device Control register Non-Fatal Error Reporting Enable bit • PCI Express Device Control register Fatal Error Reporting Enable bit Additionally, the SERR# Enable bit controls the forwarding of errors upstream to the Host. Correctable errors (ERR_COR) are reported to the Root Port registers if the Correctable Error Reporting Enable bit is set. Non-Fatal errors (ERR_NONFATAL) are reported to the Root Port registers if the SERR# Enable or Non-Fatal Error Reporting Enable bit is set. Fatal errors (ERR_FATAL) are reported to the Root Port registers if the SERR# Enable or Fatal Error Reporting Enable bit is set. The Device Status register Correctable, Non-Fatal, and Fatal Error Detected status bits are set for the corresponding errors, regardless of the Error Reporting Enable settings. 136 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) This section describes error support for transactions that cross the bridge if the originating side is the PCI Express (secondary) interface, and the destination interface is operating in a Conventional PCI/ PCI-X (primary) mode. If a Write Request or Read Completion is received with a Poisoned TLP, the entire PCI Express transaction Data Payload must be considered corrupt. Parity is inverted for all Data phases when completing PCI/PCI-X Bus transactions. If a TLP is received and an ECRC error is detected, the entire TLP must be considered corrupt and not forwarded, but dropped by the bridge. Table 8-5 defines the translation the PEX 8114 performs when it forwards a Non-Posted PCI Express Request (Write or Read) to the PCI/PCI-X Bus, and the request is immediately completed normally on the PCI/PCI-X Bus or with an error condition. Table 8-5. Translation Bridge Action when Forwarding Non-Posted PCI Express Request to PCI/PCI-X Bus Immediate PCI/PCI-X Termination Data Transfer with Parity error (Reads) PCI Express Completion Status Successful (Poisoned TLP) Completion with Parity error (Non-Posted Writes) Unsupported Request Master Abort Unsupported Request Target Abort Completer Abort ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 137 Error Handling 8.2.2.1 PLX Technology, Inc. Received Poisoned TLP When a Write Request or Read Completion is received by the PCI Express interface, and the data is poisoned, the following occurs: 1. Secondary Status register Secondary Detected Parity Error bit is set. 2. Secondary Status register Secondary Master Data Parity Error bit is set if the Poisoned TLP is a Read Completion and the Bridge Control register Secondary Parity Error Response Enable bit is set. 3. Uncorrectable Error Status register Poisoned TLP Status bit is set. 4. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared and the First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Poisoned TLP Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Poisoned TLP Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Poisoned TLP Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Poisoned TLP Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Poisoned TLP Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Uncorrectable Error Mask register Poisoned TLP Error Mask bit is cleared and the SERR# Enable bit is set. 9. Parity bit associated with each DWord of data on the PCI/PCI-X Bus is inverted. 10. When a Poisoned TLP Write Request is forwarded to the PCI/PCI-X Bus and the bridge detects PCI_PERR# asserted, the following occurs: – PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set – Secondary Uncorrectable Error Status register PERR# Assertion Detected bit is set – Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the First Error Pointer is inactive 138 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.2 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Received ECRC Error When a TLP is received and the bridge detects an ECRC error, the following occurs: 1. Transaction is dropped. 2. Secondary Status register Secondary Detected Parity Error bit is set. 3. Uncorrectable Error Status register ECRC Error Status bit is set. 4. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register ECRC Error Mask bit is cleared and the First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register ECRC Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register ECRC Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the ECRC Error Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register ECRC Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register ECRC Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the ECRC Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the ECRC Error Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the ECRC Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 139 Error Handling 8.2.2.3 PLX Technology, Inc. PCI/PCI-X Uncorrectable Data Errors The following sections describe error handling when forwarding Non-Poisoned PCI Express transactions to the PCI/PCI-X Bus, and an Uncorrectable PCI/PCI-X error is detected. Posted Writes When the PEX 8114 detects PCI_PERR# asserted on the PCI/PCI-X primary interface while forwarding a Non-Poisoned Posted Write transaction from the PCI Express interface, the following occurs: 1. PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. 2. Secondary Uncorrectable Error Status register PERR# Assertion Detected Status bit is set. 3. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the PERR# Assertion Detected Severity 5. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 140 7. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. 8. After the error is detected, the remainder of the data is forwarded. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Non-Posted Writes When the PEX 8114 detects PCI_PERR# asserted on the PCI/PCI-X primary interface while forwarding a Non-Poisoned Non-Posted Write transaction from the PCI Express interface, the following occurs: 1. PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. 2. PCI Express Completion with Unsupported Request status is generated. 3. Secondary Uncorrectable Error Status register PERR# Assertion Detected Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the PERR# Assertion Detected Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. When the Target signals Split Response, the bridge terminates the transaction as it would for a Split Request that does not contain an error and takes no further action. If the returned Split Completion is a Split Completion Error message, the bridge returns a PCI Express Completion with Unsupported Request status to the Requester. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 141 Error Handling PLX Technology, Inc. Immediate Reads When the PEX 8114 forwards a Read request (I/O, Memory, or Configuration) from the PCI Express interface and detects an Uncorrectable Data error on the primary bus while receiving an Immediate or Split Response from the Completer, the following occurs: 1. PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. 2. PCI Status register Detected Parity Error bit is set. 3. PCI_PERR# is asserted on the secondary interface if the PCI Command register Parity Error Response Enable bit is set. 4. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Data Error Severity 7. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. After detecting an Uncorrectable Data error on the destination bus for an Immediate Read transaction, the PEX 8114 continues to fetch data until the Byte Count is satisfied or the Target ends the transaction. When the bridge creates the PCI Express Completion, it forwards the Completion with Successful Completion status and poisons the TLP. For PCI-X, an Uncorrectable Data error on a Split Response does not affect handling of subsequent Split Completions. 142 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) PCI-X Split Read Completions When the bridge forwards a Non-Poisoned Read Completion from PCI Express to PCI-X and detects PCI_PERR# asserted by the PCI-X Target, the following occurs: 1. Bridge continues to forward the remainder of the Split Completion. 2. Secondary Uncorrectable Error Status register PERR# Assertion Detected Status bit is set. 3. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. PCI_SERR# is asserted on the PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the PERR# Assertion Detected Severity 5. PCI_INTA# is asserted on the PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 143 Error Handling 8.2.2.4 PLX Technology, Inc. PCI/PCI-X Address/Attribute Errors When the PEX 8114 forwards transactions from PCI Express to PCI/PCI-X, the Target asserts SERR# to report PCI Address errors. The PEX 8114 ignores the SERR# assertion, and allows the PCI Central Resource to service the error. 8.2.2.5 PCI/PCI-X Master Abort on Posted Transaction When a Posted Write transaction forwarded from PCI Express to PCI/PCI-X results in a Master Abort on the PCI/PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. PCI Status register Received Master Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Master Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Received Master Abort Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Master Abort Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Master Abort Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. 144 PCI Status register Signaled System Error bit is set if the Received Master Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.6 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) PCI/PCI-X Master Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express to PCI/PCI-X results in a Master Abort on the PCI/PCI-X Bus, the following occurs: 1. Completion with Unsupported Request status is returned on the PCI Express interface. 2. PCI Status register Received Master Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Master Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Received Master Abort Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Master Abort Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Master Abort Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Received Master Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 145 Error Handling 8.2.2.7 PLX Technology, Inc. PCI-X Master Abort on Split Completion When a Split Completion forwarded from PCI Express to PCI-X results in a Master Abort on the PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. PCI Status register Received Master Abort bit is set. 3. PCI-X Status register Split Completion Discarded bit is set. 4. Secondary Uncorrectable Error Status register Master Abort on Split Completion Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Master Abort on Split Completion Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Master Abort on Split Completion Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Master Abort on Split Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Master Abort on Split Completion Severity 7. PCI_INTA# is asserted on the PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Master Abort on Split Completion Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Master Abort on Split Completion Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Master Abort on Split Completion Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Master Abort on Split Completion Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. 146 PCI Status register Signaled System Error bit is set if the Master Abort on Split Completion Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.8 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) PCI/PCI-X Target Abort on Posted Transaction When a Posted Write transaction forwarded from PCI Express to PCI/PCI-X results in a Target Abort on the PCI/PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. PCI Status register Received Target Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Target Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Received Target Abort Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Target Abort Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Target Abort Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Received Target Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 147 Error Handling 8.2.2.9 PLX Technology, Inc. PCI/PCI-X Target Abort on Non-Posted Transaction When a Non-Posted transaction forwarded from PCI Express to PCI/PCI-X results in a Target Abort on the PCI/PCI-X Bus, the following occurs: 1. Completion with Completer Abort status is returned on the PCI Express interface. 2. PCI Status register Received Target Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Target Abort Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Received Target Abort Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Target Abort Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Target Abort Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. 148 PCI Status register Signaled System Error bit is set if the Received Target Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.10 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) PCI-X Target Abort on Split Completion When a Split Completion forwarded from PCI Express to PCI-X results in a Target Abort on the PCI-X Bus, the following occurs: 1. Entire transaction is discarded. 2. PCI Status register Received Target Abort bit is set. 3. PCI-X Bridge Status register Split Completion Discarded bit is set. 4. Secondary Uncorrectable Error Status register Target Abort on Split Completion Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Target Abort on Split Completion Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Target Abort on Split Completion Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Target Abort on Split Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Target Abort on Split Completion Severity 7. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Target Abort on Split Completion Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Target Abort on Split Completion Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Target Abort on Split Completion Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Target Abort on Split Completion Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. PCI Status register Signaled System Error bit is set if the Target Abort on Split Completion Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 149 Error Handling 8.2.2.11 PLX Technology, Inc. Unexpected Completion Received When a Completion targeted at the bridge is received on the PCI Express interface, without a corresponding outstanding request, the following occurs: 1. Entire transaction is discarded. 2. PCI-X Secondary Status register Unexpected Split Completion bit is set. 3. Uncorrectable Error Status register Unexpected Completion Status bit is set. 4. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register Uncorrectable First Error Pointer is updated if the Uncorrectable Error Mask register Unexpected Completion Mask bit is cleared and the Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Unexpected Completion Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Unexpected Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Unexpected Completion Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Unexpected Completion Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Unexpected Completion Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Unexpected Completion Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Unexpected Completion Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. 150 PCI Status register Signaled System Error bit is set if the Unexpected Completion Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.12 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Received Request Unsupported When a Non-Posted request, targeted to the PEX 8114, is received on the PCI Express interface and the bridge cannot complete the request, the following occurs: 1. Completion with Unsupported Request Completion status is returned to the Requester. 2. Uncorrectable Error Status register Unsupported Request Error Status bit is set. 3. TLP Header is logged in the Header Log register and the Advanced Error Capabilities and Control register Uncorrectable First Error Pointer is updated if the Uncorrectable Error Mask register Unsupported Request Error Mask bit is cleared and the Uncorrectable First Error Pointer is inactive. 4. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Unsupported Request Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Unsupported Request Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Unsupported Request Error Severity 5. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Unsupported Request Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Unsupported Request Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Unsupported Request Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Unsupported Request Error Severity 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the Unsupported Request Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 151 Error Handling 8.2.2.13 PLX Technology, Inc. Link Training Error When a PCI Express Link Training error is detected, the following occurs: 1. Uncorrectable Error Status register Training Error Status bit is set. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Training Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Training Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Training Error Severity 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Training Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Training Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Training Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Training Error Severity 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. 152 PCI Status register Signaled System Error bit is set if the Training Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.14 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Data Link Protocol Error When a PCI Express Data Link Protocol error is detected, the following occurs: 1. Uncorrectable Error Status register Data Link Protocol Error Status bit is set. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Data Link Protocol Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Data Link Protocol Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Data Link Protocol Error Severity 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Data Link Protocol Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Data Link Protocol Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Data Link Protocol Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Data Link Protocol Error Severity 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. PCI Status register Signaled System Error bit is set if the Data Link Protocol Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 153 Error Handling 8.2.2.15 PLX Technology, Inc. Flow Control Protocol Error When a PCI Express Flow Control Protocol error is detected, the following occurs: 1. Uncorrectable Error Status register Flow Control Protocol Error Status bit is set. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Flow Control Protocol Error Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Flow Control Protocol Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Flow Control Protocol Error Severity 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Flow Control Protocol Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Flow Control Protocol Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Flow Control Protocol Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Flow Control Protocol Error Severity 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. 154 PCI Status register Signaled System Error bit is set if the Flow Control Protocol Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.2.16 Reverse Transparent Bridge PCI Express Originating Interface (Secondary to Primary) Receiver Overflow When a PCI Express Receiver Overflow is detected, the following occurs: 1. Uncorrectable Error Status register Receiver Overflow Status bit is set. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Receiver Overflow Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Receiver Overflow Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Receiver Overflow Severity 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Receiver Overflow Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Receiver Overflow Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Receiver Overflow Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Receiver Overflow Severity 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. PCI Status register Signaled System Error bit is set if the Receiver Overflow Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 155 Error Handling 8.2.2.17 PLX Technology, Inc. Malformed TLP When a PCI Express Malformed TLP is received, the following occurs: 1. Uncorrectable Error Status register Malformed TLP Status bit is set. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Malformed TLP Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Malformed TLP Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Malformed TLP Severity 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Malformed TLP Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Malformed TLP Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Malformed TLP Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Malformed TLP Severity 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. 156 PCI Status register Signaled System Error bit is set if the Malformed TLP Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.3 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) This section describes error support for transactions that cross the bridge if the originating side is the PCI/PCI-X Bus, and the destination side is PCI Express. The PEX 8114 supports TLP poisoning as a transmitter to allow proper forwarding of Parity errors that occur on the PCI/PCI-X interface. Posted Write data received on the PCI/PCI-X interface with bad parity is forwarded to the PCI Express interface as Poisoned TLPs. Table 8-6 defines the error forwarding requirements for Uncorrectable Data errors that the PEX 8114 detects when a transaction targets the PCI Express interface. Table 8-7 defines the bridge behavior on a PCI/PCI-X Delayed transaction forwarded by the PEX 8114 to the PCI Express interface as a Memory Read or I/O Read/Write request, and the PCI Express interface returns a Completion with UR or CA status for the request. Table 8-6. Error Forwarding Requirements for Uncorrectable Data Errors Received PCI/PCI-X Error Forwarded PCI Express Error Write with Parity error Write request with Poisoned TLP Read Completion or Split Read Completion with Parity error in Data phase Read Completion with Poisoned TLP Configuration or I/O Completion with Parity error in Data phase Split Completion message with Uncorrectable Data error in Data phase Table 8-7. Read/Write Completion with Completer Abort Status Bridge Behavior on PCI/PCI-X Delayed Transaction Forwarded by PEX 8114 PCI Express Completion Status Unsupported Request (on Memory or I/O Read) Unsupported Request (on I/O Write) Completer Abort PCI/PCI-X Immediate Response Master Abort Mode = 1 Master Abort Mode = 0 Normal Completion, returns FFFF_FFFFh Target Abort Normal Completion Target Abort ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 157 Error Handling 8.2.3.1 PLX Technology, Inc. Received PCI/PCI-X Errors Uncorrectable Data Error on Posted Write When the PEX 8114 detects an Uncorrectable Data error on the PCI/PCI-X primary interface for a Posted Write transaction that crosses the bridge, the following occurs: 1. PCI_PERR# is asserted if the PCI Command register Parity Error Response Enable bit is set. 2. PCI Status register Detected Parity Error bit is set. 3. Posted Write transaction is forwarded to the PCI Express interface as a Poisoned TLP. 4. Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. 5. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 6. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 7. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Data Error Severity 8. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity 9. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 10. 158 PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Uncorrectable Data Error on Non-Posted Write in Conventional PCI Mode When a Non-Posted Write is addressed allowing it to cross the bridge, and the PEX 8114 detects an Uncorrectable Data error on the PCI interface, the following occurs: 1. PCI Status register Detected Parity Error bit is set. 2. When the PCI Command register Parity Error Response Enable bit is set, the transaction is discarded and not forwarded to the PCI Express interface. PCI_PERR# is asserted on the PCI Bus. When the Parity Error Response Enable bit is cleared, the data is forwarded to the PCI Express interface as a Poisoned TLP. The Secondary Status register Secondary Master Data Parity Error bit is set if the Bridge Control register Secondary Parity Error Response Enable bit is set. PCI_PERR# is not asserted on the PCI Bus. 3. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 4. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Data Error Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 159 Error Handling PLX Technology, Inc. Uncorrectable Data Error on Non-Posted Write in PCI-X Mode When a Non-Posted Write is addressed allowing it to cross the bridge, and the PEX 8114 detects an Uncorrectable Data error on the PCI-X interface, the following occurs: 1. PCI Status register Detected Parity Error bit is set. 2. PEX 8114 signals a Data transfer for Non-Posted Write transactions. If there is an Uncorrectable Data error, the transaction is discarded. 3. When the PCI Command register Parity Error Response Enable bit is set, PCI_PERR# is asserted on the PCI-X Bus. 4. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Data Error Severity 7. PCI_INTA# is asserted on the PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. 160 PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Uncorrectable Data Error on PCI Delayed Read Completions When the PEX 8114 forwards a Non-Poisoned or Poisoned Read Completion from PCI Express to PCI, and it detects PCI_PERR# asserted by the PCI Master, the following occurs: 1. Remainder of the Completion is forwarded. 2. Secondary Uncorrectable Error Status register PERR# Assertion Detected bit is set. 3. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. PCI_SERR# is asserted on the PCI Bus, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the PERR# Assertion Detected Severity 5. PCI_INTA# is asserted on the PCI Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. If the PEX 8114 forwards a Poisoned Read Completion from PCI Express to PCI, the PEX 8114 proceeds with the above actions when it detects PCI_PERR# asserted by the PCI Master; however, an Error message is not generated on the PCI Express interface. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 161 Error Handling PLX Technology, Inc. Uncorrectable Data Error on PCI-X Split Read Completions When the PEX 8114 detects an Uncorrectable Data error on the PCI-X interface while receiving a Split Read Completion that crosses the bridge, the following occurs: 1. PCI_PERR# is asserted if the PCI Command register Parity Error Response Enable bit is set. 2. PCI Status register Detected Parity Error bit is set. 3. Split Read Completion transaction is forwarded to the PCI Express interface as a Poisoned TLP. 4. PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. 5. Secondary Uncorrectable Error Status register Uncorrectable Data Error Status bit is set. 6. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 7. PCI_SERR# is asserted on the PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Data Error Severity 8. PCI_INTA# is asserted on the PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Data Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Data Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Data Error Severity 9. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 10. 162 PCI Status register Signaled System Error bit is set if the Uncorrectable Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Uncorrectable Address Error When the PEX 8114 detects an Uncorrectable Address error and Parity error detection is enabled by way of the PCI Command register Parity Error Response Enable bit, the following occurs: 1. Transaction is terminated with a Target Abort and discarded. 2. PCI Status register Detected Parity Error bit is set, independent of the PCI Command register Parity Error Response Enable bit value. 3. PCI Status register Signaled Target Abort bit is set. 4. Secondary Uncorrectable Error Status register Uncorrectable Address Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Address Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Address Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Address Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Address Error Severity 7. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Address Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Address Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Address Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Address Error Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. PCI Status register Signaled System Error bit is set if the Uncorrectable Address Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 163 Error Handling PLX Technology, Inc. Uncorrectable Attribute Error When the PEX 8114 detects an Uncorrectable Attribute error and Parity error detection is enabled by way of the PCI Command register Parity Error Response Enable bit, the following occurs: 1. Transaction is terminated with a Target Abort and discarded. 2. PCI Status register Detected Parity Error bit is set, independent of the PCI Command register Parity Error Response Enable bit value. 3. PCI Status register Signaled Target Abort bit is set. 4. Secondary Uncorrectable Error Status register Uncorrectable Attribute Error Status bit is set. 5. Transaction command, attributes, and address are logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Attribute Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Attribute Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Attribute Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Attribute Error Severity 7. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Attribute Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Attribute Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Attribute Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Attribute Error Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. 164 PCI Status register Signaled System Error bit is set if the Uncorrectable Attribute Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.3.2 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Unsupported Request (UR) Completion Status The PEX 8114 provides two methods for handling a PCI Express Completion received with Unsupported Request (UR) status in response to a request originated by the PCI/PCI-X interface. The Bridge Control register Master Abort Mode bit controls the response. In either case, the Secondary Status register Secondary Received Master Abort bit is set. Master Abort Mode Bit Cleared This is the default PCI/PCI-X compatibility mode, and a UR is not considered an error. When a Read transaction initiated on the PCI/PCI-X Bus results in the return of a Completion with UR status, the PEX 8114 returns FFFF_FFFFh to the originating Master and asserts PCI_TRDY# to terminate the Read transaction normally on the originating interface. When a Non-Posted Write transaction results in a Completion with UR status, the PEX 8114 asserts PCI_TRDY# to complete the Write transaction normally on the originating bus and discards the Write data. Master Abort Mode Bit Set When the Master Abort Mode bit is set, the PEX 8114 signals a Target Abort to the originating Master of an upstream Read or Non-Posted Write transaction when the corresponding request on the PCI Express interface results in a Completion with UR status. Additionally, the PCI Status register Signaled Target Abort bit is set. 8.2.3.3 Completer Abort Completion Status When the PEX 8114 receives a Completion with Completer Abort (CA) status on the PCI Express secondary interface, in response to a forwarded Non-Posted PCI/PCI-X transaction, the Secondary Status register Secondary Received Target Abort bit is set. A CA response results in a Delayed Transaction Target Abort or Split Completion Target Abort Error message on the PCI/PCI-X Bus. The PEX 8114 provides data to the requesting PCI/PCI-X agent, up to the point where data was successfully returned from the PCI Express interface, then signals Target Abort. The PCI Status register Signaled Target Abort bit is set when signaling Target Abort to a PCI/PCI-X agent. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 165 Error Handling 8.2.3.4 PLX Technology, Inc. Split Completion Errors Split Completion Message with Completer Errors A transaction originating from the PCI Express interface and requiring a Completion can be forwarded to the PCI-X interface where the Target (Completer) responds with Split Response. If the Completer encounters a condition that prevents the successful execution of a Split Transaction, the Completer must notify the Requester of the abnormal condition by returning a Split Completion message with the Completer Error class. If the bridge responds with Completer Abort status, it sets the Secondary Status register Signaled Target Abort bit. Table 8-8 defines the abnormal conditions and the bridge’s response to the Split Completion message. Each is described in the sections that follow. Table 8-8. Abnormal Conditions and Bridge Response to Split Completion Messages PCI-X Split Completion Message Completer Error Code Bit Set in PCI Status Register Bit Set in Secondary Uncorrectable Error Status Register PCI Express Completion Status Class Index Master Abort 1h 00h Received Master Abort Received Master Abort Unsupported Request Target Abort 1h 01h Received Target Abort Received Target Abort Completer Abort Uncorrectable Write Data Error 1h 02h Master Data Parity Error PERR# Assertion Detected Unsupported Request Byte Count Out of Range 2h 00h None None Unsupported Request Uncorrectable Split Write Data Error 2h 01h Master Data Parity Error PERR# Assertion Detected Unsupported Request Device-Specific Error 2h 8Xh None None Completer Abort 166 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Split Completion Message with Master Abort When a bridge receives a Split Completion message indicating Master Abort, the following occurs: 1. Completion with Unsupported Request status is returned to the Requester. 2. PCI Status register Received Master Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Master Abort Status bit is set. 4. TLP Header of the original request is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Master Abort Status Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Received Master Abort Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Received Master Abort Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Received Master Abort Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Master Abort Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Master Abort Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the Received Master Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 167 Error Handling PLX Technology, Inc. Split Completion Message with Target Abort When a bridge receives a Split Completion message indicating Target Abort, the following occurs: 1. Completion with Completer Abort status is returned to the Requester. 2. PCI Status register Received Target Abort bit is set. 3. Secondary Uncorrectable Error Status register Received Target Abort bit is set. 4. Secondary Status register Signaled Target Abort bit is set. 5. TLP Header of the original request is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 6. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Received Target Abort Severity 7. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Received Target Abort Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Received Target Abort Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Target Abort Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Received Target Abort Severity 8. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 9. 168 PCI Status register Signaled System Error bit is set if the Received Target Abort Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Split Completion Message with Uncorrectable Write Data Error or Uncorrectable Split Write Data Error When a bridge receives a Split Completion message indicating an Uncorrectable Write Data error or Uncorrectable Split Write Data error, the following occurs: 1. Completion with Unsupported Request status is returned to the Requester. 2. PCI Status register Master Data Parity Error bit is set if the PCI Command register Parity Error Response Enable bit is set. 3. Secondary Uncorrectable Error Status register PERR# Assertion Detected bit is set. 4. TLP Header of the original request is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 5. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the PERR# Assertion Detected Severity 6. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register PERR# Assertion Detected Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register PERR# Assertion Detected Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the PERR# Assertion Detected Severity 7. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 8. PCI Status register Signaled System Error bit is set if the PERR# Assertion Detected Mask bit is cleared and the SERR# Enable bit is set. Split Completion Message with Byte Count Out of Range When a bridge receives a Split Completion message indicating a Byte Count Out of Range error, a Completion with Unsupported Request status is returned to the Requester. Split Completion Message with Device-Specific Error When a bridge receives a Split Completion message indicating a Device-Specific error, a Completion with Completer Abort status is returned to the Requester. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 169 Error Handling PLX Technology, Inc. Corrupted or Unexpected Split Completion When a bridge receives a corrupted or unexpected Split Completion, the following occurs: 1. PCI-X Bridge Status register Unexpected Split Completion Status bit is set. 2. Secondary Uncorrectable Error Status register Unexpected Split Completion Error Status bit is set. 3. TLP Header of the corrupt or unexpected Split Completion is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Unexpected Split Completion Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 4. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Unexpected Split Completion Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Unexpected Split Completion Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Unexpected Split Completion Severity 5. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Unexpected Split Completion Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Unexpected Split Completion Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Unexpected Split Completion Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Unexpected Split Completion Severity 6. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 7. 170 PCI Status register Signaled System Error bit is set if the Unexpected Split Completion Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Reverse Transparent Bridge PCI/PCI-X Originating Interface (Primary to Secondary) Data Parity Error on Split Completion Messages When a bridge detects a Data error during the Data phase of a Split Completion message, the following occurs: 1. Secondary Uncorrectable Error Status register Uncorrectable Split Completion Message Data Error Status bit is set. 2. TLP Header of the Split Completion is logged in the Secondary Header Log register and the FECh register Secondary Uncorrectable Error Pointer is updated if the Secondary Uncorrectable Error Mask register Uncorrectable Split Completion Message Data Error Mask bit is cleared and the Secondary Uncorrectable First Error Pointer is inactive. 3. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Split Completion Message Data Error Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Uncorrectable Split Completion Message Data Error Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Uncorrectable Split Completion Message Data Error Severity 4. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Secondary Uncorrectable Error Severity register Uncorrectable Split Completion Message Data Error Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Secondary Uncorrectable Error Mask register Uncorrectable Split Completion Message Data Error Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Split Completion Message Data Error Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Uncorrectable Split Completion Message Data Error Severity 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. PCI Status register Signaled System Error bit is set if the Uncorrectable Split Completion Message Data Error Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 171 Error Handling PLX Technology, Inc. 8.2.4 Reverse Transparent Bridge Timeout Errors 8.2.4.1 PCI Express Completion Timeout Errors The PCI Express Completion Timeout mechanism allows Requesters to abort a Non-Posted request if a Completion does not arrive within a reasonable time. Bridges, when acting as Initiators on the PCI Express interface on behalf of internally generated requests or when forwarding requests from a secondary interface, behave as endpoints for requests of which they assume ownership. If a Completion timeout is detected and the link is up, the PEX 8114 responds as if a Completion with Unsupported Request status was received, and the following occurs: 1. Uncorrectable Error Status register Completion Timeout Status bit is set. 2. TLP Header of the original request is logged in the Header Log register and the Advanced Error Capabilities and Control register First Error Pointer is updated if the Uncorrectable Error Mask register Completion Timeout Mask bit is cleared and the First Error Pointer is inactive. 3. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Secondary Uncorrectable Error Severity register Completion Timeout Severity bit’s severity, if the following conditions are met: – Secondary Uncorrectable Error Mask register Completion Timeout Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Completion Timeout Severity 4. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Completion Timeout Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Completion Timeout Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Completion Timeout Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Completion Timeout Severity 5. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 6. 172 PCI Status register Signaled System Error bit is set if the Completion Timeout Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 8.2.4.2 Reverse Transparent Bridge Timeout Errors PCI Delayed Transaction Timeout Errors The PEX 8114 has Delayed Transaction Discard Timers for each queued delayed transaction. If a Delayed Transaction timeout is detected, the following occurs: 1. Bridge Control register Discard Timer Status bit and Secondary Uncorrectable Error Status register Delayed Transaction Discard Timer Expired Status bit are set. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus, depending upon the Uncorrectable Error Severity register Delayed Transaction Discard Timer Expired Severity bit’s severity, if the following conditions are met: – Uncorrectable Error Mask register Delayed Transaction Discard Timer Expired Mask bit is cleared, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set, the Root Control register System Error on Fatal Error Enable or System Error on Non-Fatal Error Enable bit is set, and both bits match the Delayed Transaction Discard Timer Expired Severity 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, depending upon the Uncorrectable Error Severity register Delayed Transaction Discard Timer Expired Severity bit’s severity, if the following conditions are met: – Command register Interrupt Disable bit is cleared, and – Uncorrectable Error Mask register Delayed Transaction Discard Timer Expired Mask bit is cleared, and – Root Error Command register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Delayed Transaction Discard Timer Expired Severity, and either – PCI Command register SERR# Enable bit is set –or– – PCI Express Device Control register Fatal Error Reporting Enable or Non-Fatal Error Reporting Enable bit is set and matches the Delayed Transaction Discard Timer Expired Severity 4. Device Status register Fatal Error Detected or Non-Fatal Error Detected bit is set. 5. PCI Status register Signaled System Error bit is set if the Delayed Transaction Discard Timer Expired Mask bit is cleared and the SERR# Enable bit is set. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 173 Error Handling 8.2.5 PLX Technology, Inc. Reverse Transparent Bridge PCI Express Error Messages PCI Express devices can transmit Error messages when detecting errors that compromise system integrity. When the PEX 8114 receives Error messages on the secondary PCI Express interface, the following occurs: 1. Secondary Status register Received System Error bit is set if a Non-Fatal (ERR_NONFATAL) or Fatal (ERR_FATAL) Error message is received. 2. PCI_SERR# is asserted on the PCI/PCI-X Bus when one of the following conditions occur: – Root Control register System Error on Correctable Error Enable bit is set and a Correctable Error message (ERR_COR) is received – Root Control register System Error on Non-Fatal Error Enable bit is set and a Non-Fatal Error message (ERR_NONFATAL) is received – Root Control register System Error on Fatal Error Enable bit is set and a Fatal Error message (ERR_FATAL) is received – PCI Command and Bridge Control register SERR# Enable bits are set and a Non-Fatal Error message (ERR_NONFATAL) is received – PCI Command and Bridge Control register SERR# Enable bits are set and a Fatal Error message (ERR_FATAL) is received 3. PCI_INTA# is asserted on the PCI/PCI-X Bus –or– an MSI is transmitted if the MSI Control register MSI Enable bit is set, when one of the following conditions occur: – Root Error Command register Correctable Error Reporting Enable bit is set and a Correctable Error message (ERR_COR) is received – Root Error Command register Non-Fatal Error Reporting Enable bit is set and a Non-Fatal Error message (ERR_NONFATAL) is received – Root Error Command register Fatal Error Reporting Enable bit is set and a Fatal Error message (ERR_FATAL) is received 174 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 9 9.1 Serial EEPROM Introduction The on-bridge Serial EEPROM Controller is contained in the PEX 8114 PCI/PCI-X port, as illustrated in Figure 9-1. The controller performs a serial EEPROM download when: • A serial EEPROM is present, as indicated by the EE_PR# Strap ball = Low, and • The Configuration registers are reset to their default values. Figure 9-1. Serial EEPROM Connections to PEX 8114 PEX 8114 EE_CS# Initialization Serial EEPROM EE_DO EE_DI EE_SK Serial EEPROM Controller PCI/PCI-X Port PCI Express Port Configuration Data EE_PR# Port ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Port 175 Serial EEPROM 9.2 PLX Technology, Inc. Configuration Data Download The Serial EEPROM Controller generates an EE_SK signal by dividing the PCI_CLK by 16, resulting in a shift clock frequency up to 8.3 MHz. The Serial EEPROM Controller reads a total of 1,004 bytes, from the serial EEPROM, which represents all data necessary to initialize the PEX 8114 registers. The serial EEPROM Memory Map reflects the basic device register map. A detailed description of the serial EEPROM Memory maps is provided in Appendix A, “Serial EEPROM Map.” Note: For a PCI-X clock greater than 66 MHz, a 10-MHz serial EEPROM is needed. For clock rates of 66 MHz and lower, a 5-MHz serial EEPROM is sufficient. When registers are modified through the serial EEPROM load, the serial EEPROM must retain data for all registers. Registers that must be modified away from their power-on default states can be changed by loading the necessary modified values in the serial EEPROM, at the location that corresponds to that register’s value in the serial EEPROM map. Registers that are not intended to be modified from their default values by the serial EEPROM load must be located within the serial EEPROM loaded with the default value. Serial Peripheral Interface EEPROMs, from 8 KB up to 64 KB sizes, are supported. The minimum size required, to support the PEX 8114 register load, is 8 KB. If a serial EEPROM larger than 8 KB is used, the additional space remains unused by the PEX 8114 register load resources and is used as a general-purpose serial EEPROM. The register load data starts at Location 0 in the serial EEPROM and the serial EEPROM data is loaded into the registers, in ascending sequence, and mapped according to the register assignment tables in Appendix A, “Serial EEPROM Map.” The table is arranged with the left column listing the Configuration Space register (CSR) addresses and the right column listing the serial EEPROM address to load to modify the CSR. In a few instances, the value of a single PCI-defined or Device-Specific CSR must be stored in two separate internal registers within the PEX 8114. When writing a CSR using PCI-type Configuration Writes – Memory-Mapped Writes or Pointer Indirect Writes – the internal state machines associated with the Write, place the data in both internal registers, without intervention. When loading a CSR location that contains two internal copies of the register using serial EEPROM loads, the value must be specifically loaded into both internal registers (that is, two distinct Writes to two distinct locations are required). Therefore, in certain instances, when creating the serial EEPROM image, the value needed in a CSR must be placed in two address locations in the serial EEPROM, allowing two distinct Writes to occur. The required registers for this procedure are indicated in the register assignment tables in Appendix A, “Serial EEPROM Map,” by having two serial EEPROM addresses listed in a row that has only one corresponding CSR address. In cases where two serial EEPROM addresses must be loaded to modify one CSR location, the Data loaded into both serial EEPROM addresses must be identical or the PEX 8114’s operation is undefined. During the serial EEPROM download, the controller checks for a valid Class Code and terminates the download if a value other than 060400h is used. While downloading data, the PEX 8114 generates a CRC value from the data read. When the serial EEPROM download is completed, the generated CRC value is compared to a CRC value stored in the last DWord location of the serial EEPROM. For serial EEPROMs, the CRC value is located at serial EEPROM byte offset 03ECh. All CRC are calculated in DWords and the CRC value is also a DWord. The CRC is calculated, starting at location 0, and is calculated through one location below where the CRC is stored. The CRC polynomial is as follows: G(x) = x32 + x31 + x30 + x28 + x27 + x25 + x24 + x22 + x21 + x20 + x16 + x10 + x9 + x6 + 1 A C code sample used to generate the CRC is provided in Appendix B, “Sample C Code Implementation of CRC Generator.” 176 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Configuration Data Download When the CRC values match, the PEX 8114 sets the Serial EEPROM Status register EepPrsnt[1:0] field (offset 260h[17:16]) value to 01b (serial EEPROM download complete and serial EEPROM CRC check is correct). When the CRC check fails, the PEX 8114 sets all the registers to their default values, then sets the EepPrsnt[1:0] field to 11b, to indicate failure. Disable the CRC check by loading a value of 1 in Serial EEPROM Status register CRC Disable bit (offset 260h[21]) during the serial EEPROM load. It is the responsibility of system software to detect that the serial EEPROM download is completed without error. Serial EEPROM register Initialization data, as well as user-accessible, general-purpose space located above the register initialization data, can be modified by Writes to the PEX 8114 Device-Specific Serial EEPROM registers. The Serial EEPROM Status and Control register contains Status and Control bits that set the Read/Write address and cause status data to be written to or read from the serial EEPROM. There are 14 Address bits – EepBlkAddr and EepBlkAddrUp ((offset 260h[12:0 and 20], respectively). The addressing is at a DWord address (rather than a byte offset), which allows 16-KB DWords or 64 KB to be addressed. The Serial EEPROM Buffer register (offset 264h) contains data to be written to, or the most recent data read from, the serial EEPROM. (For further details, refer to the referenced registers in Section 14.13.2, “Device-Specific Registers – Physical Layer.”) ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 177 Serial EEPROM PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 178 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 10 10.1 Interrupt Handler Introduction The PEX 8114 includes two types of interrupts: • Conventional PCI Interrupt, PCI/PCI-X PCI_INT[D:A]#, which are PEX 8114 I/O balls on the PCI/PCI-X Bus and their analogous PCI Express Assert_Intx Virtual Interrupt messages • Message Signal Interrupt (MSI), which is conveyed with Memory Write transactions In Forward Transparent Bridge mode, Conventional PCI interrupts generated external to the PEX 8114 and asserted on the PCI_INT[D:A]# balls, when enabled, are converted by the PEX 8114 to Virtual Interrupt messages and transmitted upstream on the PCI Express interface. MSI interrupts are passed through the PEX 8114 from PCI/PCI-X to PCI Express. Interrupts generated by sources internal to the bridge can be converted to MSI Interrupt messages or Assert_IntA. In Reverse Transparent Bridge mode, the Virtual Interrupt messages received on the PCI Express interface are converted to Conventional PCI interrupt signals and driven on the PCI_INT[D:A]# balls. MSI interrupts are passed through the PEX 8114, from PCI Express to PCI/PCI-X. Interrupts generated by sources internal to the bridge can be converted to MSI interrupt or Assert_IntA and Deassert_IntA messages. 10.2 Interrupt Handler Features Interrupt handler features are as follows: • Senses internal interrupt events • Generates Virtual Interrupt messages from Conventional PCI PCI_INT[D:A]# balls • Drives Conventional PCI_INT[D:A]# balls from Virtual Interrupt messages • Signals interrupts through Virtual INTA# signaling, PCI_INT[D:A]# signal Conventional PCI assertion, or MSI ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 179 Interrupt Handler 10.3 PLX Technology, Inc. Events that Cause Interrupts Events internal to the PEX 8114 that cause interrupts are as follows: • Hot Plug events – Attention Button Pressed – Power Fault Detected – MRL Sensor Changed – Presence Detect Changed – Command Completed • Internal Error FIFO overflow • Power Management Events • PCI Express Egress Credit Update Timeout Interrupts can also be generated if the Root Error Command register (offset F94h), is implemented by software in Reverse Transparent Bridge mode. Conditions that cause these interrupts are as follows: • Correctable error message is received by the PEX 8114 from downstream and the Root Error Command register Correctable Error Reporting Enable bit is set (offset F94h[0]=1) • Non-Fatal Error message is received by the PEX 8114 from downstream and the Root Error Command register Non-Fatal Error Reporting Enable bit is set (offset F94h[1]=1) • Fatal error message is received by the PEX 8114 from downstream and the Root Error Command register Fatal Error Reporting Enable bit is set (offset F94h[2]=1) • Correctable error is detected by the PEX 8114, the PCI Command register Interrupt Disable bit is cleared, and the Root Error Command register Correctable Error Reporting Enable bit is set (offsets 04h[10]=0 and F94h[0]=1, respectively) • Non-Fatal error is detected by the PEX 8114, the PCI Command register Interrupt Disable bit is cleared and the Root Error Command register Non-Fatal Error Reporting Enable bit is set (offsets 04h[10]=0 and F94h[1]=1, respectively) • Fatal error is detected by the PEX 8114, the PCI Command register Interrupt Disable bit is cleared and the Root Error Command register Fatal Error Reporting Enable bit is set (offsets 04h[10]=0 and F94h[2]=1, respectively) Interrupt requests proceed to the Interrupt Generator module, which sets the PCI Status register Interrupt Status bit (offset 04h[19]=1). Setting the status bit causes an INTA# interrupt or MSI to generate, depending upon which interrupt is enabled. INTA# and MSI interrupt generation are mutually exclusive. 180 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 10.4 INTx# Signaling INTx# Signaling In Forward Transparent Bridge mode, the PEX 8114 converts PCI_INTx# ball interrupts to virtual PCI Express INTx# signaled interrupts. PCI/PCI-X interrupts appearing on PCI_INTx# lines are converted to PCI Express-compatible packets (Assert_INTx# and Deassert_INTx# signaled interrupts) and transmitted to the upstream port. In Reverse Transparent Bridge mode, the PEX 8114 converts PCI Express virtual INTx# signaled interrupts to PCI_INTx# interrupts. Assert_INTx# and Deassert_INTx# signaled interrupts from the PCI Express port are converted to the PCI_INTx# ball interrupts. The PEX 8114 supports the PCI r3.0 Interrupt Pin and Interrupt Line registers (offset 3Ch[15:8 and 7:0], respectively), as well as the PCI r3.0 PCI Command register Interrupt Disable and PCI Status register Interrupt Status bits (offset 04h[10, 19], respectively). Although the PCI Express r1.0a provides INT[D:A]# for PCI_INT[D:A]# interrupt signaling, the PEX 8114 uses only PCI_INTA# for internal Interrupt message generation. When MSI is disabled [MSI Control register MSI Enable bit is cleared (offset 48h[16]=0)] and INTA#-type interrupts are not disabled (PCI Command register Interrupt Disable bit (offset 04h[10]=0)], interrupt requests from a defined event generate INTA#-type interrupts. When MSI is enabled [MSI Control register MSI Enable bit is set (offset 48h[16]=1)], the interrupt requests from a defined event generate MSI type interrupts, regardless of the PCI Command register Interrupt Disable bit state. When PCI_INTA# interrupts are enabled and there is an interrupt request from interrupt sources internal to the PEX 8114, the PCI Status register Interrupt Status bit is set (offset 04h[19]=1). • Forward Transparent Bridge mode – When the Interrupt Status bit is set by an interrupt source internal to the PEX 8114, an Assert_INTA# message is transmitted on the PCI Express interface. When an external PCI-X device asserts the INTx# input to the PEX 8114, the Interrupt Status bit is not set; however, the Assert_INTx# message is translated. When the external PCI-X device later de-asserts the PCI_INTx# input, the Deassert_INTx# message is transmitted without action from the host software. • Reverse Transparent Bridge mode – When the Interrupt Status bit is set, the PCI_INTA# signal is asserted on the PCI/PCI-X Bus. When an interrupt source internal to the PEX 8114 causes an interrupt to be transmitted to the PCI Express Root Complex, the Host software reads and clears the event status after servicing the interrupt. When an interrupt source internal to the PEX 8114 causes an interrupt, the PCI device hardware clears the PCI Status register Interrupt Status bit when all event status bits are cleared, and transmits a Deassert_INTA# message on the PCI Express interface or de-asserts PCI_INTA# on the PCI/PCI-X Bus. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 181 Interrupt Handler 10.5 PLX Technology, Inc. Message Signaled Interrupts A scheme supported by PEX 8114 is the Message Signaled Interrupt (MSI), which is optional for PCI r3.0 devices, but required for PCI Express devices. The MSI method uses Memory Write transactions to deliver interrupts. MSI are edge-triggered interrupts. If MSI is enabled [MSI Control register MSI Enable bit is set (offset 48h[16]=1)] and the interrupt status bit is set, the module generates an MSI. MSI and INT[D:A]# interrupt generation are mutually exclusive. 10.5.1 MSI Capability Structure The Message Capability structure required for MSI is implemented in the Interrupt Generator module. The Capability Pointer register (defined in the PCI r3.0) contains the pointer to the Capability ID. The MSI Address, MSI Upper Address, and MSI Data registers are located at offsets Capability Pointer + 4h, Capability Pointer + 8h, and Capability Pointer + Ch, respectively. The MSI Capability registers are described in Section 14.6, “Message Signaled Interrupt Capability Registers.” 182 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 10.5.2 MSI Operation MSI Operation At configuration, system software traverses the capability list of the function. If a Capability ID of 05h is found, the function implements MSI. System software reads the Message Signaled Interrupt Capability register (offset 48h), to determine whether the PEX 8114 is set up to support MSI. Because the PEX 8114 supports only one message for MSI, the MSI Control register Multiple Message Enable and Multiple Message Capable fields (offset 48h[22:20, 19:17], respectively) are always cleared to 000b. System software initializes the MSI Control register MSI 64-Bit Address Capable bit (offset 48h[23]): • When set, the Message Address field is 64 bits • When cleared, the Message Address field is 32 bits Note: The MSI Address register (offset 4Ch) is the lower 32 bits of the Message Address field. The MSI Upper Address register (offset 50h) is the upper 32 bits of the Message Address field. System software initializes the MSI Data register (offset 54h) with a system-specified message. The MSI Control register MSI Enable bit is cleared after reset, and software must set the bit if the system supports the MSI scheme. After the bit is enabled, the module performs a DWord Memory Write to the address specified by the MSI Address register contents. The two lower bytes of data written are taken from the contents of the two lower bytes of the MSI Data register. The upper two bytes of data are zero (0). Because the Multiple Message Enable field is always cleared to 000b, the module is not permitted to change the low order bits of message data to indicate a multiple message vector, and all MSI Data register data bits are directly copied to the data. After the PCI Status register Interrupt Status bit (offset 04h[19] is set and a message generated, the module does not generate another message until the system services the interrupt and clears the event status bits. The module hardware clears the Interrupt Status bit when all event status bits are cleared. 10.6 Remapping INTA# Interrupts The PEX 8114 does not perform interrupt remapping, due to its single internal register-set topology. When the PEX 8114 acts as a Forward bridge, interrupt lines INTA_ INTB_, INTC_, and INTD_ are routed straight through the PEX 8114 and converted into De-assert Interrupt and Assert Interrupt A, B, C, and D packets, respectively, on the PCI Express side of the bridge. When PEX 8114 acts as a Reverse bridge, each assert A, B, C, and D interrupt and de-assert interrupt packet causes the interrupt A, B, C, and D lines, respectively, to assert and de-assert. Refer to the PCI Express-to-PCI/PCI-X Bridge r1.0, Section 8.2, for an explanation of routing for Option A bridges. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 183 Interrupt Handler PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 184 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 11 11.1 PCI/PCI-X Arbiter Introduction The PCI/PCI-X Arbiter efficiently manages accesses to the PCI/PCI-X Bus shared by multiple Masters. It is not required that all systems provide equal bus access to all Masters. In reality, most systems require certain Masters be granted greater access to the bus than others. This is the case for systems with an embedded processor. It is assumed that the bus access requirements for all Masters in a system are known. It is possible to program the bus access requirements to meet system needs. 11.2 Arbiter Key Features The key features of the PCI/PCI-X Arbiter are as follows: • Arbiter supports up to five PCI-X or Conventional PCI devices (four external and one internal) • Bus allocation is programmable in 10% increments • Park bus on latest Master • Enable/disable Arbiter (by way of STRAP_ARB ball) • Address stepping on Configuration cycles • Asserts grants in two ways: – Standard PCI/PCI-X-compliant grants during accesses – Wait for idle bus to issue grant ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 185 PCI/PCI-X Arbiter 11.3 PLX Technology, Inc. Functional Block Diagram At any time, more than one PCI/PCI-X Bus Master can assert its specific PCI_REQ[3:0]# signal and request PCI/PCI-X Bus ownership. The Arbiter determines which PCI/PCI-X devices acquire bus ownership by asserting the specific device PCI_GNT[3:0]# signal. Figure 11-1 illustrates the relationship between the PCI/PCI-X devices and PCI/PCI-X Arbiter. Figure 11-1. Internal PCI Arbiter Top-Level Diagram PCI_REQ0# PCI/PCI-X Device 0 PCI_GNT0# PCI_REQ1# PCI/PCI-X Device 1 PCI_GNT1# Internal PCI Arbiter PCI_REQ2# PCI/PCI-X Device 2 PCI_GNT2# PCI_REQ3# PCI/PCI-X Device 3 PCI_GNT3# PCI_RST# PCI_CLK 186 STRAP_ARB PCI_IRDY# PCI_FRAME# ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 11.4 Arbiter Usage Arbiter Usage Figure 11-2 illustrates PCI/PCI-X Arbiter use in a PEX 8114 application. In this illustration, four Request/Grant pairs are used only when the Arbiter is enabled. Another active Request/Grant pair is shown, regardless of whether the Arbiter is enabled. The pair interfaces with the External Arbiter as PCI_REQ# when the Arbiter is disabled. The pair acts as PCI_REQ0# when the Arbiter is enabled. Figure 11-2. PEX 8114 Internal PCI Arbiter Usage PEX 8114 REQn3_IN GNTn3_OUT REQn4 GNTn4 REQn2_IN GNTn2_OUT REQn3 GNTn3 REQn1_IN GNTn1_OUT REQn2 GNTn2 REQn0_IN GNTn0_OUT Internal PCI Arbiter REQn1 GNTn1 REQn0 GNTn0 STRAP_ARB REQn_INT REQn_OUT GNTn_IN 0 GNTn_INT 1 STRAP_ARB Strapping Ball ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 187 PCI/PCI-X Arbiter 11.5 PLX Technology, Inc. External Bus Functional Description The PCI/PCI-X Arbiter is designed to arbitrate the bus requests of up to four PCI/PCI-X Master devices on the PCI/PCI-X Bus. The PCI-X Bus includes several enhancements that enable faster and more efficient Data transfers than the PCI Local Bus allowed, at PCI-X Bus clock frequencies up to 133 MHz. Because of these higher clock rates, register all inputs and outputs. Registering Request signals by the Arbiter should in no way limit its usage to PCI-X Bus applications. It is backward-compatible with the PCI Bus and functions as an arbiter in the PCI environment. Note: Registering of an arbiter signal is performed in compliance to the PCI-X r2.0a. No additional requirements are implied herein. 11.6 Detailed Functional Description Arbitration is necessary if more than one Master simultaneously requests the bus. When only one Master is requesting the bus and the bus is idle, the requesting bus receives the grant if it is allowed at least one Configuration register assignment. The PEX 8114 can be configured as a Slave to an external arbiter, or function as the PCI Bus Arbiter supporting up to four external PCI Bus Requesters and the PEX 8114’s internal request. The PCI Arbiter registers (offsets FA8h, FACh, and FB0h), in conjunction with the STRAP_ARB ball, control PEX 8114 arbitration characteristics. When STRAP_ARB is grounded, the PEX 8114 functions as a Slave to the External Arbiter. When functioning as a Slave to the External Arbiter, the PEX 8114 requests access to the PCI Bus by asserting PCI_REQ#, and receives grants from the External Arbiter on the PCI_GNT# ball. The three PCI Arbiter registers are divided into ten, three-bit Arbiter Allocation sub-registers. When the Arbiter is enabled, the PCI Bus bandwidth is distributed in 10% increments, by loading the Allocation sub-registers with the value that represents an external or internal arbitration contender. Table 11-1 defines the bandwidth allocations that occur when one of the 10 Arbiter Allocation sub-registers are set or cleared to the values listed. It is not required that the Requester values be evenly distributed in the allocation sub-registers to achieve the proper bus percentage, or to achieve random bus allocation. The register power-on default values provide equal bandwidth distribution among the Requesters. Typically, the Arbiter Allocation sub-registers are set at initialization; however, they can be modified at any time. If the value representing a Request ball is not loaded into an arbitration allocation sub-register, that Requester is not granted access to the PCI Bus. If all arbitration allocation sub-registers are loaded with the same Requester ID, all PCI Bus bandwidth is allocated to that Requester. Table 11-1. Arbiter Allocation Subregister Values and Bandwidth Allocation Arbiter Allocation Subregister Value 000b Allocates 10% of the bus bandwidth to internal requests. 001b Allocates 10% of the bus bandwidth to the PCI_REQ0# input. 010b Allocates 10% of the bus bandwidth to the PCI_REQ1# input. 011b Allocates 10% of the bus bandwidth to the PCI_REQ2# input. 100b Allocates 10% of the bus bandwidth to the PCI_REQ3# input. 101b and higher 188 Bandwidth Allocation Effectively removes that Arbiter Allocation sub-register from the set of usable registers (for example, if five of the Arbiter Allocation sub-registers are loaded with 111b, each of the remaining five Allocation sub-registers represent 20% of the bus bandwidth). ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 11.6.1 Bus Parking Bus Parking The Arbiter is designed to implement bus parking when there are no pending requests (bus idle). In this case, the Arbiter allows the Grant signal for the last Master to remain active. This ensures that if the last Master requested the bus again, it receives an immediate grant; however, if another Master requests the bus, the Arbiter causes all grants to go High before issuing a new grant. 11.6.2 Hidden Bus Arbitration The PCI r3.0 allows bus arbitration to occur while the currently granted device is performing a Data transfer. This feature greatly reduces arbitration overhead and improves bus utilization. Hidden arbitration occurs if the control register Grant_mode has a value of 1; otherwise, arbitration occurs when the bus is idle. Idle bus arbitration supports Conventional PCI devices. 11.6.3 Address Stepping The PEX 8114’s Internal PCI Arbiter supports address stepping. To acquire maximum PCI Bus utilization, the Arbiter removes a grant from a device that requests the bus if it fails to start a transaction on the bus within a specified minimum number of PCI_CLK cycles. In PCI-X mode high-frequency operation, when several devices are connected to the high-order Address lines, the AD bus can be slow to settle when a device is trying to drive a Configuration cycle on the bus. To accommodate these slow transitions during configurations, a Configuring Master can delay PCI_FRAME# assertion one extra cycle, to allow the AD Bus lines sufficient time to settle. The PCI_FRAME# delayed assertion is called address stepping. When a Configuring Master delays PCI_FRAME# assertion, if the Master is used with a high-performance Arbiter, the Arbiter can remove the Grant signal when the Configuring Master starts to assert PCI_FRAME#. Address stepping forces the Arbiter to allow one extra Clock cycle for the device that is driving the configuration to assert PCI_FRAME# before removing the grant. The Address Stepping Enable bit (offset FA0h[13]) controls PEX 8114 Address stepping. At reset, the bit is cleared to 0 and address stepping is disabled. Setting the Address Stepping Enable bit causes the Arbiter to delay grant removal during PCI-X Configuration cycles. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 189 PCI/PCI-X Arbiter PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 190 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 12 12.1 Hot Plug Support Hot Plug Purpose and Capability Note: The PEX 8114’s Hot Plug Controller is compliant with the Hot Plug r1.0 and PCI Standard Hot Plug Controller and Subsystem r1.0. Hot Plug capability allows orderly insertion and extraction of boards from a running system, without adversely affecting the system. Board insertion or extraction, without system down time, is performed when repair of a faulty board or system reconfiguration becomes necessary. Hot Plug capability also allows systems to isolate faulty boards in the event of a failure. The PEX 8114 includes a Hot Plug Controller capable of supporting Hot Plugging of a downstream PCI Express link. Therefore, the Hot Plug Controller is used when the PEX 8114 is in Reverse Transparent Bridge mode. PCI/PCI-X Hot Plug is not supported. Do not use the PEX 8114 to support Hot Plug in Forward Transparent Bridge mode. 12.1.1 Hot Plug Controller Capability • Insertion and removal of PCI Express boards, without removing system power • Hot Plug Controller function • Board Present and Manually operated Retention Latch (MRL) Sensor signal support • Power Indicator and Attention Indicator Output signal controlled • Attention Button monitored • Power fault detection and Faulty board isolation • Power switch for controlling downstream device power • Generates PME for a Hot Plug event in a sleeping system (D3hot Device PM state) • Presence detect is achieved through an in-band SerDes Receiver Detect mechanism or by the HP_PRSNT# signal 12.1.2 Hot Plug Port External Signals The PEX 8114 Hot Plug Controller signals are defined in Section 2.5, “Hot Plug Signals.” ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 191 Hot Plug Support 12.1.3 PLX Technology, Inc. Hot Plug Typical Hardware Configuration Figure 12-1 illustrates a typical system-level hardware configuration using the PEX 8114 to provide Hot Plug support in Reverse Transparent Bridge mode. Figure 12-1. Hot Plug Typical Hardware Configuration for Reverse Transparent Bridge Mode Application PCI_PME# or PCI_INTA# PCI Host PEX 8114 Reverse Bridge Hot Plug Power Fault HP_ATNLED# HP_BUTTON# HP_PWRLED# HP_MRL# HP_PWREN# HP_PWRFLT# HP_CLKEN# HP_PRSNT# HP_PERST# Attention Button Attention LED PCI Express Device Hot Plug Controller Manually operated Retention Latch (MRL) Power LED Hot Plug Express Add-In Board 192 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 12.2 PCI Express Capability Registers for Hot Plug PCI Express Capability Registers for Hot Plug The Hot Plug Configuration, Capability, Command, Status, and Events are described in Section 14.8, “PCI Express Capability Registers.” The applicable registers are as follows: • Slot Capability (offset 7Ch) • Slot Status and Control (offset 80h) 12.2.1 Hot Plug Interrupts The Hot Plug Controller supports Hot Plug interrupt generation on the following events: – Attention Button Pressed – Power Fault Detected – MRL Sensor Changed – Presence Detect Changed – Command Completed Depending upon the PEX 8114 downstream PCI Express port power state, a Hot Plug event can generate a system interrupt or PME. When the PEX 8114 downstream PCI Express port is in the D0 Device PM state, Hot Plug events generate a system interrupt; when not in the D0 Device PM state, a PME interrupt is generated on Hot Plug events. The Command Completed bit does not generate a PME interrupt. When the system is in Sleep mode, Hot Plug operation causes a system wakeup using PME logic. 12.3 Hot Plug Insertion and Removal Process This section describes two aspects of the Hot Plug insertion and removal process. The first describes the operator actions required for safe removal of a Hot Plug board. The next sections detail the sequence of events that occur in hardware (Hot Plug Controller) and in software. 12.3.1 Operator Actions for Hot Plug Insertion/Removal The sequence of actions taken by the operator to insert and remove a Hot Plug board are as follows. To insert a board: 1. Insert the board and lock the MRL. 2. Press the Attention button, to notify the system that a board has been inserted. 3. Verify that the Power LED blinks, then turns On (indicating that the board is ready for use). To remove a board: 1. Press the board’s Attention Button or enter the proper command on the Host console. 2. Verify that the Attention LED blinks. 3. Verify that the Power LED turns Off, indicating that the board can be safely removed. 4. Disengage the MRL switch, then remove the board. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 193 Hot Plug Support 12.3.2 PLX Technology, Inc. Hot Plug Insertion – Hardware and Software Process Table 12-1 defines the sequence of events in hardware and software for the board insertion procedure supported by the PEX 8114. Table 12-1. Hot Plug Board Insertion Process Operator / Action A. Place board in slot Hot Plug Controller Software 1. Sets Presence Detect State bit to 1. 2. Sets Presence Detect Changed to 1. 3. Asserts PCI_INTA#, if enabled. Clears Presence Detect Changed bit to 0. 4. De-asserts PCI_INTA#. B. Lock MRL 5. Clears MRL Sensor Present bit to 0. 6. Sets MRL Sensor Changed bit to 1. 7. Asserts PCI_INTA#, if enabled. Clears MRL Sensor Changed bit to 0. 8. De-asserts PCI_INTA#. C. Press Attention Button 9. Sets Attention Button Present bit to 1. 10. Asserts PCI_INTA#, if enabled. Clears Attention Button Present bit to 0. 11. De-asserts PCI_INTA#. Writes to the Slot Control register Power Indicator Control field, to blink the power LED, to indicate that the board is being powered up. Continued … D. Power Indicator blinks 12. Sets Power Indicator Control field to 10b. 13. Transmits Power Indicator Blink message downstream. 14. Sets Command Completed bit to 1. 15. Asserts PCI_INTA#, if enabled. Clears Command Completed bit to 0. 16. De-asserts PCI_INTA#. Clears the Slot Control register Power Controller Control field, to turn On power to the port. 17. Slot is powered up. 18. After a Tpepv delay, sets Command Completed bit to 1. 19. Asserts PCI_INTA#, if enabled. Clears Command Completed bit to 0. 20. De-asserts PCI_INTA#. Writes to the Slot Control register Power Indicator Control field, to turn On the Power Indicator LED, which indicates that the slot is fully powered On. E. Power Indicator On 21. Sets Power Indicator Control field to 01b. 22. Asserts PCI_INTA#, if enabled. Clears Command Completed bit to 0. 23. De-asserts PCI_INTA#. 194 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 12.3.3 Hot Plug Removal – Hardware and Software Process Hot Plug Removal – Hardware and Software Process Table 12-2 defines the sequence of events in hardware and software for the board removal procedure supported by the PEX 8114. Table 12-2. Hot Plug Board Removal Process Operator / Action A. Press Attention Button. Hot Plug Controller 1. Sets Attention Button Present bit to 1. 2. Asserts PCI_INTA#, if enabled. 3. If the Attention Button is present on the downstream device, receives the Attention Button message, and sets the Attention Button Present bit to 1. Software Clears Attention Button Present bit to 0. 4. De-asserts PCI_INTA#. Writes to the Slot Control register Power Indicator Control field, to blink the Power Indicator LED, which indicates that the board is being powered down. B. Power Indicator blinks 5. Sets Power Indicator Control field to 10b. 6. Transmits Power Indicator Blink message downstream. 7. Sets Command Completed bit to 1. 8. Asserts PCI_INTA#, if enabled. Clears Command Completed bit to 0. 9. De-asserts PCI_INTA#. Sets the Slot Control register Power Controller Control bit to 1, to turn Off power to the port. C. Power Indicator Off 10. Slot is powered Off. 11. After a Tpepv delay, sets Command Completed bit to 1. 12. Asserts PCI_INTA#, if enabled. Clears Command Completed bit to 0. Clears Power Indicator Control field to 00b, to turn Off the Power Indicator LED, which indicates that the slot is fully powered Off and the board can be removed. 13. De-asserts PCI_INTA#. D. Power Indicator Off, board ready to be removed. 14. Clears Power Indicator Control field to 00b. 15. Sets Command Completed bit to 1, due to Power Indicator Off command completion. Clears Command Completed bit to 0. 16. De-asserts PCI_INTA#. E. Unlock MRL 17. Sets MRL Sensor Present bit to 1. 18. Sets MRL Sensor Changed bit to 1. 19. Asserts PCI_INTA#, if enabled. Clears MRL Sensor Changed bit to 0. 20. De-asserts PCI_INTA#. F. Remove board from slot 21. Clears Presence Detect State bit to 0. 22. Sets Presence Detect Changed bit to 1. 23. Asserts PCI_INTA#, if enabled. Clears Presence Detect Changed bit to 0. 24. De-asserts PCI_INTA#. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 195 Hot Plug Support PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 196 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 13 13.1 Power Management Power Management Capability The PEX 8114 Power Management (PM) module interfaces with different areas of the PEX 8114 to reduce power consumption during idle periods. The PEX 8114 supports hardware-autonomous Power Management and software-driven D-State Power Management. It supports the L0s and L1 Link PM states in Hardware-Autonomous Active State PM. It also supports the L1, L2/L3 Ready, and L3 Link PM states in Conventional PCI-compatible Power Management states. D0, D3hot, and D3cold Device PM states and B0 PCI Bus power state are supported in Conventional PCI-compatible Power Management. Because the PEX 8114 does not support Aux-Power, PME generation in the D3cold Device PM state is not supported. In Forward Transparent Bridge mode, the PM module interfaces with the Physical Layer electrical sub-block, to transition the Link State into low-power states when it receives a power state change request from an upstream PCI Express component, or when an internal event forces the link state entry into low-power states in Hardware-Autonomous PM (Active Link State PM) mode. PCI Express link states are not directly visible to Conventional PCI Bus Driver software, but are derived from the Power Management state of the components residing on those links. 13.2 Power Management Capability Summary 13.2.1 General Power Management Capability • Link Power Management State (Link PM States) – PCI Express Power Management – L1, L2/L3 Ready, and L3 Link PM states (AUX power is not supported) – Active State Power Management – L0s and L1 Link PM states – B0 PCI Bus power state • Device Power Management State (Device PM States) – D0 (uninitialized and active) support – D3 (hot and cold) support • Power Management Event (PCI_PME#) support in D0 and D3hot • Power Management Data register is supported through serial EEPROM load 13.2.2 Forward Bridge-Specific Power Management Capability • PME message generation on the PCI Express link caused by PCI_PME# assertion on the PCI Bus in Forward Transparent Bridge mode. • PEX 8114 has no internal sources that generate PME messages in Forward Transparent Bridge mode. That is, there is no Forward Transparent Bridge mode PCI Bus Hot Plug support. Therefore, all PME messages result from downstream devices asserting PCI_PME# input to the PEX 8114. • Only the PCI D0 and D3 Device PM states and B0 PCI Bus power state are supported in Forward Transparent Bridge mode. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 197 Power Management 13.2.3 PLX Technology, Inc. Reverse Transparent Bridge-Specific Power Management Capability • Power Management events due to Hot Plug events in Reverse Transparent Bridge mode only (PCI Hot Plug is not supported). • Assert PCI_PME# on the upstream PCI Bus: – Upon receiving a PME message from the PCI Express downstream device, if the PME signaling bit in the Power Management Status and Control register is enabled. The PCI_PME# signal is de-asserted when the PME Status or Enable bits are cleared, according to the PCI Power Mgmt. r1.2. – Caused by a PEX 8114 internal Hot Plug event. • Generate a PME_Turn_Off message to the PCI Express downstream devices when the bridge is requested to be placed into the D3 Device PM state. After generating the PME_Turn_Off message, the PEX 8114 waits for the PME_ACK message to return prior to entering the D3 Device PM state. 13.2.4 Device Power Management States The PEX 8114 supports the PCI Express PCI-PM D0, D3hot, and D3cold (no VAUX) Device PM states. The D1 and D2 Device PM states, which are optional in the PCI Express r1.0a, are not supported. 13.2.4.1 D0 Device PM State The D0 Device PM state is divided into two distinct substates, “uninitialized” and “active.” When power is initially applied to the PCI Express bridge, it enters the D0_uninitialized Device PM state. The component remains in the D0_initialized Device PM state until the serial EEPROM loading and initial link training are complete. A device enters the D0_active Device PM state when a: • Single Memory Access Enable occurs • Combination of the following bits are set by system software: – PCI Command register I/O Access Enable bit (offset 04h[0]) – PCI Command register Memory Access Enable bit (offset 04h[1]) – PCI Command register Bus Master Enable bit (offset 04h[2]) 13.2.4.2 D3hot Device PM State A device in the D3hot Device PM state must be able to respond to Configuration accesses, allowing it to transition by software to the D0_uninitialized Device PM state. Once in D3hot Device PM state, the device can be transitioned into the D3cold Device PM state by removing power from the device. In the D3hot Device PM state, Hot Plug operations cause a PME. 13.2.4.3 D3cold Device PM State The PEX 8114 transitions to the D3cold Device PM state when its power is removed. Re-applying power causes the device to transition from the D3cold Device PM state into the D0_uninitialized Device PM state. The D3cold Device PM state assumes that all previous context is lost; therefore, software must save the necessary context while the device is in the D3hot Device PM state. 198 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 13.2.5 Link Power Management States Link Power Management States Link Power Management state is determined by the D-state of its downstream link. The PEX 8114 maintains its PCI Express link in the L0 Link PM state when it operates in standard operational mode (PCI PM state is in the D0_active Device PM state). Active State Power Management (ASPM) defines a protocol for components in the D0 Device PM state to reduce link power, by placing their links into a low-power state, and instructs the other end of the link to do likewise. This capability allows hardwareautonomous dynamic-link power reduction beyond what is achievable by software-only Power Management. Table 13-1 defines the relationship between the PEX 8114 device power state and its downstream link. Table 13-1. Connected Link Components Power States Downstream Component Device PM State PEX 8114 Device PM State L0 D0 D1 D0 L0s, L1 (optional) L1 D2 a. Permissible Interconnect Link PM State Power Saving Actions Full power. PHY Transmit lanes are operating in high-impedance state. D3hot D0 or D3hota L1, L2/L3 Ready PHY Transmit lanes are operating in high-impedance state. FC and DLL ACK/NAK Timers suspended. PLL can be disabled. D3cold (no AUX Power) D0, D3hot, or D3cold L3 Link-Off State No power to component. The PEX 8114 initiates a Link-state transition of its upstream port to the L1 Link PM state when the port is programmed to the D3hot Device PM state. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 199 Power Management 13.2.6 PLX Technology, Inc. PCI Express Power Management Support The PEX 8114 supports PCI Express features that are required or important for PCI Express Bridge Power Management. Table 13-2 defines the supported and non-supported features, and the register bits used for activating feature configuration. Reserved bits are not listed. Note: Power Management is not supported in PCI-X mode. Table 13-2. Supported PCI Express Power Management Capabilities Register Offset Bit(s) Description Supported Yes No Power Management Capability 40h 7:0 Capability ID Set to 01h, indicating that the data structure currently being pointed to is the PCI Power Management data structure. ✔ 15:8 Next Capability Pointer Default 48h points to the Message Signaled Interrupt Capability structure. ✔ 18:16 Version Default 011b indicates compliance with the PCI Power Mgmt. r1.2. ✔ 19 PME Clock Set to 1, as required by the PCI Express Base 1.0a. ✔ 21 Device-Specific Initialization Default 0 indicates that Device-Specific Initialization is not required. ✔ 24:22 AUX Current Default 000b indicates that the PEX 8114 does not support Auxiliary Current requirements. ✔ 25 D1 Support Default 0 indicates that the PEX 8114 does not support the D1 Device PM state. ✔ 26 D2 Support Default 0 indicates that the PEX 8114 does not support the D2 Device PM state. ✔ 31:27 200 PME Support Default 1100_1b indicates that the PEX 8114 forwards PME messages in the D0, D3hot, and D3cold Device PM states. ✔ ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Power Management Support Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Description Bit(s) Supported Yes No Power Management Status and Control Power State Used to determine the current Device PM state, and to set the PEX 8114 into a new Device PM state. 1:0 00b = D0 01b = Not supported 10b = Not supported 11b = D3hot ✔ If software attempts to write an unsupported state to this field, the Write operation completes normally; however, the data is discarded and no state change occurs. 3 No Soft Reset When set to 1, indicates that devices transitioning from the D3hot to D0 Device PM state, because of Power State commands, do not perform an internal reset. ✔ PME Enable 8 0 = Disables PME generation by the PEX 8114a 1 = Enables PME generation by the PEX 8114 Data Select Initially writable by serial EEPROM only. After a Serial EEPROM Write occurs to this register, RW for all CSR accesses.b Bits [12:9] select the Data and Data Scale registers. 44h 12:9 0h = D0 Device PM state power consumed 3h = D3hot Device PM state power consumed 4h = D0 Device PM state power dissipated 7h = D3hot Device PM state power dissipated ✔ ✔ ✔ RO for hardware auto-configuration. Data Scale 14:13 15 Writable by serial EEPROMb. Indicates the scaling factor to be used when interpreting the value of the Data register. The value and meaning of this field varies, depending upon which data value is selected by bits [12:9] (Data Select). There are four internal Data Scale registers (one each per Data register – 0, 3, 4 and 7). Bits [12:9], Data Select, select the Data Scale register. PME Status 0 = PME is not generated by the PEX 8114a 1 = PME is being generated by the PEX 8114 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved ✔ ✔ 201 Power Management PLX Technology, Inc. Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Bit(s) Description Supported Yes No Power Management Control/Status Bridge Extensions 22 B2/B3 Support Cleared to 0, as required by the PCI Power Mgmt. r1.2. ✔ 23 Bus Power/Clock Control Enable Cleared to 0, as required by the PCI Power Mgmt. r1.2. ✔ 44h Power Management Data 31:24 Data Writable by serial EEPROM onlyb. There are four internal Data registers. Bits [12:9], Data Select, select the Data register. ✔ a. Because the PEX 8114 does not consume auxiliary power, this bit is not sticky, and is cleared to 0 at power-on reset. b. Without serial EEPROM, Reads return 00h for Data Scale and Data registers (for all Data Selects). 202 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Power Management Support Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Description Bit(s) Supported Yes No Device Capability 8:6 Endpoint L0s Acceptable Latency Because the PEX 8114 is a bridge and not an endpoint, it does not support this feature. ✔ 000b = Disables the capability 11:9 Endpoint L1 Acceptable Latency Because the PEX 8114 is a bridge and not an endpoint, it does not support this feature. ✔ 000b = Disables the capability 12 Attention Button Present Valid only in Forward Transparent Bridge mode. For the PEX 8114 PCI Express interface, value of 1 indicates that an Attention Button is implemented on that adapter board. The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0, indicating that an Attention Button is not present on an adapter board for which the PEX 8114 provides the system interface. ✔ 13 Attention Indicator Present Valid only in Forward Transparent Bridge mode. For the PEX 8114 PCI Express interface, value of 1 indicates that an Attention Indicator is implemented on the adapter board. The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0, indicating that an Attention Indicator is not present on an adapter board for which the PEX 8114 provides the system interface. ✔ 14 Power Indicator Present Valid only in Forward Transparent Bridge mode. For the PEX 8114 PCI Express interface, value of 1 indicates that a Power Indicator is implemented on the adapter board. The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0, indicating that a Power Indicator is not present on an adapter board for which the PEX 8114 provides the system interface. ✔ Captured Slot Power Limit Value Valid only in Forward Transparent Bridge mode. The upper limit on power supplied by the slot to the PEX 8114 is determined by multiplying the value in this field by the value in field [27:26] (Captured Slot Power Limit Scale). ✔ 6Ch 25:18 Captured Slot Power Limit Scale Valid only in Forward Transparent Bridge mode. The upper limit on power supplied by the slot to the PEX 8114 is determined by multiplying the value in this field by the value in field [25:18] (Captured Slot Power Limit Value). 27:26 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved ✔ 203 Power Management PLX Technology, Inc. Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Description Bit(s) Supported Yes No Device Control 10 70h AUX Power PM Enable Cleared to 0. ✔ Device Status 20 AUX Power Detected Cleared to 0. ✔ Link Capability Active State Power Management (ASPM) Support Active State Link PM support. Indicates the level of ASPM supported by the PEX 8114. 11:10 74h 14:12 00b = Reserved 01b = L0s Link PM state entry is supported 10b = L1 Link PM state entry is supported 11b = L0s and L1 Link PM states are supported L0s Exit Latency Indicates the L0s Link PM state exit latency for the given PCI Express link. The value reported indicates the length of time that the PEX 8114 requires to complete the transition from the L0s to L0 Link PM state. ✔ ✔ 101b = PEX 8114 L0s Link PM state Exit Latency is between 1 and 2 µs 17:15 L1 Exit Latency Indicates the L1 Link PM state exit latency for the given PCI Express link. The value reported indicates the length of time that the PEX 8114 requires to complete the transition from the L1 to L0 Link PM state. ✔ 101b = PEX 8114 L1 Link PM state Exit Latency is between 16 and 32 µs Link Control Active State Power Management (ASPM) Control 78h c. 204 1:0 00b = Disables L0s and L1 Link PM state Entries for the PEX 8114 PCI Express portc 01b = Enables only L0s Link PM state Entry 10b = Enables only L1 Link PM state Entry 11b = Enables both L0s and L1 Link PM state Entries ✔ The port receiver must be capable of entering the L0s Link PM state, regardless of whether the state is disabled. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Power Management Support Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Description Bit(s) Supported Yes No Slot Capability (Reverse Transparent Bridge Mode Only) 0 Attention Button Present 0 = Attention Button is not implemented 1 = Attention Button is implemented on the slot chassis of the PEX 8114 PCI Express interface ✔ 1 Power Controller Present 0 = Power Controller is not implemented 1 = Power Controller is implemented for the slot of the PEX 8114 PCI Express interface ✔ 2 MRL Sensor Present 0 = MRL Sensor is not implemented 1 = MRL Sensor is implemented on the slot chassis of the PEX 8114 PCI Express interface ✔ 3 Attention Indicator Present 0 = Attention Indicator is not implemented 1 = Attention Indicator is implemented on the slot chassis of the PEX 8114 PCI Express interface ✔ 4 Power Indicator Present 0 = Power Indicator is not implemented 1 = Power Indicator is implemented on the slot chassis of the PEX 8114 PCI Express interface ✔ 5 Hot Plug Surprise 0 = No device in the PEX 8114 PCI Express interface slot is removed from the system without prior notification 1 = Device in the PEX 8114 PCI Express interface slot can be removed from the system without prior notification ✔ 6 Hot Plug Capable 0 = PEX 8114 PCI Express interface slot is not capable of supporting Hot Plug operations 1 = PEX 8114 PCI Express interface slot is capable of supporting Hot Plug operations ✔ Slot Power Limit Value The maximum power available from the PEX 8114 PCI Express interface is determined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by field [16:15] (Slot Power Limit Scale). ✔ 7Ch 14:7 Slot Power Limit Scale The maximum power available from the PEX 8114 PCI Express interface is determined by multiplying the value in this field by the value specified in field [14:7] (Slot Power Limit Value). 16:15 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved ✔ 205 Power Management PLX Technology, Inc. Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Bit(s) Description Supported Yes No Slot Control (Reverse Transparent Bridge Mode Only) 1 Power Fault Detector Enable 0 = Function is disabled 1 = Enables a Hot Plug Interrupt or Wakeup event on a Power Fault Detected event on the PEX 8114 PCI Express port ✔ Power Indicator Control Controls the Power Indicator on the PEX 8114 PCI Express port slot. 9:8 80h 00b = Reserved – Writes are ignored 01b = Turns On indicator to constant On state 10b = Causes indicator to Blink 11b = Turns Off indicator ✔ Writes cause the PEX 8114 PCI Express port to transmit the appropriate Power Indicator message. Reads return the PEX 8114 PCI Express port Power Indicator’s current state. 10 Power Controller Control Controls the PEX 8114 PCI Express port Slot Power Controller. 0 = Turns On the Power Controller; requires some delay to be effective 1 = Turns Off the Power Controller ✔ Slot Status (Reverse Transparent Bridge Mode Only) 17 Power Fault Detected Set to 1 when the PEX 8114 PCI Express port Slot Power Controller detects a Power Fault at the slot. ✔ Power Budget Extended Capability 138h 15:0 Extended Capability ID Set to 0004h, as required by the PCI Express Base 1.0a. ✔ 19:16 Capability Version Set to 1h, as required by the PCI Express r1.0a. ✔ 31:20 Next Capability Offset Set to 148h, which addresses the Virtual Channel Extended Capability structure. ✔ Data Select 13Ch 206 7:0 Data Select Indexes the Power Budget Data reported by way of eight Power Budget Data registers and selects the DWord of Power Budget Data that appears in each Power Budget Data register. Index values start at 0, to select the first DWord of Power Budget Data; subsequent DWords of Power Budget Data are selected by increasing index values 1 to 7. ✔ ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Power Management Support Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Description Bit(s) Supported Yes No Power Budget Data 7:0 Base Power Eight registers. Specifies (in Watts) the base power value in the operating condition. This value must be multiplied by the Data Scale to produce the actual power consumption value. Data Scale Specifies the scale to apply to the Base Power value. The power consumption of the device is determined by multiplying the Base Power field contents with the value corresponding to the encoding returned by this field. 9:8 12:10 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x PM Sub-State 000b = PEX 8114 is in the default Power Management sub-state ✔ ✔ ✔ PM State Current Device Power Management (PM) state. 14:13 140h 00b = D0 Device PM state 11b = D3 Device PM state ✔ All other encodings are reserved. Type Type of operating condition. 17:15 000b = PME Auxiliary 001b = Auxiliary 010b = Idle 011b = Sustained 111b = Maximum ✔ All other encodings are reserved. Power Rail Power Rail of operating condition. 20:18 000b = Power 12V 001b = Power 3.3V 010b = Power 1.8V 111b = Thermal ✔ All other encodings are reserved. Note: There are eight registers that can be programmed by way of the serial EEPROM. Each register has a different port power configuration. Each configuration is selected by writing to the Data Select register Data Select field (offset 13Ch[7:0]) ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 207 Power Management PLX Technology, Inc. Table 13-2. Supported PCI Express Power Management Capabilities (Cont.) Register Offset Description Bit(s) Supported Yes No Power Budget Capability 144h 0 System Allocated 1 = Power budget for the device is included within the system power budget ✔ Power Management Hot Plug User Configuration 0 1 2 0 = Idle condition lasts for 1 µs 1 = Idle condition lasts for 4 µs L1 Upstream Port Receiver Idle Count For active L1 Link PM state entry. 0 = Upstream port receiver idle for 2 µs 1 = Upstream port receiver idle for 3 µs HPC PME Turn-Off Enable 1 = PME Turn-Off message is transmitted before the port is turned Off on a downstream port ✔ ✔ ✔ HPC Tpepv Delay Slot power-applied to power-valid delay time. 1E0h 4:3 5 6 208 L0s Entry Idle Count Time to meet to enter the L0s Link PM state. 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms HPC Inband Presence Detect Enable 0 = HP_PRSNT# Input ball used to detect whether a board is present in the slot 1 = SerDes Receiver Detect mechanism is used to detect whether a board is present in the slot HPC Tpvperl Delay Downstream port power-valid to Reset signal release time. 0 = 20 ms 1 = 100 ms (default) ✔ ✔ ✔ ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 14 14.1 Registers Introduction This chapter details the PEX 8114 registers, and presents the PEX 8114 user-programmable registers and the order in which they appear in the register map. Register descriptions, when applicable, include details regarding their use and meaning in Forward and Reverse Transparent Bridge modes. For further details regarding register names and descriptions, refer to the following specifications: • PCI r2.3 • PCI r3.0 • PCI-to-PCI Bridge r1.1 • PCI Power Mgmt. r1.2 • PCI Express Base 1.0a • PCI Express-to-PCI/PCI-X Bridge r1.0 • PCI-X r1.0b • PCI-X r2.0a ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 209 Registers 14.2 PLX Technology, Inc. Type 1 Register Map Table 14-1. Type 1 Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h … Type 1 Configuration Space Header Registers New Capability Pointer (40h) 34h … 3Ch Next Capability Pointer (48h) Capability ID (01h) Power Management Capability Registers Next Capability Pointer (58h if PCI-X; 68h if PCI Express) 40h 44h Capability ID (05h) 48h … Message Signaled Interrupt Capability Registers 54h Next Capability Pointer (68h) Capability ID (07h) 58h … PCI-X Capability Registers 64h Next Capability Pointer (00h) Capability ID (10h) 68h … PCI Express Capability Registers 80h 84h – Reserved F4h F8h Device-Specific Indirect Configuration Mechanism Registers FCh Next Capability Offset (FB4h) 1h Extended Capability ID (0003h) 100h 104h Device Serial Number Extended Capability Registers 108h 10Ch – Reserved Next Capability Offset (148h) 1h Extended Capability ID (0004h) 134h 138h … Power Budget Extended Capability Registers 144h Next Capability Offset (000h) 1h Extended Capability ID (0002h) 148h … Virtual Channel Extended Capability Registers 1C4h 1C8h Device-Specific Registers … F7Ch 210 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Register Map Table 14-1. Type 1 Register Map (Cont.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F80h PCI-X Device-Specific Registers … F88h F8Ch Root Port Registers … F9Ch FA0h PCI-X-Specific Registers FA4h FA8h PCI Arbiter Registers … FB0h Next Capability Offset (138h) 1h PCI Express Extended Capability ID (0001h) FB4h … Advanced Error Reporting Extended Capability Registers FFCh ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 211 Registers 14.3 PLX Technology, Inc. Register Descriptions The remainder of this chapter details the PEX 8114 registers, including: • Bit/field names • Register function in Forward and Reverse Transparent Bridge modes • Type • Whether the power-on/reset value can be modified by way of the PEX 8114 serial EEPROM Initialization feature • Initial power-on/reset (default) value The register types are grouped by user accessibility. Table 14-2 defines the types used in the PEX 8114, and their descriptions. Table 14-2. Type HwInit Description Hardware Initialized Register or Register Bit The register bits are initialized by the PEX 8114 Hardware-Initialization mechanism or PEX 8114 serial EEPROM register Initialization feature. The register bits are Read-Only after initialization and can only be reset with “Power Good Reset” (PEX_PERST# assertion). RC Read-Clear – Reading Register Clears Register Value The register bits generally indicate the tally of event occurrences. These registers are used for performance monitoring and, when read, are cleared to 0. RO Read-Only Register or Register Bit The register bits are Read-Only and cannot be altered by software. The register bits can be initialized by the PEX 8114 Hardware-Initialization mechanism or PEX 8114 serial EEPROM register Initialization feature. ROS Read-Only, Sticky Same as RO, except that bits are not initialized nor modified by a Hot Reset. RW Read-Write Register or Register Bit The register bits are Read-Write and can be set or cleared by software to the needed state. RWC Read-Only Status – Write 1 to Clear Status Register or Register Bit The register bits indicate status when read. A status bit set by the system to 1 to indicate status can be cleared by writing 1 to that bit. RWCS Read-Only Status – Write 1 to clear Status register or Register Bit, Sticky The register bits indicate status when read. A status bit set by the system to 1 to indicate status can be cleared by writing 1 to that bit. Writing 0 has no effect. Bits are not initialized or modified by reset. Devices that consume AUX power preserve register values when AUX power consumption is enabled (by way of AUX power or PME Enable). RWS 212 Register Types Read-Write Register or Bit, Sticky The register bits are Read-Write and can be set or cleared by software to the needed state. Bits are not initialized or modified by reset. Devices that consume AUX power preserve register values when AUX power consumption is enabled (by way of AUX power or PME Enable). ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.4 Type 1 Configuration Space Header Registers Type 1 Configuration Space Header Registers Table 14-3. Type 1 Configuration Space Header Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Device ID Vendor ID 00h PCI Status PCI Command 04h Class Code Header Type and Multi-Function BIST (Not Supported) Secondary Latency Timer Primary Latency Timer Revision ID 08h Cache Line Size 0Ch Base Address 0 10h Base Address 1 14h Subordinate Bus Number Secondary Status Secondary Bus Number Primary Bus Number 18h I/O Limit I/O Base 1Ch Memory Limit Memory Base 20h Prefetchable Memory Limit Prefetchable Memory Base 24h Prefetchable Memory Base Upper 32 Bits 28h Prefetchable Memory Limit Upper 32 Bits 2Ch I/O Limit Upper 16 Bits I/O Base Upper 16 Bits 30h New Capability Pointer (48h if PCI-X; 40h if PCI Express) Reserved Expansion ROM Base Address (Not Supported) Bridge Control 34h 38h Interrupt Pin Interrupt Line 3Ch Register 14-1. 00h Product Identification Bit(s) Description Type Serial EEPROM Default 15:0 Vendor ID Identifies the device manufacturer. Defaults to the PCI-SIG-issued Vendor ID of PLX (10B5h) if not overwritten by serial EEPROM. HwInit Yes 10B5h 31:16 Device ID Identifies the particular device. Defaults to the PLX part number for the PEX 8114 (8114h) if not overwritten by serial EEPROM. HwInit Yes 8114h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 213 Registers PLX Technology, Inc. Register 14-2. 04h PCI Command/Status Bit(s) Description Type Serial EEPROM Default PCI Command 0 I/O Access Enable 0 = PEX 8114 ignores I/O Space accesses on the primary interface 1 = PEX 8114 responds to I/O Space accesses on the primary interface RW Yes 0 1 Memory Access Enable 0 = PEX 8114 ignores Memory Space accesses on the primary interface 1 = PEX 8114 responds to Memory Space accesses on the primary interface RW Yes 0 2 Bus Master Enable Controls the PEX 8114 Memory and I/O request forwarding in the upstream direction. Does not affect forwarding of Completions in the upstream nor downstream direction, nor forwarding of messages (including INTA# Interrupt messages). Forward Transparent Bridge mode: 0 = PEX 8114 does not respond to Memory nor I/O requests targeting the bridge on the secondary interface 1 = PEX 8114 forwards Memory and I/O requests Reverse Transparent Bridge mode: 0 = PEX 8114 handles Memory and I/O requests received on the secondary interface as Unsupported Requests (UR); for Non-Posted requests, the PEX 8114 returns a Completion with UR Completion status 1 = PEX 8114 forwards Memory and I/O requests in the upstream direction RW Yes 0 3 Special Cycle Enable Not supported Cleared to 0, as required by the PCI Express Base 1.0a. RO No 0 4 Memory Write and Invalidate Used when the PCI-X interface is in PCI mode. Controls the PEX 8114’s ability to convert PCI Express Memory Write requests into Memory Write and Invalidate requests on the PCI Bus. RW Yes 0 RW Yes 0 RW Yes 0 RO No 0 VGA Palette Snoop Valid in Reverse Transparent Bridge mode. PCI Express-to-PCI bridges do not support VGA Palette snooping. 5 0 = PEX 8114 treats VGA Palette Write accesses as other accesses 1 = VGA Palette snooping is enabled (that is, the PEX 8114 does not respond to VGA Palette register Writes and snoops the data) Refer to Section 5.2.1.4, “VGA Mode,” for further details. Parity Error Response Enable Controls the PEX 8114’s response to Data Parity errors forwarded from its primary interface (such as a Poisoned TLP or PCI Bus Parity errors). 6 7 214 0 = PEX 8114 must ignore Data Parity errors that it detects and continue standard operation (however, records status, such as setting bit 31 (Detected Parity Error) 1 = PEX 8114 must set the proper error bits and report the error when a Data Parity error is detected IDSEL Stepping/Wait Cycle Control Not supported Cleared to 0, as required by the PCI Express Base 1.0a. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-2. 04h PCI Command/Status (Cont.) Type Serial EEPROM Default 8 SERR# Enable Controls bit 30 (Signaled System Error). Forward Transparent Bridge mode: 1 = Enables reporting of Fatal and Non-Fatal errors detected by the device to the Root Complex Reverse Transparent Bridge mode: 1 = Enables reporting of errors detected by the device by asserting PCI_SERR# on the PCI-X Bus RW Yes 0 9 Fast Back-to-Back Transactions Enabled Not supported Cleared to 0, as required by the PCI Express Base 1.0a. RO No 0 10 Interrupt Disable Forward Transparent Bridge mode: 0 = PEX 8114 is enabled to generate INTA# Interrupt messages 1 = PEX 8114 is prevented from generating INTA# Interrupt messages Reverse Transparent Bridge mode: 0 = PEX 8114 is enabled to generate INTA# interrupts 1 = PEX 8114 is prevented from generating INTA# interrupts RW Yes 0 Bit(s) Description 15:11 Reserved 18:16 Reserved 00h PCI Status 19 Interrupt Status Indicates that an INTx# Interrupt message is pending on behalf of sources internal to the PEX 8114. This bit does not reflect the PCI_INTx# input status associated with the secondary interface. 000b RO No 0 RO Yes 1 RO/Fwd RO/Rev No 0 1 0 = No INTA# Interrupt message is pending 1 = INTA# Interrupt message is pending internally 20 Capabilities List Required by the PCI Express Base 1.0a to be 1 at all times. 21 66 MHz Capable Forward Transparent Bridge mode: Cleared to 0, as required by the PCI Express Base 1.0a. Reverse Transparent Bridge mode: PCI-X interface is capable of 66-MHz operation; therefore, this bit is set to 1. 22 Reserved 23 Fast Back-to-Back Transactions Capable Forward Transparent Bridge mode: Cleared to 0, as required by the PCI Express Base 1.0a. Reverse Transparent Bridge mode: Set to 1, indicating Fast Back-to-Back Transaction capability. 0 RO/Fwd RO/Rev ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved No 0 1 215 Registers PLX Technology, Inc. Register 14-2. 04h PCI Command/Status (Cont.) Bit(s) Description Type Serial EEPROM Default RWC Yes 0 RO/Fwd RO/Rev No No 00b 10b RWC Yes 0 Master Data Parity Error Reports Data Parity error detection by the PEX 8114 on the primary interface. Set to 1 if bit 6 (Parity Error Response Enable) is set, and one of the following conditions occur. Forward Transparent Bridge mode: • PEX 8114 receives a Completion marked poisoned on the primary interface, or • PEX 8114 poisons a Write request on the primary interface 24 Reverse Transparent Bridge mode: • PEX 8114, as a bus Master on the primary interface, asserts PCI_PERR# on a Read transaction or detects PCI_PERR# asserted on a Write transaction, or • PEX 8114 receives a Completion or Split Completion with a Parity error on the secondary interface, or • PEX 8114 receives a Split Completion message for a Non-Posted Write on the primary interface, indicating an Uncorrectable (Split) Write Data error 26:25 27 216 DEVSEL Timing Forward Transparent Bridge mode: Cleared to 00b, as required by the PCI Express Base 1.0a. Reverse Transparent Bridge mode: Pertain to PCI and PCI-X modes. Encode PCI_DEVSEL# timing. For the PEX 8114, the field is set to 10b, indicating slow speed. Signaled Target Abort Forward Transparent Bridge mode: When a Memory-Mapped access payload length is greater than 1 DWord, the PEX 8114 sets this bit to 1. Also set to 1 when the PEX 8114 completes a request as a Transaction Target on its primary interface, using Completer Abort Completion status. Reverse Transparent Bridge mode: When the PCI-X interface signals Target Abort, the PEX 8114 sets this bit to 1. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-2. 04h PCI Command/Status (Cont.) Type Serial EEPROM Default 28 Received Target Abort Forward Transparent Bridge mode: Set to 1 when the PEX 8114 receives a Completion with Completer Abort Completion status. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 is the transaction Master, terminated with a Target Abort or PCI-X Split Completion message, indicating that a Target Abort was received. RWC Yes 0 29 Received Master Abort Forward Transparent Bridge mode: Set to 1 when the PEX 8114 receives a Completion with Unsupported Request Completion status. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 is the transaction Master, terminated by the bridge with Master Abort status. RWC Yes 0 30 Signaled System Error Forward Transparent Bridge mode: Set to 1 when the PEX 8114 transmits an ERR_FATAL or ERR_NONFATAL message to the Root Complex. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 asserts PCI_SERR# on the PCI-X Bus. RWC Yes 0 RWC Yes 0 Bit(s) 31 Description Detected Parity Error Forward Transparent Bridge mode: Set to 1 by the PEX 8114 when it receives a Poisoned TLP, or TLP with bad ECRC (Read Completion or Write Request) on the primary interface, regardless of the bit 6 (Parity Error Response Enable) state. Reverse Transparent Bridge mode: Reports detection of an Address or Data Parity error by the PEX 8114 on its primary interface. Must be set to 1, regardless of the bit 6 (Parity Error Response Enable) state, when the PEX 8114 detects any of the following conditions: • Address or Attribute Parity error as a potential Target • Data Parity error when the Target of a Write transaction or PCI-X Split Completion • Data Parity error when the Master of a Read transaction (Immediate Read data or PCI-X Split Response) ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 217 Registers PLX Technology, Inc. Register 14-3. 08h Class Code and PCI Revision ID Bit(s) Description Type Serial EEPROM Default 7:0 Revision ID Unless overwritten by the serial EEPROM, returns the Silicon Revision (BCh or BDh), the PLX-assigned Revision ID for this version of the PEX 8114. The PEX 8114 Serial EEPROM register Initialization capability is used to replace the PLX Revision ID with another Revision ID. RO Yes BCh or BDh Class Code 060400h 15:8 Programming Interface The PEX 8114 supports the PCI-to-PCI Bridge r1.1 requirements, but not subtractive decoding, on its upstream interface. RO Yes 00h 23:16 Sub-Class Code PCI-to-PCI bridge. RO Yes 04h 31:24 Base Class Code Bridge device. RO Yes 06h Type Serial EEPROM Default RW Yes 00h RO/Fwd RW/Rev RW/Rev No Yes Yes 00h 00h (PCI) 40h (PCI-X) Register 14-4. 0Ch Miscellaneous Control Bit(s) Description Cache Line Size Specifies the system Cache Line Size (in units of DWords). 7:0 00h = 1 DWord (32-bit bus); 2 DWords (64-bit bus) 01h = 1 DWord 02h = 2 DWords 04h = 4 DWords 08h = 8 DWords 10h = 16 DWords 20h = 32 DWords All other encodings are reserved. 15:8 Primary Latency Timer Forward Transparent Bridge mode: Cleared to 00h, as required by the PCI Express Base 1.0a. Reverse Transparent Bridge mode: Specifies the Master Latency Timer (in units of PCI Bus clocks) when the primary interface is a Bus Master. 22:16 Header Type The PEX 8114 Configuration Space Header adheres to the Type 1 PCI-to-PCI Bridge Configuration Space layout defined by the PCI-to-PCI Bridge r1.1. RO No 01h Multi-Function Always 0, because the PEX 8114 is a single-function device. RO No 0 BIST Not supported Cleared to 00h. RO No 00h 23 31:24 218 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-5. 10h Base Address 0 Bit(s) 0 2:1 Description Type Serial EEPROM Default RO No 0 RO Yes 00b RO No 0 Memory Space Indicator When enabled, the Base Address register maps the PEX 8114 Configuration registers into Memory space. Memory Map Type 00b = Base Address register is 32 bits wide and can be mapped anywhere in the 32-bit Memory space 10b = Base Address register is 64 bits wide and can be mapped anywhere in the 64-bit Address space All other encodings are reserved. 3 Prefetchable Base Address register maps the PEX 8114 Configuration registers into Non-Prefetchable Memory space, by default. 12:4 Reserved 000h 31:13 Base Address Base Address for Device-Specific Memory-Mapped Configuration mechanism. RW Yes 0000_0h Register 14-6. 14h Base Address 1 Bit(s) 31:0 Type Serial EEPROM Default Base Address 1 For 64-bit addressing, Base Address 1 extends Base Address 0, to provide the upper 32 Address bits when the Base Address 0 register Memory Map Type field (offset 10h[2:1]) is set to 10b. RW Yes 0000_0000h Read-Only when the Base Address 0 register is not enabled as a 64-bit BAR [Memory Map Type field (offset 10h[2:1]) is not equal to 10b]. RO No 0000_0000h Description ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 219 Registers PLX Technology, Inc. Register 14-7. 18h Bus Number Bit(s) Description Type Serial EEPROM Default 7:0 Primary Bus Number Records the Bus Number of the PCI Bus segment to which the primary interface of the PEX 8114 is connected. Set by Configuration software. RW Yes 00h 15:8 Secondary Bus Number Records the Bus Number of the PCI Bus segment that is the secondary interface of the PEX 8114. Set by Configuration software. RW Yes 00h 23:16 Subordinate Bus Number Records the Bus Number of the highest numbered PCI Bus segment subordinate to the PEX 8114. Set by Configuration software. RW Yes 00h 31:24 Secondary Latency Timer Forward Transparent Bridge mode: Specifies the Master Latency Timer (in units of PCI Bus clocks) when the secondary interface is a Bus Master. Reverse Transparent Bridge mode: Cleared to 00h, as required by the PCI Express Base 1.0a. RW/Fwd RW/Fwd RO/Rev Yes Yes No 00h (PCI) 40h (PCI-X) 00h 220 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-8. 1Ch Secondary Status, I/O Limit, and I/O Base Bit(s) Description Type Serial EEPROM Default Note: The PEX 8114 uses the Memory Base and Limit registers (offset 20h) to determine the Address range of Non-Prefetchable Memory transactions to forward from one of its interfaces to the other. I/O Base 3:0 I/O Base Addressing Capability 1h = 32-bit Address decoding is supported RO No 1h RW Yes 0h RO No 1h RW Yes 0h All other encodings are reserved. 7:4 I/O Base Address[15:12] The PEX 8114 uses the I/O Base and I/O Limit registers to determine the Address range of I/O transactions to forward from one interface to the other. These bits specify the corresponding PEX 8114 I/O Base Address[15:12]. The PEX 8114 assumes I/O Base Address[11:0]=000h. The PEX 8114 decodes Address bits [31:0], and uses the I/O Base and Limit Upper 16 Bits register I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits fields (offset 30h[15:0 and 31:16], respectively). I/O Limit 11:8 I/O Limit Addressing Capability 1h = 32-bit Address decoding is supported All other encodings are reserved. 15:12 I/O Limit Address[15:12] The PEX 8114 uses the I/O Base and I/O Limit registers to determine the Address range of I/O transactions to forward from one interface to the other. These bits specify the corresponding PEX 8114 I/O Limit Address[15:12]. The PEX 8114 assumes Address bits [11:0] of the I/O Limit Address are FFFh. The PEX 8114 decodes Address bits [31:0], and uses the I/O Base and Limit Upper 16 Bits register I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits fields (offset 30h[15:0 and 31:16], respectively). When the I/O Limit Address is less than the I/O Base Address, the PEX 8114 does not forward I/O transactions from the primary/upstream bus to its secondary/downstream bus. However, the PEX 8114 forwards all I/O transactions from the secondary bus to its primary bus. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 221 Registers PLX Technology, Inc. Register 14-8. 1Ch Secondary Status, I/O Limit, and I/O Base (Cont.) Bit(s) Description Type Serial EEPROM Default Secondary Status 20:16 Reserved 0-0h 21 66 MHz Capable Forward Transparent Bridge mode: PCI-X interface is capable of 66-MHz operation; therefore, this bit is set to 1. Reverse Transparent Bridge mode: Not supported 0 = Not enabled, because PCI Express does not support 66 MHz 22 Reserved 23 Fast Back-to-Back Transactions Capable Forward Transparent Bridge mode: Set to 1, indicating Fast Back-to-Back Transactions capable. Reverse Transparent Bridge mode: Reserved 0 = Not enabled, because PCI Express does not support this function RO/Fwd RO/Rev No No 1 0 0 RO/Fwd RO/Rev No No 1 0 RWC Yes 0 RO/Fwd RO/Rev No No 10b 00b RWC Yes 0 Master Data Parity Error Reports Data Parity error detection by the PEX 8114 on the secondary interface. Set to 1 if the Bridge Control register Parity Error Response Enable bit is set (offset 3Ch[16]=1), and one of the following conditions occur. Forward Transparent Bridge mode: • PEX 8114, as a bus Master on the secondary interface, asserts PCI_PERR# on a Read transaction or detects PCI_PERR# asserted on a Write transaction 24 • PEX 8114 receives a Completion or Split Completion with a Parity error on the secondary interface • PEX 8114 receives a Split Completion message for a Non-Posted Write, indicating an Uncorrectable (Split) Write Data error Reverse Transparent Bridge mode: • PEX 8114 receives a Completion marked poisoned on the secondary interface • PEX 8114 poisons a Write Request on the secondary interface 26:25 27 222 DEVSEL Timing Forward Transparent Bridge mode: Pertains to PCI and PCI-X modes. Encodes PCI_DEVSEL# timing. For the PEX 8114, the field is set to 10b, indicating slow speed. Reverse Transparent Bridge mode: Cleared to 00b, as required by the PCI Express Base 1.0a. Signaled Target Abort Forward Transparent Bridge mode: When the PCI-X interface signals Target Abort, the PEX 8114 sets this bit to 1. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 completes a request as a Transaction Target on its secondary interface, using Completer Abort Completion status. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-8. 1Ch Secondary Status, I/O Limit, and I/O Base (Cont.) Type Serial EEPROM Default 28 Received Target Abort Forward Transparent Bridge mode: Set to 1 when the PEX 8114 is the transaction Master terminated with a Target Abort or PCI-X Split Completion message indicating that a Target Abort was received. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 receives a Completion with Completer Abort Completion status. RWC Yes 0 29 Received Master Abort Forward Transparent Bridge mode: Set to 1 when the PEX 8114 is the transaction Master terminated by the bridge with Master Abort status. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 receives a Completion with Unsupported Request (UR) Completion status. RWC Yes 0 30 Received System Error Forward Transparent Bridge mode: Set to 1 when the PEX 8114 asserts PCI_SERR# on its secondary interface. Reverse Transparent Bridge mode: Set to 1 when an ERR_FATAL or ERR_NONFATAL message is received on the PEX 8114’s secondary interface. RWC Yes 0 RWC Yes 0 Bit(s) Description Detected Parity Error Forward Transparent Bridge mode: Reports an Address or Data Parity error when detected by the PEX 8114 on its secondary interface. Must be set to 1, regardless of the Bridge Control register Parity Error Response Enable bit (offset 3Ch[16]) state, when any of the following three conditions is true: • Detects an Address or Attribute Parity error as a potential Target 31 • Detects a Data Parity error when the Target of a Write transaction or PCI-X Split Completion • Detects a Data Parity error when the Master of a Read transaction (Immediate Read data or PCI-X Split Response) Reverse Transparent Bridge mode: Set to 1 by the PEX 8114 when it receives a Poisoned TLP or a TLP with bad ECRC (Read Completion or Write Request) on the secondary interface, regardless of the Bridge Control register Parity Error Response Enable bit (offset 3Ch[16]) state. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 223 Registers PLX Technology, Inc. Register 14-9. 20h Memory Base and Limit Bit(s) Description Type Serial EEPROM Default Note: The PEX 8114 uses the Prefetchable Memory Base and Limit register (offset 24h) to determine the Address range of Prefetchable Memory transactions to forward from one of its interfaces to the other. Memory Base 3:0 Reserved 0h 15:4 Memory Base Address[31:20] Specifies the PEX 8114 non-prefetchable Memory Base Address[31:20]. The PEX 8114 assumes Memory Base Address[19:0]=00000h. RW Yes 000h Memory Limit 19:16 Reserved 0h 31:20 Memory Limit Address[31:20] Specifies the PEX 8114 non-prefetchable Memory Limit Address[31:20]. The PEX 8114 assumes Memory Limit Address[19:0]=FFFFFh. RW Yes 000h Register 14-10. 24h Prefetchable Memory Base and Limit Type Serial EEPROM Default RO Yes 1h RW Yes 000h 19:16 Prefetchable Memory Limit Capability 0h = PEX 8114 supports 32-bit Prefetchable Memory Addressing 1h = PEX 8114 defaults to 64-bit Prefetchable Memory Addressing support, as required by the PCI Express Base 1.0a RO Yes 1h 31:20 Prefetchable Memory Limit Address[31:20] Specifies the PEX 8114 Prefetchable Memory Limit Address[31:20]. The PEX 8114 assumes Prefetchable Memory Limit Address[19:0]=FFFFFh. RW Yes 000h Bit(s) Description Prefetchable Memory Base 3:0 Prefetchable Memory Base Capability 0h = PEX 8114 supports 32-bit Prefetchable Memory Addressing 1h = PEX 8114 defaults to 64-bit Prefetchable Memory Addressing support, as required by the PCI Express Base 1.0a Note: If the application needs 32-bit only Prefetchable space, the serial EEPROM must clear both this field and field [19:16] (Prefetchable Memory Limit Capability). Prefetchable Memory Base Address[31:20] Specifies the PEX 8114 Prefetchable Memory Base Address[31:20]. The PEX 8114 assumes Prefetchable Memory Base Address[19:0]=00000h. 15:4 Note: When the Prefetchable Memory Limit Address is less than the Prefetchable Memory Base Address, the PEX 8114 does not forward Prefetchable Memory transactions from the upstream bus to its downstream bus. However, the PEX 8114 forwards all Memory transactions from the downstream bus to its upstream bus. Prefetchable Memory Limit 224 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-11. 28h Prefetchable Memory Base Upper 32 Bits Bit(s) 31:0 Type Serial EEPROM Default When offset 24h[3:0]=1h RW Yes 0000_0000h When offset 24h[3:0]=0h RO No 0000_0000h Type Serial EEPROM Default When offset 24h[19:16]=1h RW Yes 0000_0000h When offset 24h[19:16]=0h RO No 0000_0000h Description Prefetchable Memory Base Address[63:32] The PEX 8114 uses this register for Prefetchable Memory Upper Base Address[63:32]. When the Prefetchable Memory Base register Prefetchable Memory Base Capability field indicates 32-bit addressing, this register is Read-Only and returns 0000_0000h. Register 14-12. 2Ch Prefetchable Memory Limit Upper 32 Bits Bit(s) 31:0 Description Prefetchable Memory Limit Address[63:32] The PEX 8114 uses this register for Prefetchable Memory Upper Limit Address[63:32]. When the Prefetchable Memory Limit register Prefetchable Memory Limit Capability field indicates 32-bit addressing, this register is Read-Only and returns 0000_0000h. Register 14-13. 30h I/O Base and Limit Upper 16 Bits Bit(s) Description Type Serial EEPROM Default 15:0 I/O Base Upper 16 Bits The PEX 8114 uses this register for I/O Base Address[31:16]. RW Yes 0000h 31:16 I/O Limit Upper 16 Bits The PEX 8114 uses this register for I/O Limit Address[31:16]. RW Yes 0000h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 225 Registers PLX Technology, Inc. Register 14-14. 34h New Capability Pointer Bit(s) Description 7:0 New Capability Pointer PCI-X interface: Default 48h points to the Message Signaled Interrupt Capability structure. PCI Express interface: Default 40h points to the Power Management Capability structure. 31:8 Reserved Type Serial EEPROM Default RO No 48h (PCI-X) 40h (PCI Express) 0000_00h Register 14-15. 38h Expansion ROM Base Address Bit(s) 31:0 Description Expansion ROM Base Address Not supported Cleared to 0000_0000h. Type Serial EEPROM Default RO No 0000_0000h Register 14-16. 3Ch Bridge Control and Interrupt Signal Bit(s) Description Type Serial EEPROM Default RW Yes 00h RO No 01h Interrupt Signal 7:0 15:8 Interrupt Line The PEX 8114 does not use this register, but provides it for operating system and device driver use. Interrupt Pin Identifies the Conventional PCI Interrupt message that the device (or device function) uses. Only value 00h or 01h is allowed in the PEX 8114. 00h = Indicates that the device does not use Conventional PCI Interrupt message(s) 01h = Maps to Conventional PCI Interrupt messages for INTA# 226 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-16. 3Ch Bridge Control and Interrupt Signal (Cont.) Bit(s) Description Type Serial EEPROM Default RW Yes 0 RW Yes 0 Bridge Control Parity Error Response Enable Controls the PEX 8114’s response to Address and Data Parity errors on the secondary interface. 16 0 = PEX 8114 must ignore Parity errors that it detects on the secondary interface and continue standard operation. The PEX 8114 must generate parity, although Parity Error reporting is disabled. 1 = PEX 8114 must detect and report Parity errors on the secondary interface [enables the Secondary Status register Master Data Parity Error bit (offset 1Ch[24]=1)]. SERR# Enable Forward Transparent Bridge mode: Controls forwarding of secondary interface PCI_SERR# assertions to the primary interface. The PEX 8114 transmits an ERR_FATAL or ERR_NONFATAL cycle on the primary interface when all the following conditions are true: • PCI_SERR# is asserted on the secondary interface • This bit is set • PCI Command register SERR# Enable bit is set (offset 04h[8]=1) 17 Reverse Transparent Bridge mode: Controls forwarding of ERR_FATAL and ERR_NONFATAL from the secondary interface to the primary interface, by asserting PCI_SERR# when all the following conditions are true: • ERR_FATAL or ERR_NONFATAL is received on the secondary interface • This bit is set • PCI Command register SERR# Enable bit is set (offset 04h[8]=1) When set to 1, and the PCI Command register SERR# Enable bit is set, enables the PCI Status register Signaled System Error bit (offset 04h[30]=1). 18 ISA Enable Refer to Section 5.2.1.3, “ISA Mode,” for details. RW Yes 0 19 VGA Enable Refer to Section 5.2.1.4, “VGA Mode,” and the PCI r3.0, for details. RW Yes 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 227 Registers PLX Technology, Inc. Register 14-16. 3Ch Bridge Control and Interrupt Signal (Cont.) Type Serial EEPROM Default RW Yes 0 RW Yes 0 22 Secondary Bus Reset Forward Transparent Bridge mode: 1 = Causes PCI_RST# to assert on the secondary interface Reverse Transparent Bridge mode: 1 = Causes a Hot Reset on the PEX 8114 secondary interface RW Yes 0 23 Fast Back-to-Back Transaction Enable Not supported Cleared to 0, as required by the PCI Express Base 1.0a. RO No 0 Bit(s) 20 Description VGA 16-Bit Decode Refer to Section 5.2.1.4, “VGA Mode,” and the PCI r3.0, for details. Master Abort Mode Controls bridge behavior after it receives a Master Abort termination (such as, an Unsupported Request on PCI Express) on either interface. This bit does not affect the behavior of the bridge when forwarding a UR Completion from PCI Express to the PCI-X interface, if the PCI-X interface is operating in PCI-X mode. 21 228 0 = Do not report Master Aborts. Return FFFF_FFFFh on Reads and discard data on Writes initiated from the PCI-X interface (PCI-to-PCI Express). For Posted transactions initiated from the PCI Express interface (PCI Express-to-PCI), no action is taken (that is, all data is discarded). 1 = Report UR Completions from PCI Express by signaling Target Abort on the PCI-X interface operating in Conventional PCI mode (PCI-to-PCI Express). For Posted transactions initiated from the PCI Express interface (PCI Express-to-PCI) that experience a Master Abort on the PCI-X interface, the bridge must return ERR_FATAL or ERR_NONFATAL on the primary interface (provided the PCI Command register SERR# Enable bit is set (offset 04h[8]=1). ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Type 1 Configuration Space Header Registers Register 14-16. 3Ch Bridge Control and Interrupt Signal (Cont.) Bit(s) 24 Description Primary Discard Timer Pertains to the PCI Bus in Conventional PCI mode and Reverse Transparent Bridge mode. Selects the number of PCI clocks that the bridge waits for a Master on the primary interface to repeat a Delayed Transaction request. The Counter starts after the Delayed Completion (the Delayed Transaction Completion on the secondary interface) reaches the head of the bridge’s upstream queue (that is, all Ordering requirements are satisfied and the bridge is ready to complete the Delayed Transaction with the originating Master on the primary bus). If the originating Master does not repeat the transaction before the Counter expires, the bridge deletes the Delayed Transaction from its queue and sets bit 26 (Discard Timer Status). Type Serial EEPROM Default RO/Fwd RW/Rev No Yes 0 0 RW/Fwd RO/Rev Yes No 0 0 RWC Yes 0 RW Yes 0 0 = Primary Discard Timer counts 215 PCI Clock cycles 1 = Primary Discard Timer counts 210 PCI Clock cycles 25 Secondary Discard Timer Pertains to the PCI Bus in Conventional PCI mode and Forward Transparent Bridge mode. Selects the number of PCI clocks the bridge waits for a Master on the secondary interface to repeat a Delayed Transaction request. The Counter starts after the Completion (PCI Express Completion associated with the Delayed Transaction request) reaches the head of the bridge’s downstream queue (that is, all Ordering requirements are satisfied and the bridge is ready to complete the Delayed Transaction with the originating Master on the secondary bus). If the originating Master does not repeat the transaction before the Counter expires, the bridge deletes the Delayed Transaction from its queue and sets bit 26 (Discard Timer Status). 0 = Secondary Discard Timer counts 215 PCI Clock cycles 1 = Secondary Discard Timer counts 210 PCI Clock cycles 26 Discard Timer Status Pertains to the PCI Bus in Conventional PCI mode. Set to 1 when bit 24 or 25 (Primary Discard Timer or Secondary Discard Timer, respectively) expires and a Delayed Completion is discarded from a queue in the PEX 8114. The default state of this bit after reset must be 0. Once set, remains set until it is reset by writing 1 to this bit location. 27 Discard Timer SERR# Enable Pertains to the PCI Bus in Conventional PCI mode. When set to 1, enables the bridge to generate an ERR_FATAL or ERR_NONFATAL transaction when bit 25 (Secondary Discard Timer) expires and a Delayed Transaction is discarded from a queue in the PEX 8114. 31:28 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0h 229 Registers PLX Technology, Inc. 14.5 Power Management Capability Registers This section details the PEX 8114 Power Management Capability registers. Table 14-4 defines the register map. Table 14-4. Power Management Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Power Management Capability Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Capability Pointer (48h) Power Management Control/ Status Bridge Extensions Capability ID (01h) 40h Power Management Status and Control 44h Register 14-17. 40h Power Management Capability Bit(s) Description Type Serial EEPROM Default 7:0 Capability ID Set to 01h, indicating that the data structure currently being pointed to is the PCI Power Management data structure. RO Yes 01h 15:8 Next Capability Pointer Default 48h points to the Message Signaled Interrupt Capability structure. RO Yes 48h 18:16 Version Default 011b indicates compliance with the PCI Power Mgmt. r1.2. RO Yes 011b 19 PME Clock Set to 1, as required by the PCI Express Base 1.0a. RO No 1 20 Reserved 21 Device-Specific Initialization Default 0 indicates that Device-Specific Initialization is not required. RO Yes 0 24:22 AUX Current Not supported Default 000b indicates that the PEX 8114 does not support Auxiliary Current requirements. RO Yes 000b 25 D1 Support Not supported Default 0 indicates that the PEX 8114 does not support the D1 Device PM state. RO No 0 26 D2 Support Not supported Default 0 indicates that the PEX 8114 does not support the D2 Device PM state. RO No 0 PME Support Default 1100_1b indicates that the PEX 8114 forwards PME messages in the D0, D3hot, and D3cold Device PM states. RO Yes 1100_1b 31:27 230 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Power Management Capability Registers Register 14-18. 44h Power Management Status and Control Bit(s) Description Type Serial EEPROM Default RW Yes 00b Power Management Status and Control Power State Used to determine the current Device PM state, and to set the PEX 8114 into a new Device PM state. 1:0 00b = D0 01b = D1 – Not supported 10b = D2 – Not supported 11b = D3hot If software attempts to write an unsupported state to this field, the Write operation completes normally; however, the data is discarded and no state change occurs. 2 Reserved 3 No Soft Reset When set to 1, indicates that devices transitioning from the D3hot to D0 Device PM state, because of Power State commands, do not perform an internal reset. 7:4 0 RO Yes Reserved 1 0h PME Enable 8 0 = Disables PME generation by the PEX 8114a 1 = Enables PME generation by the PEX 8114 RWS No 0 RO Yes 0h RO No 0h RO Yes 00b RWC No 0 Data Select Initially writable by serial EEPROM only. After a Serial EEPROM Write occurs to this register, RW for all CSR accesses.b Bits [12:9] select the Data and Data Scale registers. 12:9 0h = D0 Device PM state power consumed 3h = D3hot Device PM state power consumed 4h = D0 Device PM state power dissipated 7h = D3hot Device PM state power dissipated Not supported RO for hardware auto-configuration. Data Scale 14:13 Writable by serial EEPROMb. Indicates the scaling factor to be used when interpreting the value of the Data register. The value and meaning of this field varies, depending upon which data value is selected by bits [12:9] (Data Select). There are four internal Data Scale registers (one each per Data register – 0, 3, 4 and 7). Bits [12:9], Data Select, select the Data Scale register. PME Status 15 0 = PME is not generated by the PEX 8114a 1 = PME is being generated by the PEX 8114 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 231 Registers PLX Technology, Inc. Register 14-18. 44h Power Management Status and Control (Cont.) Bit(s) Description Type Serial EEPROM Default Power Management Control/Status Bridge Extensions 21:16 Reserved 0-0h 22 B2/B3 Support Not supported Cleared to 0, as required by the PCI Power Mgmt. r1.2. RO No 0 23 Bus Power/Clock Control Enable Not supported Cleared to 0, as required by the PCI Power Mgmt. r1.2. RO No 0 RO Yes 00h Power Management Data Data 31:24 Writable by serial EEPROM onlyb. There are four internal Data registers. Bits [12:9], Data Select, select the Data register. a. Because the PEX 8114 does not consume auxiliary power, this bit is not sticky, and is cleared to 0 at power-on reset. b. With no serial EEPROM, reads return 00h for the Data Scale and Data registers (for all Data Selects). 232 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.6 Message Signaled Interrupt Capability Registers Message Signaled Interrupt Capability Registers This section details the PEX 8114 Message Signaled Interrupt (MSI) Capability registers. Table 14-5 defines the register map. Table 14-5. Message Signaled Interrupt Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Capability Pointer (58h if PCI-X; 68h if PCI Express) MSI Control Capability ID (05h) 48h MSI Address 4Ch MSI Upper Address 50h Reserved MSI Data 54h Register 14-19. 48h Message Signaled Interrupt Capability Bit(s) Description Type Serial EEPROM Default MSI Capability Header 7:0 Capability ID Set to 05h, as required by the PCI r3.0. RO Yes 05h 15:8 Next Capability Pointer PCI-X interface: Set to 58h to point to the PCI-X Capability structure. PCI Express interface: Set to 68h to point to the PCI Express Capability structure. RO Yes 58h (PCI-X) 68h (PCI Express) MSI Enable 0 = Message Signaled Interrupts for the PEX 8114 are disabled 1 = Message Signaled Interrupts for the PEX 8114 are enabled RW Yes 0 19:17 Multiple Message Capable 000b = PEX 8114 is requesting one message – the only value supported RO Yes 000b 22:20 Multiple Message Enable 000b = PEX 8114 contains one allocated message – the only value supported RW Yes 000b 23 MSI 64-Bit Address Capable 1 = PEX 8114 is capable of generating 64-bit MSI addresses RO Yes 1 MSI Control 16 31:24 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 00h 233 Registers PLX Technology, Inc. Register 14-20. 4Ch MSI Address Bit(s) 1:0 31:2 Description Type Serial EEPROM Reserved 00b Message Address Note: Default Refer to register offset 50h for MSI Upper Address. RW Yes 0000_0000h Type Serial EEPROM Default RW Yes 0000_0000h Type Serial EEPROM Default RW Yes 0000h Register 14-21. 50h MSI Upper Address Bit(s) 31:0 Description Message Upper Address MSI Write transaction upper address[63:32]. Valid/used only when the MSI Control register MSI 64-Bit Address Capable bit is set (offset 48h[23]=1). Note: Refer to register offset 4Ch for MSI Address. Register 14-22. 54h MSI Data Bit(s) Description 15:0 Message Data MSI Write Transaction TLP Payload. 31:16 Reserved 234 0000h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.7 PCI-X Capability Registers PCI-X Capability Registers This section details the PEX 8114 PCI-X Capability registers. Table 14-6 defines the register map. Table 14-6. PCI-X Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCI-X Secondary Status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Capability Pointer (68h) Capability ID (07h) 58h PCI-X Bridge Status 5Ch Upstream Split Transaction Control 60h Downstream Split Transaction Control 64h Register 14-23. 58h PCI-X Capability, Secondary Status Bit(s) Description Type Serial EEPROM Default PCI-X Capability Header 7:0 Capability ID Set to 07h. RO No 07h 15:8 Next Capability Pointer Set to 68h to point to PCI Express Capability structure. RO No 68h RO/Fwd RO/Rev Yes No 1 0 RO/Fwd RO/Rev No No 1 0 RWC/Fwd RO/Rev No No 0 0 RWC No 0 PCI-X Secondary Status 16 64-Bit Device Pertains to the PCI-X interface in Forward Transparent Bridge mode. 1 = Indicates that the PCI-X interface has 64 AD lines 17 133 MHz Capable Pertains to the PCI-X interface in Reverse Transparent Bridge mode and PCI-X mode. When set to 1, indicates that the PCI-X interface is capable of operating with a clock frequency of 133 MHz. 0 = Maximum operating clock frequency is 66 MHz 1 = Maximum operating clock frequency is 133 MHz 18 Split Completion Discarded Pertains to the PCI-X interface in Forward Transparent Bridge mode.This bit is set if the bridge discards a Split Completion propagating downstream toward the secondary bus because the Requester does not accept it. 0 = Split Completion is not discarded 1 = Split Completion is not discarded 19 Unexpected Split Completion Pertains to the PCI-X interface in Forward Transparent Bridge mode and the PCI Express interface in Reverse Transparent Bridge mode. This bit is set if a Split Completion is received on the PCI-X interface and there is no matching request. 0 = Unexpected Split Completion is not received 1 = Unexpected Split Completion is received ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 235 Registers PLX Technology, Inc. Register 14-23. 58h PCI-X Capability, Secondary Status (Cont.) Bit(s) 20 Description Split Completion Overrun Pertains to the PCI-X interface in Forward Transparent Bridge mode. This bit is set if the bridge terminates a Split Completion on the secondary bus with Retry or Disconnect at Next ADB because the bridge buffers are full. Used by algorithms that optimize the Downstream Split Transaction Control register Split Transaction Commitment Limit field (offset 64h[31:16]) setting. (Refer to the PCI-X r2.0a, Appendix D, for further details.) The bridge is also permitted to set this bit in other situations that indicate that the bridge commitment limit is overly high. For example, if the bridge stores Immediate Completion data in the same buffer area as Split Completion data, the Completer executes the transaction as an Immediate transaction, and the bridge disconnects the transaction because the buffers are full. Type Serial EEPROM Default RWC/Fwd RO/Rev No No 0 0 RWC/Fwd RWC/Rev No No 0 0 RO/Fwd RO/Rev No No 0h 0h 0 = Bridge accepted all Split Completions 1 = Bridge terminated a Split Completion with Retry or Disconnect at Next ADB because the bridge buffers are full 21 Split Request Delayed Pertains to the PCI-X interface in Forward Transparent Bridge mode and the PCI Express interface in Reverse Transparent Bridge mode. This bit is set when the PCI-X interface cannot forward a transaction due to a lack of space specified in the Downstream Split Transaction Control register Split Transaction Commitment Limit field (offset 64h[31:16]). (Refer to the PCI-X r2.0a, Appendix D, for further details.) 0 = Bridge does not delay a Split Request 1 = Bridge does delay a Split Request Secondary Clock Bus Mode and Frequency Pertains to the PCI-X interface in Forward Transparent Bridge mode. Provides a code that indicates to software the mode and frequency in which the PCI-X interface is operating. Encodings not listed are reserved. 25:22 27:26 236 Reg Mode 0h 1h 2h 3h Reserved Error Protection Conventional PCI parity PCI-X Mode 1 parity PCI-X Mode 1 parity PCI-X Mode 1 parity Max. Clock Freq. (MHz) N/A 66 100 133 Min. Clock Period (ns) N/A 15 10 7.5 00b ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI-X Capability Registers Register 14-23. 58h PCI-X Capability, Secondary Status (Cont.) Bit(s) Description Type Serial EEPROM Default RO/Fwd RO/Rev No No 00b 00b PCI-X Capabilities List Item Version Pertains to the PCI-X interface in Forward Transparent Bridge mode. Indicates the PCI-X Capabilities List item format, and whether the PEX 8114 supports ECC in Mode 1. 29:28 Value Version 00b 01b 10b 11b 0 1 2 Reserved ECC Support Capabilities None Mode 2, not Mode 1 Mode 1 or Modes 1 and 2 List Item Size 16 bytes 32 bytes 32 bytes 30 PCI-X 266 Capable Not supported Cleared to 0. RO No 0 31 PCI-X 533 Capable Not supported Cleared to 0. RO No 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 237 Registers PLX Technology, Inc. Register 14-24. 5Ch PCI-X Bridge Status Bit(s) Description Type Serial EEPROM Default RO No 000b 2:0 Function Number Contains the PEX 8114 Function Number. This number is used in the Completer ID. 7:3 Device Number Contains the PEX 8114 Device Number. Forward Transparent Bridge mode: This number is assigned by the number in the Device Number field of the Type 0 Configuration Write Request targeted to this device on the PCI Express interface. Reverse Transparent Bridge mode: The Device Number is assigned by the Device Number field in the Type 0 Configuration Transaction targeted to the device on the PCI-X interface. This number is used in the Completer ID. RO/Fwd RO/Rev No No 00h 1Fh 15:8 Bus Number This number is a second register for software to read the value of the Bus Number written into the Primary Bus Number at offset 18h. This number is used in the Completer ID. RO No 00h RO/Fwd RO/Rev No Yes 0 1 RO/Fwd RO/Rev No No 0 1 RO/Fwd RWC/Rev No No 0 0 RWC/Fwd RWC/Rev No No 0 0 16 64-Bit Device Pertains to the PCI-X interface in Reverse Transparent Bridge mode. 1 = Indicates that the PCI-X interface has 64 AD lines 17 133 MHz Capable Pertains to the PCI-X interface in Forward Transparent Bridge mode and PCI-X mode. When set to 1, indicates that the PCI-X interface is capable of operating with a clock frequency of 133 MHz. 0 = Maximum operating clock frequency is 66 MHz 1 = Maximum operating clock frequency is 133 MHz 18 Split Completion Discarded Pertains to the PCI-X interface in Reverse Transparent Bridge mode. This bit is set if the bridge discards a Split Completion propagating downstream toward the secondary bus because the Requester would not accept it. 0 = Split Completion is not discarded 1 = Split Completion is discarded 19 Unexpected Split Completion Pertains to the PCI-X interface in Reverse Transparent Bridge mode and the PCI Express interface in Forward Transparent Bridge mode. This bit is set if a Split Completion is received on the PCI-X interface and there is no matching request. 0 = Unexpected Split Completion is not received 1 = Unexpected Split Completion was received 238 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI-X Capability Registers Register 14-24. 5Ch PCI-X Bridge Status (Cont.) Bit(s) 20 Description Split Completion Overrun Pertains to the PCI-X interface in Reverse Transparent Bridge mode. This bit is set if the bridge terminates a Split Completion on the secondary bus with Retry or Disconnect at Next ADB because the bridge buffers are full. Used by algorithms that optimize the Downstream Split Transaction Control register Split Transaction Commitment Limit field setting. (Refer to the PCI-X r2.0a, Appendix D, for further details.) The bridge is also permitted to set this bit in other situations that indicate that the bridge commitment limit is overly high. For example, if the bridge stores immediate Completion data in the same buffer area as Split Completion data, the Completer executes the transaction as an Immediate transaction, and the bridge disconnects the transaction because the buffers became full. Type Serial EEPROM Default RO/Fwd RWC/Rev No No 0 0 RWC/Fwd RWC/Rev No No 0 0 0 = Bridge accepted all Split Completions 1 = Bridge terminated a Split Completion with Retry or Disconnect at Next ADB because the bridge buffers are full 21 Split Request Delayed Pertains to the PCI-X interface in Reverse Transparent Bridge mode and the PCI Express interface in Forward Transparent Bridge mode. This bit is set when the PCI-X interface cannot forward a transaction due to a lack of space specified in the Downstream Split Transaction Control register Split Transaction Commitment Limit field. (Refer to the PCI-X r2.0a, Appendix D, for further details.) 0 = Bridge does not delay a Split Request 1 = Bridge does delay a Split Request 28:22 Reserved 00h 29 Device ID Messaging Capable Not supported Cleared to 0. RO No 0 30 PCI-X 266 Capable Not supported Cleared to 0. RO No 0 31 PCI-X 533 Capable Not supported Cleared to 0. RO No 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 239 Registers PLX Technology, Inc. Register 14-25. 60h Upstream Split Transaction Control Type Serial EEPROM Default 15:0 Split Transaction Capacity Indicates the Buffer Size (in ADQs) available for storage of Completions for requests on the secondary interface that are addressing Completers on the primary interface. RO No 0010h 31:16 Split Transaction Commitment Limit Indicates the Sequence Size (in units of ADQs) for Read transactions forwarded by the bridge from Requesters on the secondary interface, to Completers on the primary interface. (Refer to the PCI-X r2.0a, Appendix D, for a detailed discussion of Split Transaction commitment.) When the bridge stores Split Read Completions in the same buffer as other Split Completions, this register indicates the size of all upstream Split Transactions of these types that the bridge is permitted to commit to at one time. Software is permitted to program this register to a value greater than or equal to the contents of the Split Transaction Capacity register. A value less than the contents of the Split Transaction Capacity register causes unspecified results. When this register is set to FFFFh, the bridge is permitted to forward all Split Requests of any size, regardless of available Buffer space (an exception is described in Section 2.6, “Strapping Signals”). Software is permitted to change this register at any time. The most recent value of the register is used each time the bridge forwards a Split Transaction. If the register value is set to FFFFh, the bridge does not track the outstanding commitment. If the register is later set to another value, the bridge does not accurately track outstanding commitments until all outstanding commitments complete. Systems that require accurate limitation of Split Transactions must never set this register to FFFFh. They must quiesce all devices that initiate traffic that crosses the bridge in this direction after the register setting is changed from FFFFh. An algorithm for setting this register is not specified. System software is permitted to use any method for selecting the value for this register. Individual devices and device drivers are not permitted to change the value of this register except under control of a system-level configuration routine. (Refer to the PCI-X r2.0a, Appendix D, for details and setting recommendations.) Default value of this field equals the value stored in field [15:0] (Split Transaction Capacity). RW Yes 0010h Bit(s) 240 Description ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI-X Capability Registers Register 14-26. 64h Downstream Split Transaction Control Type Serial EEPROM Default 15:0 Split Transaction Capacity Indicates the Buffer Size (in ADQs) available for storage of Completions for requests on the primary interface that are addressing Completers on the secondary interface. RO No 0010h 31:16 Split Transaction Commitment Limit Indicates the Sequence Size (in units of ADQs) for Read transactions forwarded by the bridge from Requesters on the primary interface, to Completers on the secondary interface. (Refer to the PCI-X r2.0a, Appendix D, for a detailed discussion of Split Transaction commitment.) If the bridge stores Split Read Completions in the same buffer as other Split Completions, this register indicates the size of all downstream Split Transactions of these types that the bridge is permitted to commit to at one time. Software is permitted to program this register to a value greater than or equal to the contents of the Split Transaction Capacity register. A value less than the contents of the Split Transaction Capacity register causes unspecified results. If this register is set to FFFFh, the bridge is permitted to forward all Split Request of any size, regardless of available buffer space. Software is permitted to change this register at any time. The most recent value of the register is used each time the bridge forwards a Split Transaction. When the register value is set to FFFFh, the bridge does not track the outstanding commitment. If the register is later set to another value, the bridge does not accurately track outstanding commitments until all outstanding commitments complete. Systems that require accurate limitation of Split Transactions must never set this register to FFFFh. They must quiesce all devices that initiate traffic that crosses the bridge in this direction after the register setting is changed from FFFFh. An algorithm for setting this register is not specified. System software is permitted to use any method for selecting the value for this register. Individual devices and device drivers are not permitted to change the value of this register except under control of a system-level configuration routine. (Refer to the PCI-X r2.0a for details and setting recommendations.) Default value of this field equals the value stored in the Split Transaction Capacity field. RW Yes 0010h Bit(s) Description ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 241 Registers 14.8 PLX Technology, Inc. PCI Express Capability Registers This section details the PEX 8114 PCI Express Capability registers. Hot Plug Capability, Command, Status, and Events are included in these registers. Table 14-7 defines the register map. Table 14-7. PCI Express Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCI Express Capability 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Next Capability Pointer (00h) Capability ID (10h) Device Capability 6Ch Device Status Device Control 70h Link Capability Link Status 74h Reserved Link Control Slot Capability Reserved 242 Reserved (Forward Transparent Bridge Mode) Slot Status (Reverse Transparent Bridge Mode) 68h Reserved (Forward Transparent Bridge Mode) Slot Control (Reverse Transparent Bridge Mode) 78h 7Ch 80h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-27. 68h PCI Express Capability List and Capability Bit(s) Description Type Serial EEPROM Default RO Yes 10h RO Yes 00h RO Yes 1h RO/Fwd RO/Rev Yes Yes 7h 8h RO/Fwd RO/Rev No Yes 0 1 RO Yes 0000_0b PCI Express Capability List 7:0 15:8 Capability ID Set to 10h, as required by the PCI Express Base 1.0a. Next Capability Pointer 00h = PCI Express Capability is the last capability in the PEX 8114 Capabilities list The PEX 8114 Extended Capabilities list starts at 100h. PCI Express Capability 19:16 Capability Version Set to 1h, as required by the PCI Express Base 1.0a. 23:20 Device/Port Type Set at reset, as required by the PCI Express Base 1.0a. Slot Implemented 24 Forward Transparent Bridge mode: 0 = Disables or connects to an upstream port Reverse Transparent Bridge mode: 0 = Disables or connects to an integrated componenta 1 = Indicates that the downstream port connects to a slot, as opposed to being connected to an integrated component or being disabled a. 29:25 Interrupt Message Number The serial EEPROM writes 0000_0b, because the Base message and MSI messages are the same. 31:30 Reserved 00b The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0h, indicating that the PEX 8114 downstream port connects to an integrated component or is disabled. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 243 Registers PLX Technology, Inc. Register 14-28. 6Ch Device Capability Bit(s) 2:0 Description Maximum Payload Size Supported 000b = PEX 8114 supports 128-byte maximum Payload 001b = PEX 8114 supports 256-byte maximum Payload Type Serial EEPROM Default RO Yes 001b No other encodings are supported. 4:3 Phantom Functions Supported Not supported Cleared to 00b. RO Yes 00b 5 Extended Tag Field Supported 0 = Maximum Tag field is 5 bits 1 = Maximum Tag field is 8 bits RO Yes 0 RO Yes 000b RO Yes 000b 8:6 Endpoint L0s Acceptable Latency Not supported Because the PEX 8114 is a bridge and not an endpoint, it does not support this feature. 000b = Disables the capability 11:9 Endpoint L1 Acceptable Latency Not supported Because the PEX 8114 is a bridge and not an endpoint, it does not support this feature. 000b = Disables the capability 244 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-28. 6Ch Device Capability (Cont.) Type Serial EEPROM Default 12 Attention Button Present Forward Transparent Bridge mode: For the PEX 8114 PCI Express interface, value of 1 indicates that an Attention Button is implemented on that adapter board. The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0, indicating that an Attention Button is not present on an adapter board for which the PEX 8114 provides the system interface. Reverse Transparent Bridge mode: Not valid for Reverse Transparent Bridge mode. HwInit/Fwd RO/Rev Yes No 1 0 13 Attention Indicator Present Forward Transparent Bridge mode: For the PEX 8114 PCI Express interface, value of 1 indicates that an Attention Indicator is implemented on the adapter board. The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0, indicating that an Attention Indicator is not present on an adapter board for which the PEX 8114 provides the system interface. Reverse Transparent Bridge mode: Not valid for Reverse Transparent Bridge mode. HwInit/Fwd RO/Rev Yes No 1 0 14 Power Indicator Present Forward Transparent Bridge mode: For the PEX 8114 PCI Express interface, value of 1 indicates that a Power Indicator is implemented on the adapter board. The PEX 8114 Serial EEPROM register Initialization capability is used to change this value to 0, indicating that a Power Indicator is not present on an adapter board for which the PEX 8114 provides the system interface. Reverse Transparent Bridge mode: Not valid for Reverse Transparent Bridge mode. HwInit/Fwd RO/Rev Yes No 1 0 Bit(s) Description 17:15 Reserved 25:18 Captured Slot Power Limit Value Forward Transparent Bridge mode: The upper limit on power supplied by the slot to the PEX 8114 is determined by multiplying the value in this field by the value in field [27:26] (Captured Slot Power Limit Scale). Reverse Transparent Bridge mode: Not valid for Reverse Transparent Bridge mode. 000b RO/Fwd RO/Rev Yes No 00h 00h RO/Fwd RO/Rev Yes No 00b 00b Captured Slot Power Limit Scale Forward Transparent Bridge mode: The upper limit on power supplied by the slot to the PEX 8114 is determined by multiplying the value in this field by the value in field [25:18] (Captured Slot Power Limit Value). 27:26 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 Reverse Transparent Bridge mode: Not valid for Reverse Transparent Bridge mode. 31:28 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0h 245 Registers PLX Technology, Inc. Register 14-29. 70h Device Status and Control Bit(s) Description Type Serial EEPROM Default Device Control 0 Correctable Error Reporting Enabled 0 = Disables 1 = Enables the PEX 8114 to report Correctable errors RW Yes 0 1 Non-Fatal Error Reporting Enabled 0 = Disables 1 = Enables the PEX 8114 to report Non-Fatal errors RW Yes 0 2 Fatal Error Reporting Enabled 0 = Disables 1 = Enables the PEX 8114 to report Fatal errors RW Yes 0 3 Unsupported Request Reporting Enable 0 = Disables 1 = Enables the PEX 8114 to report Unsupported Request errors RW Yes 0 4 PCI Express Relaxed Ordering Enabled Not supported Cleared to 0. RO No 0 RW Yes 000b 7:5 Maximum Payload Size Power-on/reset value is 000b, indicating that initially the PEX 8114 is configured to support a Maximum Payload Size of 128 bytes. Software can change this field to configure the PEX 8114 to support Payload Sizes of 256 or 128. Software must not change this field to values other than those indicated by the Device Capability register Maximum Payload Size Supported field (offset 6Ch[2:0]). 000b = Indicates that initially, the PEX 8114 port is configured to support a Maximum Payload Size of 128 bytes 001b = Indicates that initially, the PEX 8114 port is configured to support a Maximum Payload Size of 256 bytes No other encodings are supported. 246 8 Extended Tag Field Enable Not supported Cleared to 0. RO No 0 9 Phantom Functions Enable Not supported Cleared to 0. RO No 0 10 AUX Power PM Enable Not supported Cleared to 0. RO No 0 11 No Snoop Enable Not supported Cleared to 0. RO No 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-29. 70h Device Status and Control (Cont.) Bit(s) Description Type Serial EEPROM Default RW Yes 010b RW Yes 0 RWC Yes 0 RWC Yes 0 RWC Yes 0 RWC Yes 0 Maximum Read Request Size Specifies the maximum size (in bytes) of a Read request generated by the PEX 8114. 14:12 15 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes (default) 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved Bridge Configuration Retry Enable Device Status 16 Correctable Error Detected Set when the PEX 8114 detects a Correctable error, regardless of the bit 0 (Correctable Error Reporting Enabled) state. 0 = PEX 8114 did not detect a Correctable error 1 = PEX 8114 detected a Correctable error 17 Non-Fatal Error Detected Set when the PEX 8114 detects a Non-Fatal error, regardless of the bit 1 (Non-Fatal Error Reporting Enabled) state. 0 = PEX 8114 did not detect a Non-Fatal error 1 = PEX 8114 detected a Non-Fatal error 18 Fatal Error Detected Set when the PEX 8114 detects a Fatal error, regardless of the bit 2 (Fatal Error Reporting Enabled) state. 0 = PEX 8114 did not detect a Fatal error 1 = PEX 8114 detected a Fatal error 19 Unsupported Request Detected Set when the PEX 8114 detects an Unsupported Request, regardless of the bit 3 (Unsupported Request Reporting Enable) state. 0 = PEX 8114 did not detect an Unsupported Request 1 = PEX 8114 detected an Unsupported Request 20 AUX Power Detected Not supported Cleared to 0. RO No 0 21 Transactions Pending 1 = Indicates that the bridge is waiting for a Completion from an outstanding transaction RO No 0 31:22 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 000h 247 Registers PLX Technology, Inc. Register 14-30. 74h Link Capability Bit(s) Description Type Serial EEPROM Default 3:0 Maximum Link Speed Set to 0001b, as required by the PCI Express Base 1.0a for a 2.5 Gbps PCI Express link. RO Yes 0001b 9:4 Maximum Link Width The PEX 8114 Maximum Link Width is x4 = 00_0100b. RO No 00_0100b RO Yes 11b RO No 101b RO Yes 101b Active State Power Management (ASPM) Support Active State Link PM support. Indicates the level of ASPM supported by the PEX 8114. 11:10 14:12 00b = Reserved 01b = L0s Link PM state entry is supported 10b = L1 Link PM state entry is supported 11b = L0s and L1 Link PM states are supported L0s Exit Latency Indicates the L0s Link PM state exit latency for the given PCI Express link. The value reported indicates the length of time that the PEX 8114 requires to complete the transition from the L0s to L0 Link PM state. 101b = PEX 8114 L0s Link PM state Exit Latency is between 1 and 2 µs 17:15 L1 Exit Latency Indicates the L1 Link PM state exit latency for the given PCI Express link. The value reported indicates the length of time that the PEX 8114 requires to complete the transition from the L1 to L0 Link PM state. 101b = PEX 8114 L1 Link PM state Exit Latency is between 16 and 32 µs 23:18 Reserved 31:24 Port Number The Port number is 0. 248 0-0h RO No 00h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-31. 78h Link Status and Control Bit(s) Description Type Serial EEPROM Default RW Yes 00b Link Control 1:0 Active State Power Management (ASPM) Control 00b = Disables L0s and L1 Link PM state Entries for the PEX 8114 PCI Express porta 01b = Enables only L0s Link PM state Entry 10b = Enables only L1 Link PM state Entry 11b = Enables both L0s and L1 Link PM state Entries 2 Reserved 3 Read Completion Boundary (RCB) Specifies the naturally occurring boundary upon which a Read request can be broken up into smaller Completions than the original size of the request. 0 RW Yes 0 4 Link Disable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 1 = Disables the PEX 8114 downstream PCI Express link RO/Fwd RW/Rev No Yes 0 0 5 Retrain Link Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Writing 1 to this bit causes the PEX 8114 to initiate re-training of its PCI Express link. When read, always returns 0. RO/Fwd RO/Rev No Yes 0 0 6 Common Clock Configuration 0 = PEX 8114 and the device at the other end of the PCI Express link are operating with an asynchronous Reference Clock 1 = PEX 8114 and the device at the other end of the PCI Express link are operating with a distributed common Reference Clock RW Yes 0 RW Yes 0 0 = 64 bytes 1 = 128 bytes 7 Extended Sync When set to 1, causes the PEX 8114 to transmit: • 4,096 FTS Ordered-Sets in the L0s Link PM state, • Followed by a single SKIP Ordered-Set prior to entering the L0 Link PM state, • Finally, transmission of 1,024 TS1 Ordered-Sets in the Recovery state. 15:8 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 00h 249 Registers PLX Technology, Inc. Register 14-31. 78h Link Status and Control (Cont.) Type Serial EEPROM Default RO Yes 1h RO Yes 00_0100b 26 Training Error Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 1 = Indicates that the PEX 8114 detected a Link Training error RO/Fwd RO/Rev No Yes 0 0 27 Link Training Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 1 = Indicates that the PEX 8114 PCI Express interface requested link training and either the link training is in progress or about to start RO/Fwd RO/Rev No No 0 0 28 Slot Clock Configuration 0 = Indicates that the PEX 8114 uses an independent clock 1 = Indicates that the PEX 8114 uses the same physical Reference Clock that the platform provides on the connector HwInit Yes 0 Bit(s) Description Link Status 19:16 Link Speed Set to 1h, as required by the PCI Express Base 1.0a for a 2.5 Gbps PCI Express link. Negotiated Link Width Link width is determined by negotiated value with attached port/lane. 25:20 00_0001b = x1 00_0010b = x2 00_0100b = x4 (default) All other encodings are not supported. The value in this field is undefined when the link is not up. 31:29 a. 250 Reserved 000b The port receiver must be capable of entering the L0s Link PM state, regardless of whether the state is disabled. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-32. 7Ch Slot Capability (Reverse Transparent Bridge Mode Only) Bit(s) Description Type Serial EEPROM Default 0 Attention Button Present Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Attention Button is not implemented 1 = Attention Button is implemented on the slot chassis of the PEX 8114 PCI Express interface RO/Fwd HwInit/Rev No Yes 0 1 1 Power Controller Present Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Power Controller is not implemented 1 = Power Controller is implemented for the slot of the PEX 8114 PCI Express interface RO/Fwd HwInit/Rev No Yes 0 1 2 MRL Sensor Present Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = MRL Sensor is not implemented 1 = MRL Sensor is implemented on the slot chassis of the PEX 8114 PCI Express interface RO/Fwd HwInit/Rev No Yes 0 1 3 Attention Indicator Present Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Attention Indicator is not implemented 1 = Attention Indicator is implemented on the slot chassis of the PEX 8114 PCI Express interface RO/Fwd HwInit/Rev No Yes 0 1 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 251 Registers PLX Technology, Inc. Register 14-32. 7Ch Slot Capability (Reverse Transparent Bridge Mode Only) (Cont.) Bit(s) Description Type Serial EEPROM Default 4 Power Indicator Present Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Power Indicator is not implemented 1 = Power Indicator is implemented on the slot chassis of the PEX 8114 PCI Express interface RO/Fwd HwInit/Rev No Yes 0 1 5 Hot Plug Surprise Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = No device in the PEX 8114 PCI Express interface slot is removed from the system without prior notification 1 = Device in the PEX 8114 PCI Express interface slot can be removed from the system without prior notification RO/Fwd HwInit/Rev No Yes 0 0 6 Hot Plug Capable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = PEX 8114 PCI Express interface slot is not capable of supporting Hot Plug operations 1 = PEX 8114 PCI Express interface slot is capable of supporting Hot Plug operations RO/Fwd HwInit/Rev No Yes 0 1 Slot Power Limit Value Forward Transparent Bridge mode: Do not change in Forward Transparent Bridge mode. Reverse Transparent Bridge mode: The maximum power available from the PEX 8114 PCI Express interface is determined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by field [16:15] (Slot Power Limit Scale). RO/Fwd HwInit/Rev No Yes 00h 19h RO/Fwd HwInit/Rev No Yes 00b 00b 14:7 16:15 Slot Power Limit Scale Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: The maximum power available from the PEX 8114 PCI Express interface is determined by multiplying the value in this field by the value specified in field [14:7] (Slot Power Limit Value). 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x 18:17 Not supported 31:19 Physical Slot Number Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Specifies a non-zero identification number for the PEX 8114 PCI Express port slot. 252 00b RO/Fwd HwInit/Rev No Yes 0-0h 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-33. 80h Slot Status and Control (Reverse Transparent Bridge Mode Only) Type Serial EEPROM Default 0 Attention Button Pressed Enabled Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Function is disabled 1 = Enables a Hot Plug Interrupt or Wakeup event on an Attention Button Pressed event on the PEX 8114 PCI Express port RO/Fwd RW/Rev No Yes 0 0 1 Power Fault Detector Enable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Function is disabled 1 = Enables a Hot Plug Interrupt or Wakeup event on a Power Fault Detected event on the PEX 8114 PCI Express port RO/Fwd RW/Rev No Yes 0 0 2 MRL Sensor Changed Enable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Function is disabled 1 = Enables a Hot Plug Interrupt or Wakeup event on an MRL Sensor Changed event on the PEX 8114 PCI Express port RO/Fwd RW/Rev No Yes 0 0 3 Presence Detect Changed Enable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Function is disabled 1 = Enables a Hot Plug Interrupt or Wakeup event on a Presence Detect Changed event on the PEX 8114 PCI Express port RO/Fwd RW/Rev No Yes 0 0 Bit(s) Description Slot Control ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 253 Registers PLX Technology, Inc. Register 14-33. 80h Slot Status and Control (Reverse Transparent Bridge Mode Only) (Cont.) Bit(s) Description Type Serial EEPROM Default 4 Command Completed Interrupt Enable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Function is disabled 1 = Enables a Hot Plug Interrupt or Wakeup event when a command is completed by the Hot Plug Controller on the PEX 8114 PCI Express port RO/Fwd RW/Rev No Yes 0 0 5 Hot Plug Interrupt Enable Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: 0 = Function is disabled 1 = Enables a Hot Plug Interrupt on any enabled Hot Plug events for the PEX 8114 PCI Express port RO/Fwd RW/Rev No Yes 0 0 RO/Fwd RW/Rev No Yes 00b 11b Attention Indicator Control Forward Transparent Bridge mode: Do not change for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Controls the Attention Indicator on the PEX 8114 PCI Express port slot. 7:6 00b = Reserved – Writes are ignored 01b = Turns On indicator to constant On state 10b = Causes indicator to Blink 11b = Turns Off indicator Writes cause the PEX 8114 PCI Express port to transmit the appropriate Attention Indicator messages. Reads return the PEX 8114 PCI Express port Attention Indicator’s current state. 254 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI Express Capability Registers Register 14-33. 80h Slot Status and Control (Reverse Transparent Bridge Mode Only) (Cont.) Bit(s) Description Type Serial EEPROM Default RO/Fwd RW/Rev No Yes 00b 11b RO/Fwd RW/Rev No Yes 0 1 Power Indicator Control Forward Transparent Bridge mode: Do not change for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Controls the Power Indicator on the PEX 8114 PCI Express port slot. 9:8 00b = Reserved – Writes are ignored 01b = Turns On indicator to constant On state 10b = Causes indicator to Blink 11b = Turns Off indicator Writes cause the PEX 8114 PCI Express port to transmit the appropriate Power Indicator message. Reads return the PEX 8114 PCI Express port Power Indicator’s current state. 10 Power Controller Control Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Controls the PEX 8114 PCI Express port Slot Power Controller. 0 = Turns On the Power Controller; requires some delay to be effective 1 = Turns Off the Power Controller 11 15:12 Not supported Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0 0-0h 255 Registers PLX Technology, Inc. Register 14-33. 80h Slot Status and Control (Reverse Transparent Bridge Mode Only) (Cont.) Type Serial EEPROM Default 16 Attention Button Pressed Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 PCI Express port slot Attention Button is pressed. RO/Fwd RWC/Rev No Yes 0 0 17 Power Fault Detected Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 PCI Express port Slot Power Controller detects a Power Fault at the slot. RO/Fwd RWC/Rev No Yes 0 0 18 MRL Sensor Changed Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Set to 1 when an MRL state change is detected on the PEX 8114 PCI Express port slot. RO/Fwd RWC/Rev No Yes 0 0 19 Presence Detect Changed Forward Transparent Bridge mode: Not valid for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Set to 1 when a Presence Detect Change is detected on the PEX 8114 PCI Express port slot. RO/Fwd RWC/Rev No Yes 0 0 20 Command Completed Forward Transparent Bridge mode: Do not change for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Set to 1 when the PEX 8114 PCI Express port slot Hot Plug Controller completes an issued command. RO/Fwd RWC/Rev No Yes 0 0 RO/Fwd RO/Rev No Yes 0 0 RO/Fwd RO/Rev No Yes 0 0 Bit(s) Description Slot Status 21 MRL Sensor State Forward Transparent Bridge mode: Do not change for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Reveals the PEX 8114 PCI Express port MRL Sensor’s current state. 0 = MRL Sensor is closed 1 = MRL Sensor is open 22 Presence Detect State Forward Transparent Bridge mode: Do not use for Forward Transparent Bridge mode. Reverse Transparent Bridge mode: Reveals the PEX 8114 PCI Express port slot’s current Presence state. 0 = Slot is empty 1 = Slot is occupied 23 31:24 256 Not supported Reserved 0 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.9 Device-Specific Indirect Configuration Mechanism Registers Device-Specific Indirect Configuration Mechanism Registers This section details the PEX 8114 Device-Specific Indirect Configuration Mechanism registers. Table 14-8 defines the register map. Table 14-8. Device-Specific Indirect Configuration Mechanism Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Configuration Address Window F8h Configuration Data Window FCh Register 14-34. F8h Configuration Address Window Bit(s) Description Type Serial EEPROM Default 2:0 Function Number [2:0] RO/Fwd RW/Rev No No 000b 000b 7:3 Device Number [4:0] RO/Fwd RW/Rev No No 0000_0b 0000_0b 15:8 Bus Number [7:0] RO/Fwd RW/Rev No No 00h 00h 25:16 Register DWord Address [9:0] RO/Fwd RW/Rev No No 000h 000h 30:26 Reserved 31 0h Configuration Enable RO/Fwd RW/Rev No No 0 0 Type Serial EEPROM Default RO/Fwd RW/Rev No No 0000_0000h 0000_0000h Register 14-35. FCh Configuration Data Window Bit(s) 31:0 Description Software selects a register by writing into the Register Address Window, write or read that register using this register. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 257 Registers 14.10 PLX Technology, Inc. Device Serial Number Extended Capability Registers This section details the PEX 8114 Device Serial Number Extended Capability registers. Table 14-9 defines the register map. Table 14-9. Device Serial Number Extended Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Next Capability Offset (FB4h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version (1h) Extended Capability ID (0003h) 100h Serial Number (Lower DW) 104h Serial Number (Higher DW) 108h Register 14-36. 100h Device Serial Number Extended Capability Bit(s) Description Type Serial EEPROM Default 15:0 Extended Capability ID Set to 0003h, as required by the PCI Express Base 1.0a. RO Yes 0003h 19:16 Capability Version Set to 1h, as required by the PCI Express Base 1.0a. RO Yes 1h 31:20 Next Capability Offset Set to FB4h, which is the Advanced Error Reporting Capability structure. RO Yes FB4h Type Serial EEPROM Default RO Yes 0000_0EDFh Type Serial EEPROM Default RO Yes 0000_0001h Register 14-37. 104h Serial Number (Lower DW) Bit(s) 31:0 Description Serial Number[31:0] Lower half of a 64-bit register. Value set by Serial EEPROM register initialization. Register 14-38. 108h Serial Number (Higher DW) Bit(s) 31:0 258 Description Serial Number[63:32] Upper half of a 64-bit register. Value set by Serial EEPROM register initialization. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.11 Power Budget Extended Capability Registers Power Budget Extended Capability Registers This section details the PEX 8114 Power Budget Extended Capability registers. Table 14-10 defines the register map. Table 14-10. Power Budget Extended Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version (1h) Next Capability Offset (148h) Extended Capability ID (0004h) Reserved 138h Data Select Power Budget Data Reserved 13Ch 140h Power Budget Capability 144h Register 14-39. 138h Power Budget Extended Capability Bit(s) Description Type Serial EEPROM Default 15:0 Extended Capability ID Set to 0004h, as required by the PCI Express Base 1.0a. RO Yes 0004h 19:16 Capability Version Set to 1h, as required by the PCI Express Base 1.0a. RO Yes 1h 31:20 Next Capability Offset Set to 148h, which addresses the Virtual Channel Extended Capability structure. RO Yes 148h Register 14-40. 13Ch Data Select Bit(s) Description Type Serial EEPROM Default 7:0 Data Select Indexes the Power Budget Data reported by way of eight Power Budget Data registers and selects the DWord of Power Budget Data that appears in each Power Budget Data register. Index values start at 0, to select the first DWord of Power Budget Data; subsequent DWords of Power Budget Data are selected by increasing index values 1 to 7. RW Yes 00h 31:8 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 259 Registers PLX Technology, Inc. Register 14-41. 140h Power Budget Data Bit(s) Description Type Serial EEPROM Default Note: There are eight registers that can be programmed by way of the serial EEPROM. Each register has a different port power configuration. Each configuration is selected by writing to the Data Select register Data Select field (offset 13Ch[7:0]). 7:0 Base Power Eight registers. Specifies (in Watts) the base power value in the operating condition. This value must be multiplied by the Data Scale to produce the actual power consumption value. RO Yes 00h RO Yes 00b RO Yes 000b RO Yes 00b RO Yes 000b RO Yes 000b Data Scale Specifies the scale to apply to the Base Power value. The power consumption of the device is determined by multiplying the Base Power field contents with the value corresponding to the encoding returned by this field. 9:8 12:10 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x PM Sub-State 000b = PEX 8114 is in the default Power Management sub-state PM State Current Device Power Management (PM) state. 14:13 00b = D0 Device PM state 11b = D3 Device PM state All other encodings are reserved. Type Type of operating condition. 17:15 000b = PME Auxiliary 001b = Auxiliary 010b = Idle 011b = Sustained 111b = Maximum All other encodings are reserved. Power Rail Power Rail of operating condition. 20:18 000b = Power 12V 001b = Power 3.3V 010b = Power 1.8V 111b = Thermal All other encodings are reserved. 31:21 Reserved 0-0h Register 14-42. 144h Power Budget Capability Bit(s) 0 31:1 260 Description System Allocated 1 = Power budget for the device is included within the system power budget Reserved Type Serial EEPROM Default HwInit Yes 1 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.12 Virtual Channel Extended Capability Registers Virtual Channel Extended Capability Registers This section details the PEX 8114 Virtual Channel Extended Capability registers. Table 14-11 defines the register map. Table 14-11. Virtual Channel Extended Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version (1h) Next Capability Offset (000h) Extended Capability ID (0002h) 148h Port VC Capability 1 14Ch Port VC Capability 2 (Not Supported) 150h Port VC Status (Not Supported) Port VC Control (Not Supported) 154h VC0 Resource Capability (Not Supported) 158h VC0 Resource Control 15Ch VC0 Resource Status Reserved 160h 164h – Reserved 1C4h Register 14-43. 148h Virtual Channel Extended Capability Bit(s) Description Type Serial EEPROM Default 15:0 Extended Capability ID Set to 0002h, as required by the PCI Express Base 1.0a. RO Yes 0002h 19:16 Capability Version Set to 1h, as required by the PCI Express Base 1.0a. RO Yes 1h 31:20 Next Capability Offset Cleared to 000h, indicating that the Virtual Channel Extended Capability is the last extended capability in the Extended Capability list. RO Yes 000h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 261 Registers PLX Technology, Inc. Register 14-44. 14Ch Port VC Capability 1 Bit(s) 0 3:1 4 Description Extended VC Count 0 = PEX 8114 supports only the default Virtual Channel 0 (VC0) 1 = Reserved Type Serial EEPROM Default RO No 0 Reserved 000b Low-Priority Extended VC Count For Strict Priority arbitration, indicates the number of extended Virtual Channels (those in addition to the default Virtual Channel 0) that belong to the Low-Priority Virtual Channel group for the PEX 8114. RO No 0 0 = For the PEX 8114, only the default Virtual Channel 0 belongs to the Low-Priority Virtual Channel group 1 = Reserved 7:5 Reserved 000b 9:8 Reference Clocks Not supported Cleared to 00b. RO No 00b 11:10 Port Arbitration Table Entry Size Not supported Cleared to 00b. RO No 00b 31:12 Reserved 0-0h Register 14-45. 150h Port VC Capability 2 Bit(s) Description 1:0 VC Arbitration Capability Not supported Cleared to 00b. 23:2 Reserved 31:24 VC Arbitration Table Offset Not supported Cleared to 00h. 262 Type Serial EEPROM Default RO No 00b 0-0h RO No 00h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Virtual Channel Extended Capability Registers Register 14-46. 154h Port VC Status and Control Bit(s) Description Type Serial EEPROM Default Port VC Control 0 Load VC Arbitration Table Not supported Cleared to 0. RO No 0 1 VC Arbitration Select Not supported Cleared to 0. RO No 0 15:2 Reserved 0-0h Port VC Status 16 31:17 VC Arbitration Table Status Not supported Cleared to 0. RO No Reserved 0 0-0h Register 14-47. 158h VC0 Resource Capability Bit(s) 0 13:1 Description Port Arbitration Capability Not supported Cleared to 0. Type Serial EEPROM Default RO No 0 Reserved 0-0h 14 Advanced Packet Switching Not supported Cleared to 0. RO No 0 15 Reject Snoop Transactions Not supported Cleared to 0. RO No 0 Maximum Time Slots Not supported Cleared to 000_0000b. RO No 000_0000b 22:16 23 31:24 Reserved Port Arbitration Table Offset Not supported Cleared to 00h. 0 RO ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved No 00h 263 Registers PLX Technology, Inc. Register 14-48. 15Ch VC0 Resource Control Bit(s) 0 7:1 15:8 Description TC/VC0 Map The PEX 8114 supports only VC0. Traffic Class 0 (TC0) must be mapped to VC0. By default, Traffic Classes [7:1] are mapped to VC0. Type Serial EEPROM RO Yes RW Yes Default FFh Reserved 00h Load Port Arbitration Table Not supported Cleared to 0. RO No 0 19:17 Port Arbitration Select Not supported Cleared to 000b. RO No 000b 23:20 Reserved 26:24 VC0 ID Defines the PEX 8114 PCI Express VC0 ID code. Because this is the default VC0, it is cleared to 000b. 30:27 Reserved 16 31 0-0h RO Yes 000b 0-0h VC0 Enable 0 = Not allowed 1 = Enables PEX 8114 PCI Express default VC0 RO Yes 1 Type Serial EEPROM Default Register 14-49. 160h VC0 Resource Status Bit(s) 15:0 Reserved 0000h 16 Port Arbitration Table Status Not supported Cleared to 0. RO No 0 17 VC0 Negotiation Pending 0 = VC0 negotiation completed 1 = VC0 initialization is not complete for the PEX 8114 PCI Express link RO Yes 1 31:18 264 Description Reserved 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.13 Device-Specific Registers Device-Specific Registers The registers described in this section are unique to the PEX 8114 device, are not referenced in the PCI Express Base 1.0a, and pertain to the PCI Express interface. Table 14-12 defines the register map. Note: In Reverse Transparent Bridge mode, this register group is accessed using a Memory-Mapped cycle or the Device-Specific Indirect Configuration mechanism. It is recommended that these register values not be changed. Table 14-12. Device-Specific Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1C8h Device-Specific Registers – Error Checking and Debug … 1FCh Device-Specific Registers – Physical Layer 200h … 2C4h 2C8h Device-Specific Registers – Content-Addressable Memory Routing … 6BCh 6C0h Device-Specific Registers – Base Address Shadow … 73Ch Reserved 740h – 9ECh 9F0h Device-Specific Registers – Ingress Credit Handler B7Ch Reserved B80h – BFCh C00h … C10h Internal Credit Handler Virtual Channel and Type Threshold Registers F70h … F7Ch ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 265 Registers 14.13.1 Table 14-13. PLX Technology, Inc. Device-Specific Registers – Error Checking and Debug Device-Specific Error Checking and Debug Register Map (PCI Express Interface) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECC Check Disable 1C8h Reserved Device-Specific Error 32-Bit Error Status (Factory Test Only) 1CCh Reserved Device-Specific Error 32-Bit Error Mask (Factory Test Only) 1D0h 1D4h – 1DCh Reserved Power Management Hot Plug User Configuration 1E0h Egress Control and Status 1E4h Reserved Bad TLP Count 1E8h Reserved Bad DLLP Count 1ECh TLP Payload Length Count 1F0h Reserved 1F4h Reserved ACK Transmission Latency Limit Reserved 266 1F8h 1FCh ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-50. 1C8h ECC Check Disable Bit(s) Description Type Serial EEPROM Default 0 ECC 1-Bit Error Check Disable 0 = RAM 1-Bit Soft Error Check is enabled 1 = Disables RAM 1-Bit Soft Error Check RW Yes 0 1 ECC 2-Bit Error Check Disable 0 = RAM 2-Bit Soft Error Check is enabled 1 = Disables RAM 2-Bit Soft Error Check RW Yes 0 31:2 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 267 Registers PLX Technology, Inc. Register 14-51. 1CCh Device-Specific Error 32-Bit Error Status (Factory Test Only) Bit(s) Note: 0 Description Type Serial EEPROM Default RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 All errors in register offset 1CCh generate MSI/INTA# interrupts, when enabled. Completion FIFO Overflow Status 0 = No overflow detected 1 = Completion FIFO Overflow detected when 4-deep Completion FIFO for ingress, or 2-deep Completion FIFO for egress, overflows Egress PRAM Soft-Error Overflow Egress Packet RAM 1-bit Soft Error Counter overflow. 1 0 = No error detected 1 = Egress PRAM 1-bit Soft Error (8-bit Counter) overflow when destination packet RAM 1-bit soft error count is greater than or equal to 256, it generates an MSI/INTA# interrupt, if enabled Egress LLIST Soft-Error Overflow Egress Link-List RAM 1-bit Soft Error Counter overflow. 2 3 4 5 6 0 = No error detected 1 = Egress Link-List 1-bit Soft Error (8-bit Counter) overflow when destination module link lists RAM 1-bit soft error count is greater than or equal to 256, it generates an MSI/INTA# interrupt, if enabled Egress PRAM ECC Error Egress Packet RAM 2-bit error detection. 0 = No error detected 1 = Egress PRAM 2-bit ECC error detected Egress LLIST ECC Error Egress Link-List RAM 2-bit error detection. 0 = No error detected 1 = Egress Link-List 2-bit ECC error detected Ingress RAM 1-Bit ECC Error Source Packet RAM 1-bit soft error detection. 0 = No error detected 1 = Ingress RAM 1-BIT ECC error detected Egress Memory Allocation Unit (MAU) 1-Bit Soft Error Counter Overflow Egress Memory Allocation/De-allocation RAM 1-bit soft error count is greater than or equal to 8. 0 = No error detected 1 = Egress MAU 1-bit Soft Error overflow 7 Egress Memory Allocation Unit (MAU) 2-Bit Soft Error Egress Packet Memory Allocation/De-allocation RAM 2-bit error detection. 0 = No 2-bit error detected 1 = Egress MAU 2-bit soft error detected 268 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-51. 1CCh Device-Specific Error 32-Bit Error Status (Factory Test Only) (Cont.) Bit(s) 8 9 10 11 Description Ingress RAM Uncorrectable ECC Error Ingress Packet RAM 2-bit Error detection. 0 = No 2-bit error detected 1 = Packet RAM Uncorrectable ECC error detected Ingress LLIST 1-Bit ECC Error Ingress Link-List RAM 1-bit soft error detection. 0 = No error detected 1 = 1-bit ECC error detected Ingress LLIST Uncorrectable ECC Error Ingress packet Link-List RAM 2-bit error detection. 0 = No 2-bit error detected 1 = Ingress Link-List Uncorrectable ECC Error detected Credit Update Timeout Status No useful credit update to make forward progress for 512 ms or 1s (disabled by default). Type Serial EEPROM Default RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 0 = No Credit Update Timeout detected 1 = Credit Update Timeout completed 12 13 INCH Underrun Error Ingress Credit Underrun. 0 = No error detected 1 = Credit underrun error detected Ingress Memory Allocation Unit 1-Bit Soft Error Counter Overflow Ingress Memory Allocation/De-allocation RAM 1-bit Soft Error count greater than or equal to 8. 0 = No error detected 1 = 1-bit Soft Error Counter is > 8 14 Ingress Memory Allocation Unit 2-Bit Soft Error Ingress Memory Allocation/De-allocation RAM 2-bit error detection for Transaction Layer Ingress Memory Allocation/De-allocation unit. 0 = No error detected 1 = 2-bit soft error detected 31:15 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 269 Registers PLX Technology, Inc. Register 14-52. 1D0h Device-Specific Error 32-Bit Error Mask (Factory Test Only) Bit(s) Note: 270 Description Type Serial EEPROM Default Error logging is enabled in register offset 1D0h, by default. 0 Completion FIFO Overflow Mask 0 = If enabled, error generates MSI/INTA# interrupt 1 = Completion FIFO Overflow Status bit is masked/disabled RWS Yes 1 1 Egress PRAM Soft-Error Overflow Mask 0 = No effect on reporting activity 1 = Egress PRAM Soft-Error Overflow bit is masked/disabled RWS Yes 1 2 Egress LLIST Soft-Error Overflow Mask 0 = No effect on reporting activity 1 = Egress LLIST Soft-Error Overflow bit is masked/disabled RWS Yes 1 3 Egress PRAM ECC Error Mask 0 = No effect on reporting activity 1 = Egress PRAM ECC Error bit is masked/disabled RWS Yes 1 4 Egress LLIST ECC Error Mask 0 = No effect on reporting activity 1 = Egress LLIST ECC Error bit is masked/disabled RWS Yes 1 5 Ingress RAM 1-Bit ECC Error Mask 0 = No effect on reporting activity 1 = Ingress RAM 1-Bit ECC Error bit is masked/disabled RWS Yes 1 6 Egress Memory Allocation Unit 1-Bit Soft Error Counter Overflow Mask 0 = No effect on reporting activity 1 = Egress Memory Allocation Unit (MAU) 1-Bit Soft Error Counter Overflow bit is masked/disabled RWS Yes 1 7 Egress Memory Allocation Unit 2-Bit Soft Error Mask 0 = No effect on reporting activity 1 = Egress Memory Allocation Unit (MAU) 2-Bit Soft Error bit is masked/disabled RWS Yes 1 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-52. 1D0h Device-Specific Error 32-Bit Error Mask (Factory Test Only) (Cont.) Bit(s) Description Type Serial EEPROM Default 8 Ingress RAM Uncorrectable ECC Error Mask 0 = No effect on reporting activity 1 = Ingress RAM Uncorrectable ECC Error bit is masked/disabled RWS Yes 1 9 Ingress LLIST 1-Bit ECC Error Mask 0 = No effect on reporting activity 1 = Ingress RAM 1-Bit ECC Error bit is masked/disabled RWS Yes 1 10 Ingress LLIST Uncorrectable ECC Error Mask 0 = No effect on reporting activity 1 = Ingress LLIST Uncorrectable ECC Error bit is masked/disabled RWS Yes 1 11 Credit Update Timeout Status Mask 0 = No effect on reporting activity 1 = Credit Update Timeout Status bit is masked/disabled RWS Yes 1 12 INCH Underrun Error Mask 0 = No effect on reporting activity 1 = INCH Underrun Error bit is masked/disabled RWS Yes 1 13 Ingress Memory Allocation Unit 1-Bit Soft Error Counter Overflow Mask 0 = No effect on reporting activity 1 = TIC_MAU 1-bit Soft Error Counter-overflow is masked/disabled RWS Yes 1 14 Ingress Memory Allocation Unit 2-Bit Soft Error Mask 0 = Error reporting enabled using interrupts 1 = 2-Bit soft error reporting is masked/disabled RWS Yes 1 31:15 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 271 Registers PLX Technology, Inc. Register 14-53. 1E0h Power Management Hot Plug User Configuration Bit(s) 0 1 2 Description L0s Entry Idle Count Time to meet to enter the L0s Link PM state. 0 = Idle condition lasts for 1 µs 1 = Idle condition lasts for 4 µs L1 Upstream Port Receiver Idle Count For active L1 Link PM state entry. 0 = Upstream port receiver idle for 2 µs 1 = Upstream port receiver idle for 3 µs HPC PME Turn-Off Enable 1 = PME Turn-Off message is transmitted before the port is turned Off on a downstream port Type Serial EEPROM Default RW Yes 0 RW Yes 0 RW Yes 0 RO Yes 00b RO Yes 0 RO Yes 1 RW Yes 0_0000_0b HPC Tpepv Delay Slot power-applied to power-valid delay time. 4:3 5 6 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms HPC Inband Presence Detect Enable 0 = HP_PRSNT# Input ball used to detect whether a board is present in the slot 1 = SerDes Receiver Detect mechanism is used to detect whether a board is present in the slot HPC Tpvperl Delay Downstream port power-valid to Reset signal release time. 0 = 20 ms 1 = 100 ms (default) 12:7 Factory Test Only 31:13 Reserved 272 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-54. 1E4h Egress Control and Status Bit(s) Description Type Serial EEPROM Default 0 Egress Credit Update Timer Enable In this mode, when the port is not receiving credits to make forward progress and the Egress Timeout timer times out, the downstream link is brought down. RW Yes 0 0 = Egress Credit update timer disabled 1 = Egress Credit update timer enabled 1 Egress Timeout Value 0 = Minimum 512 ms (Maximum 768 ms) 1 = Minimum 1,024 ms (Maximum 1,280 ms) RW Yes 0 2 DL_Down Handling 0 = Reports unsupported request error for all TLP requests received in DL_Down state 1 = Reports unsupported request for first Posted/Non-Posted TLP request in DL_Down state – silently drops subsequent TLP requests RW Yes 0 7:3 Reserved 0-0h Link-List RAM Soft Error Count Link-List RAM 8-bit Soft Error Counter value. The Counter is shared by: • Packet Link-List RAM 15:8 • Packet Link-List De-allocation RAM • Scheduler Data RAM RO Yes 00h RO Yes 0h Counter increments for 1-bit soft errors detected in the RAM. 19:16 VC&T Encountered Timeout 0h = VC0 Posted 1h = VC0 Non-Posted 2h = VC0 Completion All other encodings are not supported. 23:20 Reserved 31:24 Packet RAM Soft Error Count Hardware increments this counter when a 1-bit Soft error in packet RAM Read is detected. 0h RO ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved No 00h 273 Registers PLX Technology, Inc. Register 14-55. 1E8h Bad TLP Count Bit(s) Description 7:0 Bad TLP Count Counts the number of TLPs with bad LCRC, or number of TLPs with a Sequence Number mismatch error. The maximum value is FFh. The Counter saturates at FFh and does not roll over to 00h. 31:8 Reserved Type Serial EEPROM Default RW Yes 00h 0000_00h Register 14-56. 1ECh Bad DLLP Count Bit(s) Description 7:0 Bad DLLP Count Counts the number of DLLPs with bad LCRC, or number of DLLPs with a Sequence Number mismatch error. The maximum value is FFh. The Counter saturates at FFh and does not roll over to 00h. 31:8 Reserved Type Serial EEPROM Default RW Yes 00h 0000_00h Register 14-57. 1F0h TLP Payload Length Count Bit(s) Description 20:0 TLP Payload Length Count Defines the TLP Payload Size transferred over the link in 1-ms period. 31:21 Reserved Type Serial EEPROM Default RW Yes 00_0000h 000h Register 14-58. 1F8h ACK Transmission Latency Limit Bit(s) Description Type Serial EEPROM Default RW Yes FFh RW Yes 00h ACK Transmission Latency Limit The value is based upon the Negotiated Link Width encoding, as listed below. Register Value Link Width Decimal Hex x1 255 FFh x2 217 D9h x4 118 76h 7:0 15:8 HPC Test Bits Factory Test Only Testing bits – must be 00h. 31:16 Reserved 274 0000h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.13.2 Table 14-14. Device-Specific Registers Device-Specific Registers – Physical Layer Device-Specific Physical Layer Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 200h – Phy User Test Pattern 0 210h Phy User Test Pattern 1 214h Phy User Test Pattern 2 218h Phy User Test Pattern 3 21Ch Physical Layer Command and Status 220h Port Configuration 224h Physical Layer Test 228h Factory Test Only 22Ch Physical Layer Port Command 230h SKIP Ordered-Set Interval 234h SerDes[0-3] Quad Diagnostics Data 238h Reserved 23Ch – SerDes Nominal Drive Current Select Reserved Reserved SerDes Drive Current Level 1 Reserved 244h 248h 24Ch Reserved 250h SerDes Drive Equalization Level Select 1 Reserved Status Data from Serial EEPROM 20Ch Serial EEPROM Status 254h 258h – Serial EEPROM Control 260h Serial EEPROM Buffer Reserved 25Ch 264h 268h – 2C4h Note: In this section, the term “SerDes quad” or “quad” refers to assembling SerDes lanes into a group of four contiguous lanes for testing purposes. The quad is defined as SerDes[0-3], which maps to Lanes [0-3] respectively. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 275 Registers PLX Technology, Inc. Register 14-59. 210h Phy User Test Pattern 0 Bit(s) 31:0 Description Test Pattern 0 Used for Digital Far-End Loopback testing. Type Serial EEPROM Default RW Yes 0-0h Type Serial EEPROM Default RW Yes 0-0h Type Serial EEPROM Default RW Yes 0-0h Type Serial EEPROM Default RW Yes 0-0h Register 14-60. 214h Phy User Test Pattern 1 Bit(s) 31:0 Description Test Pattern 1 Used for Digital Far-End Loopback testing. Register 14-61. 218h Phy User Test Pattern 2 Bit(s) 31:0 Description Test Pattern 2 Used for Digital Far-End Loopback testing. Register 14-62. 21Ch Phy User Test Pattern 3 Bit(s) 31:0 276 Description Test Pattern 3 Used for Digital Far-End Loopback testing. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-63. 220h Physical Layer Command and Status Bit(s) Description Type Serial EEPROM Default 0 Port Enumerator Enable 0 = Enumerate is not enabled 1 = Enumerate is enabled HwInit Yes 0 1 TDM Enable 0 = TDM is not enabled 1 = TDM is enabled HwInit Yes 0 2 Reserved 3 Upstream Port as Configuration Master Enable 0 = Upstream Port Cross-link is not supported 1 = Upstream Port Cross-link is supported RW Yes 0 4 Downstream Port as Configuration Slave Enable 0 = Downstream Port Cross-link is not supported 1 = Downstream Port Cross-link is supported RW Yes 0 RW Yes 0 5 6 7 0 Lane Reversal Disable Provides the ability to enable or disable lane reversal. 0 = Lane reversal is supported 1 = Lane reversal is not supported Reserved 0 FC-Init Triplet Enable Flow control Initialization. RW Yes 0 RW Yes 40h 0 = Init FL1 Triplet can be interrupted by SKIP Ordered-Set/Idle Data symbol 1 = Init FL1 Triplet not interrupted 15:8 N_FTS Value Number of Fast Training Sets (N_FTS) value to transmit in training sets. 19:16 Reserved 22:20 Number of Ports Enumerated Number of ports in current configuration. 0h 23 Reserved 24 Port 0 Deskew Buffer Error Status 1 = Deskew Buffer overflow or underflow 31:25 HwInit Yes 000b 0 RWC Yes Reserved 0 00h Register 14-64. 224h Port Configuration Bit(s) Description 2:0 Port Configuration 31:3 Reserved Type Serial EEPROM Default HwInit Yes 000b ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 277 Registers PLX Technology, Inc. Register 14-65. 228h Physical Layer Test Bit(s) Description Type Serial EEPROM Default 0 Timer Test Mode Enable 0 = Standard Physical Layer Timer parameters used 1 = Shortens Timer scale from milliseconds to microseconds RW Yes 0 1 SKIP-Timer Test Mode Enable 0 = Disables SKIP-Timer Test mode 1 = Enables SKIP-Timer Test mode RW Yes 0 2 Port_0_x1 1 = PCI Express interface is configured as x1 only RW Yes 0 3 TCB Capture Disable 0 = Training Control Bit (TCB) Capture enabled 1 = Disables TCB Capture RW Yes 0 4 Analog Loopback Enable 1 = Analog Loopback testing enabled (Loopback before elastic buffer) RW Yes 0 5 Port/SerDes Test Pattern Enable Select 1 = Bit 28 (Test Pattern Enable) selects the port, rather than SerDes[0-3] RW Yes 0 6 Reserved 7 SerDes BIST Enable SerDes Built-In Self-Test Enable. When programmed to 1 by serial EEPROM, enables SerDes internal loopback Pseudo-Random Bit Sequence (PRBS) test for 512 µs before starting link initialization. 0 RO Yes 0 RW Yes 00b PRBS Association Selects the SerDes within the quad for PRBS generation/checking. 9:8 15:10 278 00b = SerDes 0 01b = SerDes 1 10b = SerDes 2 11b = SerDes 3 Reserved 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-65. 228h Physical Layer Test (Cont.) Bit(s) 16 19:17 20 Description PRBS Enable 1 = Enables PRBS sequence generation/checking on SerDes[0-3] Type Serial EEPROM Default RW Yes 0 Reserved PRBS External Loopback The following bit commands are valid when the Physical Layer Port Command register Port 0 Loopback Command bit is set (offset 230h[0]=1). 000b RW Yes 0 0 = SerDes[0-3] establishes internal analog Loopback when bit 16=1 1 = SerDes[0-3] establishes external analog Loopback when bit 16=1 23:21 24 27:25 28 31:29 Reserved PRBS Error Count Reset When set to 1, resets the PRBS Error Counter (offset 238h[31:24]). 000b RO Yes Reserved Test Pattern Enable Enables SerDes[0-3] test pattern transmission in Digital Far-End Loopback mode. 0 000b RW Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Yes 0 000b 279 Registers PLX Technology, Inc. Register 14-66. 230h Physical Layer Port Command Bit(s) 0 1 Description Port 0 Loopback Command 0 = PCI Express interface is not enabled to proceed to Loopback Master state 1 = PCI Express interface is enabled to proceed to Loopback Master state Port 0 Scrambler Disable If a serial EEPROM load sets this bit, the scrambler is disabled in a Configuration Complete state. If software sets this bit when the link is in the Up state, hardware immediately disables its scrambler without executing the Link Training protocol. The upstream/downstream device scrambler will not be disabled. Type Serial EEPROM Default RW Yes 0 RW Yes 0 RW Yes 0 RO No 0 0 = PCI Express interface scrambler is enabled 1 = PCI Express interface scrambler is disabled Port 0 Rx L1 Only PCI Express interface Receiver enters the ASPM L1 Link PM state. 2 3 31:4 0 = PCI Express interface Receiver is allowed to go to the ASPM L0s or L1 Link PM state when an Electrical Idle Ordered-Set in the L0 Link PM state is detected 1 = PCI Express interface Receiver is allowed to go to the ASPM L1 Link PM state only when an Electrical Idle Ordered-Set in the L0 Link PM state is detected Port 0 Ready as Loopback Master PCI Express interface LTSSM established Loopback as a Master. 0 = PCI Express interface is not in Loopback Master mode 1 = PCI Express interface in is Loopback Master mode Reserved 0000_000h Register 14-67. 234h SKIP Ordered-Set Interval Bit(s) 11:0 31:12 280 Description SKIP Ordered-Set Interval SKIP Ordered-Set interval (in symbol times). 49Ch = Minimum interval (1,180 symbol times) 602h = Maximum interval (1,538 symbol times) Reserved Type Serial EEPROM Default RWS Yes 49Ch 0000_0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-68. 238h SerDes[0-3] Quad Diagnostics Data Bit(s) Note: Description Type Serial EEPROM Default SerDes[0-3] map to Lanes [0-3], respectively 9:0 Expected PRBS Data Expected PRBS SerDes[0-3] Diagnostic data. RO Yes 00h 19:10 Received PRBS Data Received PRBS SerDes[0-3] Diagnostic data. RO Yes 00h 23:20 Reserved 31:24 PRBS Error Count PRBS SerDes[0-3] Error count (0 to 255). 0h RO Yes 00h Register 14-69. 248h SerDes Nominal Drive Current Select Bit(s) Note: Description Type Serial EEPROM Default RWS Yes 00b RWS Yes 00b RWS Yes 00b RWS Yes 00b SerDes[0-3] map to Lanes [0-3], respectively 1:0 SerDes_0 Nominal Drive Current 3:2 SerDes_1 Nominal Drive Current 5:4 SerDes_2 Nominal Drive Current 7:6 SerDes_3 Nominal Drive Current 31:8 Reserved The following values for Nominal Current apply to each drive: 00b = 20 mA 01b = 10 mA 10b = 28 mA 11b = 20 mA 0000_00h Register 14-70. 24Ch SerDes Drive Current Level 1 Bit(s) Note: Description Type Serial EEPROM Default RWS Yes 0h RWS Yes 0h RWS Yes 0h RWS Yes 0h SerDes[0-3] map to Lanes [0-3], respectively 3:0 SerDes_0 Drive Current Level 7:4 SerDes_1 Drive Current Level 11:8 SerDes_2 Drive Current Level 15:12 SerDes_3 Drive Current Level 31:16 Reserved The following values represent the ratio of Actual Current/ Nominal Current (selected in SerDes Nominal Drive Current Select register) and apply to each drive: 0h = 1.00 1h = 1.05 2h = 1.10 3h = 1.15 4h = 1.20 5h = 1.25 6h = 1.30 7h = 1.35 8h = 0.60 9h = 0.65 Ah = 0.70 Bh = 0.75 Ch = 0.80 Dh = 0.85 Eh = 0.90 Fh = 0.95 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0000h 281 Registers PLX Technology, Inc. Register 14-71. 254h SerDes Drive Equalization Level Select 1 Bit(s) Note: 3:0 Description Serial EEPROM Default RWS Yes 8h RWS Yes 8h RWS Yes 8h RWS Yes 8h SerDes[0-3] map to Lanes [0-3], respectively SerDes_0 Drive Equalization Level 7:4 SerDes_1 Drive Equalization Level 11:8 SerDes_2 Drive Equalization Level 15:12 SerDes_3 Drive Equalization Level 31:16 Reserved 282 Type The following values represent the percentage of Drive Current attributable to Equalization Current and apply to each drive: IEQ / IDR De-Emphasis (dB) 0h = 0.00 1h = 0.04 2h = 0.08 3h = 0.12 4h = 0.16 5h = 0.20 6h = 0.24 7h = 0.28 8h = 0.32 9h = 0.36 Ah = 0.40 Bh = 0.44 Ch = 0.48 Dh = 0.52 Eh = 0.56 Fh = 0.60 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96 0000h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-72. 260h Serial EEPROM Status and Control Bit(s) Description Type Serial EEPROM Default RW Yes 000h RW Yes 000b RO Yes 00b RO Yes 00b Serial EEPROM Control 12:0 EepBlkAddr Serial EEPROM Block Address for 32 KB. EepCmd[2:0] Commands to the Serial EEPROM Controller. 15:13 000b = Reserved 001b = Data from bits [31:24] (Status Data from Serial EEPROM register) are written to the Serial EEPROM internal Status register 010b = Write four bytes of data from the EepBuf into the memory location pointed to by the EepBlkAddr field 011b = Read four bytes of data from the memory location pointed to by the EepBlkAddr field into the EepBuf 100b = Reset Write Enable latch 101b = Data from Serial EEPROM internal Status register written to bits [31:24] (Status Data from Serial EEPROM register) 110b = Set Write Enable latch 111b = Reserved Note: For value of 001b, only bits [31, 27:26] can be written into the serial EEPROM’s internal Status register Serial EEPROM Status EepPrsnt[1:0] Serial EEPROM Present status, unless bit 21 (CRC Disable) is set to ignore CRC checking (not recommended). 17:16 00b = Not present 01b = Serial EEPROM is present – no CRC error 10b = Reserved 11b = Serial EEPROM is present, but with CRC error – unless bit 21 (CRC Disable) is set to ignore CRC checking (not recommended) EepCmdStatus Serial EEPROM Command status 19:18 00b = Serial EEPROM Command is complete 01b = Serial EEPROM Command is not complete 10b = Serial EEPROM Command is complete, with CRC error 11b = Reserved 20 EepBlkAddrUp EepBlkAddr upper bit 13. Extends the serial EEPROM to 64 KB. RW Yes 0 21 CRC Disable 0 = Serial EEPROM input data uses CRC 1 = Serial EEPROM input data CRC disabled (not recommended) RW Yes 0 23:22 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 00b 283 Registers PLX Technology, Inc. Register 14-72. 260h Serial EEPROM Status and Control (Cont.) Bit(s) Description Type Serial EEPROM Default RW Yes 0 RW Yes 0 RW Yes 00b RO Yes 000b RW Yes 0 Status Data from Serial EEPROMa 24 25 EepRdy Serial EEPROM RDY#. 0 = Serial EEPROM is ready to transmit data 1 = Write cycle is in progress EepWen Serial EEPROM Write Enable. 0 = Serial EEPROM Write is disabled 1 = Serial EEPROM Write is enabled EepBp[1:0] Serial EEPROM Block-Write Protect bits. Block Protection options protect the top 1/4, top 1/2, or the entire serial EEPROM. PEX 8114 Configuration data is stored in the lower addresses; therefore, when using Block Protection, the entire serial EEPROM should be protected with BP[1:0]=11b. BP[1:0] Level 27:26 30:28 31 Array Addresses Protected 16-KB Device 32-KB Device 64-KB Device 00b 0 None None None 01b 1 (top 1/4) 3000h - 3FFFh 6000h - 7FFFh C000h - FFFFh 10b 2 (top 1/2) 2000h - 3FFFh 4000h - 7FFFh 8000h - FFFFh 11b 3 (All) 0000h - 3FFFh 0000h - 7FFFh 0000h - FFFFh EepWrStatus Serial EEPROM Write status. Value is 000b when serial EEPROM is not in an internal Write cycle. Note: Definition of this field varies among the serial EEPROM manufacturers. Reads of the serial EEPROM internal Status register can return 000b or 111b, depending upon the serial EEPROM that is used. EepWpen Serial EEPROM Write Protect Enable. Overrides the internal serial EEPROM Write Protect WP# input and enables/disables Writes to the Serial EEPROM Status register: • When WP# is High or EepWpen = 0, and EepWen = 1, the Serial EEPROM Status register is writable • When WP# is Low and EepWpen = 1, or EepWen = 0, the Serial EEPROM Status register is protected Notes: If the internal serial EEPROM Write Protect WP# input is Low, after software sets the EepWen bit to write-protect the Serial EEPROM Status register, the EepWen value cannot be changed to 0, nor can the EepBp[1:0] bits be cleared to disable Block Protection, until WP# is high. This bit is not implemented in certain serial EEPROMs. Refer to the serial EEPROM manufacturer’s data sheet. a. 284 Within the serial EEPROM’s internal Status register, only bits [31, 27:26] can be written. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-73. 264h Serial EEPROM Buffer Bit(s) Description Type Serial EEPROM Default 31:0 EepBuf Serial EEPROM RW buffer. Read/Write command to the corresponding Serial EEPROM Control register (offset 260h) results in a 4-byte Read/Write to or from the serial EEPROM device. RW No 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 285 Registers 14.13.3 PLX Technology, Inc. Device-Specific Registers – Content-Addressable Memory Routing The Content-Addressable Memory (CAM) Routing registers contain mirror copies of the registers used for: • Bus Number CAM – Used to determine Configuration TLP Completion route This register contains a mirror copy of the PEX 8114 Primary Bus Number, Secondary Bus Number, and Subordinate Bus Number registers. • I/O CAM – Used to determine I/O request routing This register contains a mirror copy of the PEX 8114 I/O Base and I/O Limit registers. • Address-Mapping CAM (AMCAM) – Used to determine Memory request route These registers contain mirror copies of the PEX 8114 Memory Base and Limit, Prefetchable Memory Base and Limit, Prefetchable Memory Base Upper 32 Bits, and Prefetchable Memory Limit Upper 32 Bits registers. These registers are automatically updated by hardware. Modifying these registers by writing to the addresses listed herein is not recommended. These mirror copies are used by the PCI Express interface. Table 14-15. Device-Specific CAM Routing Register Map for PCI Express Interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 2C8h – Bus Number CAM 8 2E8h Reserved 2ECh – Reserved I/O CAM_8 Reserved 314h 318h 31Ch – 3C4h AMCAM_8 Memory Limit and Base 3C8h AMCAM_8 Prefetchable Memory Limit and Base[31:0] 3CCh AMCAM_8 Prefetchable Memory Base[63:32] 3D0h AMCAM_8 Prefetchable Memory Limit[63:32] 3D4h Reserved 3D8h – 65Ch TIC Control 660h Reserved 664h TIC Port Enable (Factory Test Only) 668h Reserved IOCAM_8 Limit[31:16] 66Ch – IOCAM_8 Base[31:16] Reserved 286 2E4h 69Ch 6A0h 6A4h – 6BCh ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.13.3.1 Device-Specific Registers Device-Specific Registers – Bus Number CAM Register 14-74. 2E8h Bus Number CAM 8 Bit(s) Description Type Serial EEPROM Default 7:0 Primary Bus Number Mirror copy of the Bus Number register Primary Bus Number field (offset 18h[7:0]). RW Yes 00h 15:8 Secondary Bus Number Mirror copy of the Bus Number register Secondary Bus Number field (offset 18h[15:8]). RW Yes FFh 23:16 Subordinate Bus Number Mirror copy of the Bus Number register Subordinate Bus Number field (offset 18h[23:16]). RW Yes 00h 31:24 Reserved 14.13.3.2 00h Device-Specific Registers – I/O CAM Register 14-75. 318h I/O CAM_8 Bit(s) 3:0 Description I/O Addressing Capability 1h = 32-bit I/O addressing Type Serial EEPROM Default RO Yes 1h RW Yes Fh RO Yes 1h RW Yes 0h All other encodings are reserved. 7:4 11:8 I/O Base Mirror copy of I/O Base value. I/O Addressing Capability 1h = 32-bit I/O addressing All other encodings are reserved. 15:12 I/O Limit Mirror copy of I/O Limit value. 31:16 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0000h 287 Registers PLX Technology, Inc. 14.13.3.3 Device-Specific Registers – Address-Mapping CAM Address-Mapping CAM (AMCAM) registers contain mirror images of the PEX 8114 Memory Base and Limit, Prefetchable Memory Base and Limit, Prefetchable Memory Base Upper 32 Bits, and Prefetchable Memory Limit Upper 32 Bits registers. Register 14-76. 3C8h AMCAM_8 Memory Limit and Base Bit(s) Description 3:0 Reserved 15:4 Memory Base Mirror copy of Memory Base value. 19:16 Reserved 31:20 Memory Limit Mirror copy of Memory Limit value. Type Serial EEPROM Default 0h RW Yes FFFh 0h RW Yes 000h Type Serial EEPROM Default RO Yes 1h RW Yes FFFh RO Yes 1h RW Yes 000h Type Serial EEPROM Default RW Yes FFFF_FFFFh Type Serial EEPROM Default RW Yes 0000_0000h Register 14-77. 3CCh AMCAM_8 Prefetchable Memory Limit and Base[31:0] Bit(s) 3:0 Description Addressing Support 0h = 32-bit addressing supported 1h = 64-bit addressing supported All other encodings are reserved. 15:4 19:16 Prefetchable Memory Base AMCAM_8 Prefetchable Memory Base[31:20]. Addressing Support 0h = 32-bit addressing supported 1h = 64-bit addressing supported All other encodings are reserved. 31:20 Prefetchable Memory Limit AMCAM_8 Prefetchable Memory Limit[31:20]. Register 14-78. 3D0h AMCAM_8 Prefetchable Memory Base[63:32] Bit(s) 31:0 Description Prefetchable Memory Base[63:32] AMCAM_8 Prefetchable Memory Base[63:32]. Register 14-79. 3D4h AMCAM_8 Prefetchable Memory Limit[63:32] Bit(s) 31:0 288 Description Prefetchable Memory Limit[63:32] AMCAM_8 Prefetchable Memory Limit[63:32]. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.13.3.4 Device-Specific Registers Device-Specific Registers – Transaction Layer Ingress Control The Transaction Layer Ingress Control (TIC) registers offer both user-accessible and Factory Test control bits. The user can access TIC Control bits [1:0] and control various aspects of downstream Configuration accesses in Reverse Transparent Bridge mode. (Refer to the TIC Control register description.) Table 14-16. Device-Specific TIC Control Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIC Control 660h Reserved 664h TIC Port Enable (Factory Test Only) 668h Register 14-80. 660h TIC Control Type Serial EEPROM Default RW Yes 0 Disable Unsupported Request Response for Reserved Configuration Registers 1 = Disables completions with an Unsupported Request (UR) status from being returned when Configuration Writes are attempted on Device-Specific registers RW Yes 0 TIC Control Factory Test Only RW Yes 0-0h Bit(s) Description TIC Control Valid in Reverse Transparent Bridge mode. 0 = Configuration Transactions from the downstream port are not accepted 1 = Configuration transactions (Type 0) coming upstream from a downstream port are allowed to enter the device and the Type 1 Header of the bridge is accessible 0 1 31:2 Register 14-81. 668h TIC Port Enable (Factory Test Only) Bit(s) 31:0 Description TIC_UNP_Status Factory Test Only 14.13.3.5 Table 14-17. Type Serial EEPROM Default RW Yes FFFF_FFFFh Device-Specific Register – I/O CAM Base and Limit Upper 16 Bits Device-Specific I/O CAM Base and Limit Upper 16 Bits Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IOCAM_8 Limit[31:16] 66Ch – IOCAM_8 Base[31:16] Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 69Ch 6A0h 6A4h – 6BCh 289 Registers PLX Technology, Inc. Register 14-82. 6A0h I/OCAM_8 Base and Limit Upper 16 Bits Bit(s) Description Type Serial EEPROM Default 15:0 IOCAM_8 Base[31:16] I/O Base Upper 16 bits. RW Yes FFFFh 31:16 IOCAM_8 Limit[31:16] I/O Limit Upper 16 bits. RW Yes 0000h 290 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.13.4 Device-Specific Registers Device-Specific Registers – Base Address Shadow The PEX 8114 registers defined in Table 14-18 each contain a shadow copy of their respective Type 1 Configuration Base Address registers (Base Address 0 and Base Address 1, offsets 10h and 14h, respectively). Table 14-18. Device-Specific Base Address Shadow Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 6C0h – 6FCh BAR0_8 700h BAR1_8 704h Reserved 708h – 73Ch Register 14-83. 700h BAR0_8 Bit(s) 0 2:1 Description Memory Space Indicator When enabled, the Base Address register maps the PEX 8114 Configuration registers into Memory space. Memory Map Type 00b = Base Address register is 32 bits wide and can be mapped anywhere in the 32-bit Memory space 10b = Base Address register is 64 bits wide and can be mapped anywhere in the 64-bit Address space Type Serial EEPROM Default RO No 0 RO Yes 00b RO No 0 All other encodings are reserved. 3 Prefetchable Base Address register maps the PEX 8114 Configuration registers into Non-Prefetchable Memory space, by default. 12:4 Reserved 000h 31:13 Base Address Base Address for Device-Specific Memory-Mapped Configuration mechanism. RW Yes 0000_0h Register 14-84. 704h BAR1_8 Bit(s) Description Type Serial EEPROM Default RW Yes 0000_0000h 31:0 Base Address 1 For 64-bit addressing, Base Address 1 extends Base Address 0, to provide the upper 32 Address bits when the BAR0_8 register Memory Map Type field (offset 700h[2:1]) is set to 10b. Read-Only when the BAR0_8 register is not enabled as a 64-bit BAR [Memory Map Type field (offset 700h[2:1]) is not equal to 10b]. RO No 0000_0000h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 291 Registers PLX Technology, Inc. 14.13.5 Table 14-19. Device-Specific Registers – Ingress Credit Handler Device-Specific Ingress Credit Handler (INCH) Register Map for PCI Express Interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 9F0h INCH FC Update Pending Timer Reserved Reserved 9F4h 9F8h Reserved INCH Mode 9FCh INCH Threshold VC0 Posted A00h INCH Threshold VC0 Non-Posted A04h INCH Threshold VC0 Completion A08h Reserved A0Ch – B7Ch Register 14-85. 9F4h INCH FC Update Pending Timer Bit(s) Description Type Serial EEPROM Default RW Yes 00h Update Timer Update the pending timer, using the guidelines as follows. Maximum Packet Size 7:0 128 bytes 256 bytes 31:8 Link Width Recommended Timer Count x1 76h x2 40h x4 24h x1 D0h x2 6Ch x4 3Bh Reserved 0000_00h Register 14-86. 9FCh INCH Mode Bit(s) Description Type Serial EEPROM Default RO Yes FFh 7:0 Maximum Mode Enable Factory Test Only 15:8 Reserved 19:16 Factory Test Only RW Yes 0h 23:20 Pending Timer Source Pending timer register – uses serial EEPROM values. RW Yes 0h 31:24 Reserved 292 00h 00h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.13.5.1 Device-Specific Registers Ingress Credit Handler Threshold Virtual Channel Registers There are three Ingress Credit Handler (INCH) Threshold Virtual Channel (VC) registers. These registers represent the maximum number of Headers or Payload credits allocated to VC0, for each type of transaction. The register names and address/location are defined in Table 14-19. The following registers describe the data that applies to these registers. Register 14-87. A00h INCH Threshold VC0 Posted Bit(s) Description Type Serial EEPROM Default Posted credits are used for VC0 Memory Write and Message transactions. 2:0 Reserved 8:3 Payload Payload = 0_0111_0b. 13:9 Header Header = 01_100b. 31:14 Reserved 000b RW Yes 30Eh 0-0h Register 14-88. A04h INCH Threshold VC0 Non-Posted Bit(s) Description Type Serial EEPROM Default Non-Posted credits are used for VC0 Memory Read, I/O Read, I/O Write, Configuration Read, and Configuration Write transactions. 8:0 Payload Payload = 0_0000_1010b. 13:9 Header Header = 01_010b. 31:14 Reserved RW Yes 140Ah 0-0h Register 14-89. A08h INCH Threshold VC0 Completion Bit(s) Description Type Serial EEPROM Default Completion credits are used for VC0 Memory Read, I/O Read, I/O Write, Configuration Read, and Configuration Write transaction Completions. 2:0 Reserved 8:3 Payload Payload = 0_0110_0b. 13:9 Header Header = 01_010b. 31:14 Reserved 000b RW ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Yes 28Ch 0-0h 293 Registers 14.13.6 PLX Technology, Inc. Internal Credit Handler Virtual Channel and Type Threshold Registers This section defines the Internal Credit Handler (ITCH) Virtual Channel (VC) and Type [P (Posted), NP (Non-Posted), and Cpl (Completion)] (VC&T) Threshold registers for the PCI Express and PCI-X interfaces. 14.13.6.1 ITCH VC&T Threshold Registers – PCI Express Interface Device-Specific The ITCH VC&T Threshold registers defined in Table 14-20 control internal traffic from the PCI Express interface to the PCI-X interface. The threshold (Packet Count) units are equivalent to 8 beats, where each beat can be up to 20 bytes. Therefore, a programmed value of 1 represents 160 bytes, 2 represents 320 bytes, and so forth. The entire TLP (Header, Payload, and ECRC, if any) is used to determine a total byte size, and the total byte size is divided by 20 and rounded up to the nearest integer, to determine the number of beats. Every 8 beats counts as 1 threshold unit. The Upper Packet Count is the high threshold. If more units than the programmed upper count are queued, no more packets can be scheduled across the internal fabric. Note: Previously scheduled packets arrive in their entirety, completely unaffected by the cut-off signal. The Lower Packet Count is the low threshold. After cutting off a VC&T due to the high threshold, that VC&T is turned On again after the count returns below the low threshold. The upper and lower counts must be different, and the upper number must be at least two units larger than the lower number. Table 14-20. Device-Specific ITCH VC&T Threshold Register Map for PCI Express Interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI Express Interface ITCH VC&T Threshold_1 C00h PCI Express Interface ITCH VC&T Threshold_2 C04h Reserved 294 C08h – C10h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-90. C00h PCI Express Interface ITCH VC&T Threshold_1 Bit(s) Description Type Serial EEPROM Default 4:0 VC0 Posted Upper Packet Count VC0 Posted upper packet beat limit. RW Yes 10h 7:5 Not used RW Yes 000b 12:8 VC0 Posted Lower Packet Count VC0 Posted lower packet beat limit. RW Yes 08h 15:13 Not used RW Yes 000b 20:16 VC0 Non-Posted Upper Packet Count VC0 Non-Posted upper packet beat limit. RW Yes 04h 23:21 Not used RW Yes 000b 28:24 VC0 Non-Posted Lower Packet Count VC0 Non-Posted lower packet beat limit. RW Yes 01h 31:29 Not used RW Yes 000b Type Serial EEPROM Default Register 14-91. C04h PCI Express Interface ITCH VC&T Threshold_2 Bit(s) Description 4:0 VC0 Completion Upper Packet Count VC0 Completion upper packet beat limit. RW Yes 10h 7:5 Not used RW Yes 000b 12:8 VC0 Completion Lower Packet Count VC0 Completion lower packet beat limit. RW Yes 08h 15:13 Not used RW Yes 000b 20:16 VC1 Posted Upper Packet Count VC1 Posted upper packet beat limit. This information is listed for internal and serial EEPROM configuration only – not to be changed by users. RW Yes 04h Note: Although the PEX 8114 supports only VC0, this field is used for internal transactions, such as shadow Writes. 23:21 Not used RW Yes 000b 28:24 VC1 Posted Lower Packet Count VC1 Posted lower packet beat limit. This information is listed for internal and serial EEPROM configuration only – not to be changed by users. RW Yes 01h RW Yes 000b Although the PEX 8114 supports only VC0, this field is used for internal transactions, such as shadow Writes. Note: 31:29 Not used ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 295 Registers 14.13.6.2 PLX Technology, Inc. ITCH VC&T Threshold Registers – PCI-X Interface Device-Specific The ITCH VC&T Threshold registers defined in Table 14-21 control internal traffic from the PCI-X interface to the PCI Express interface. The threshold (Packet Count) units are equivalent to 8 beats, where each beat can be up to 20 bytes. Therefore, a programmed value of 1 represents 160 bytes, 2 represents 320 bytes, and so forth. The entire TLP (Header, Payload, and ECRC, if any) is used to determine a total byte size, and the total byte size is divided by 20 and rounded up to the nearest integer, to determine the number of beats. Every 8 beats counts as 1 threshold unit. The Upper Packet Count is the high threshold. If more units than the programmed upper count are queued, no more packets can be scheduled across the internal fabric. Note: Previously scheduled packets arrive in their entirety, completely unaffected by the cut-off signal. The Lower Packet Count is the low threshold. After cutting off a VC&T due to the high threshold, when the count returns below the low threshold, that VC&T is again turned on. The upper and lower counts must be different, and the upper number must be at least two units larger than the lower number. Table 14-21. Device-Specific ITCH VC&T Threshold Register Map for PCI-X Interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI-X Interface ITCH VC&T Threshold_1 F70h PCI-X Interface ITCH VC&T Threshold_2 F74h Reserved 296 F78h – F7Ch ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Device-Specific Registers Register 14-92. F70h PCI-X Interface ITCH VC&T Threshold_1 Bit(s) Description Type Serial EEPROM Default 4:0 VC0 Posted Upper Packet Count VC0 Posted upper packet beat limit. RW Yes 10h 7:5 Not used RW Yes 000b 12:8 VC0 Posted Lower Packet Count VC0 Posted lower packet beat limit. RW Yes 08h 15:13 Not used RW Yes 000b 20:16 VC0 Non-Posted Upper Packet Count VC0 Non-Posted upper packet beat limit. RW Yes 04h 23:21 Not used RW Yes 000b 28:24 VC0 Non-Posted Lower Packet Count VC0 Non-Posted lower packet beat limit. RW Yes 01h 31:29 Not used RW Yes 000b Type Serial EEPROM Default Register 14-93. F74h PCI-X Interface ITCH VC&T Threshold_2 Bit(s) Description 4:0 VC0 Completion Upper Packet Count VC0 Completion upper packet beat limit. RW Yes 10h 7:5 Not used RW Yes 000b 12:8 VC0 Completion Lower Packet Count VC0 Completion lower packet beat limit. RW Yes 08h 15:13 Not used RW Yes 000b 20:16 VC1 Posted Upper Packet Count VC1 Posted upper packet beat limit. This information is listed for internal and serial EEPROM configuration only – not to be changed by users. RW Yes 04h Note: Although the PEX 8114 supports only VC0, this field is used for internal transactions, such as shadow Writes. 23:21 Not used RW Yes 000b 28:24 VC1 Posted Lower Packet Count VC1 Posted lower packet beat limit. This information is listed for internal and serial EEPROM configuration only – not to be changed by users. RW Yes 01h RW Yes 000b Although the PEX 8114 supports only VC0, this field is used for internal transactions, such as shadow Writes. Note: 31:29 Not used ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 297 Registers 14.14 Table 14-22. PLX Technology, Inc. PCI-X Device-Specific Registers PCI-X Device-Specific Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCI-X Interface Device-Specific Error 32-Bit Error Status (Factory Test Only) F80h PCI-X Interface Device-Specific Error 32-Bit Error Mask (Factory Test Only) F84h Reserved 298 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI-X Interface Completion Buffer Timeout F88h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 PCI-X Device-Specific Registers Register 14-94. F80h PCI-X Interface Device-Specific Error 32-Bit Error Status (Factory Test Only) Bit(s) Note: 0 Description Type Serial EEPROM Default RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 RWCS Yes 0 All errors in offset F80h generate MSI/INTA# interrupts, if enabled. Device-Specific Error Completion FIFO Overflow Status 0 = No overflow is detected 1 = Completion FIFO Overflow is detected when 4-deep Completion FIFO for ingress, or 2-deep Completion FIFO for egress, overflows Egress PRAM Soft Error Overflow Egress Packet RAM 1-bit Soft Error Counter overflow. 1 0 = No error is detected 1 = Egress PRAM 1-bit Soft Error (8-bit Counter) overflow when destination packet RAM 1-bit soft error count is greater than or equal to 256, it generates an MSI/INTA# interrupt, if enabled Egress LLIST Soft Error Overflow Egress Link-List RAM 1-bit Soft Error Counter overflow. 2 3 4 5 7:6 8 31:9 0 = No error is detected 1 = Egress Link-List 1-bit Soft Error (8-bit Counter) overflow when destination module link lists RAM 1-bit soft error count is greater than or equal to 256, it generates an MSI/INTA# interrupt, if enabled Egress PRAM ECC Error Egress Packet RAM 2-bit error detection. 0 = No error is detected 1 = Egress PRAM 2-bit ECC error is detected Egress LLIST ECC Error Egress Link-List RAM 2-bit error detection. 0 = No error is detected 1 = Egress Link-List 2-bit ECC error is detected Ingress RAM 1-Bit ECC Error Source Packet RAM 1-bit soft error detection. 0 = No error is detected 1 = Ingress RAM 1-BIT ECC error is detected Reserved Ingress RAM Uncorrectable ECC Error Ingress Packet RAM 2-bit Error detection. 0 = No 2-bit error is detected 1 = Packet RAM Uncorrectable ECC error is detected 00b RWCS Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Yes 0 0-0h 299 Registers PLX Technology, Inc. Register 14-95. F84h PCI-X Interface Device-Specific Error 32-Bit Error Mask (Factory Test Only) Bit(s) Type Serial EEPROM Default 0 Device-Specific Error Completion FIFO Overflow Status Mask 0 = When enabled, error generates an MSI/INTA# interrupt 1 = Device-Specific Error Completion FIFO Overflow Status bit is masked/disabled RWS Yes 1 1 Egress PRAM Soft Error Overflow Mask 0 = No effect on reporting activity 1 = Egress PRAM Soft Error Overflow bit is masked/disabled RWS Yes 1 2 Egress LLIST Soft Error Overflow Mask 0 = No effect on reporting activity 1 = Egress LLIST Soft Error Overflow bit is masked/disabled RWS Yes 1 3 Egress PRAM ECC Error Mask 0 = No effect on reporting activity 1 = Egress PRAM ECC Error bit is masked/disabled RWS Yes 1 4 Egress LLIST ECC Error Mask 0 = No effect on reporting activity 1 = Egress LLIST ECC Error bit is masked/disabled RWS Yes 1 5 Ingress RAM 1-Bit ECC Error Mask 0 = No effect on reporting activity 1 = Ingress RAM 1-Bit ECC Error bit is masked/disabled RWS Yes 1 7:6 8 31:9 Description Reserved 00b Ingress RAM Uncorrectable ECC Error Mask 0 = No effect on reporting activity 1 = Ingress RAM Uncorrectable ECC Error bit is masked/disabled RWS Yes Reserved 1 0-0h Register 14-96. F88h PCI-X Interface Completion Buffer Timeout Bit(s) Description 7:0 Target Tag Timeout 31:8 Reserved 300 Type Serial EEPROM Default RWC Yes 00h 0000_00h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.15 Root Port Registers Root Port Registers Table 14-23. Root Port Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Root Control F8Ch Root Status F90h Root Error Command F94h Root Error Status F98h Error Identification F9Ch Register 14-97. F8Ch Root Control Bit(s) Description Type Serial EEPROM Default 0 System Error on Correctable Error Enable RO/Fwd RW/Rev No Yes 0 0 1 System Error on Non-Fatal Error Enable RO/Fwd RW/Rev No Yes 0 0 2 System Error on Fatal Error Enable RO/Fwd RW/Rev No Yes 0 0 3 PME Interrupt Enable RO/Fwd RW/Rev No Yes 0 0 31:4 Reserved 0000_000h Register 14-98. F90h Root Status Bit(s) 15:0 Description PME Requester ID 16 PME Status 17 PME Pending 31:18 Type Serial EEPROM Default RO No 0000h RWC No 0 RO No Reserved 0 0000h Register 14-99. F94h Root Error Command Bit(s) Description Type Serial EEPROM Default 0 Correctable Error Reporting Enable RO/Fwd RW/Rev No Yes 0 0 1 Non-Fatal Error Reporting Enable RO/Fwd RW/Rev No Yes 0 0 2 Fatal Error Reporting Enable RO/Fwd RW/Rev No Yes 0 0 31:3 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 301 Registers PLX Technology, Inc. Register 14-100. F98h Root Error Status Bit(s) Description Type Serial EEPROM Default 0 Correctable Error Received RO/Fwd RWCS/Rev No Yes 0 0 1 Multiple Correctable Errors Received RO/Fwd RWCS/Rev No Yes 0 0 2 Uncorrectable Error Received RO/Fwd RWCS/Rev No Yes 0 0 3 Multiple Uncorrectable Errors Received RO/Fwd RWCS/Rev No Yes 0 0 4 First Uncorrectable Fatal RO/Fwd RWCS/Rev No Yes 0 0 5 Non-Fatal Error Message Received RO/Fwd RWCS/Rev No Yes 0 0 6 Fatal Error Message Received RO/Fwd RWCS/Rev No Yes 0 0 26:7 Reserved 0000_0h 31:27 Advanced Error Interrupt Message Number RO No 0000_0b Type Serial EEPROM Default Register 14-101. F9Ch Error Identification Bit(s) Description 15:0 Error Correctable Source Identification RO/Fwd ROS/Rev No No 0000h 0000h 31:16 Error Fatal/Non-Fatal Source Identification RO/Fwd ROS/Rev No No 0000h 0000h 302 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.16 Table 14-24. PCI-X-Specific Registers PCI-X-Specific Registers PCI-X-Specific Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCI Clock Enable, Strong Ordering, Read Cycle Value Prefetch ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved FA0h Reserved FA4h 303 Registers PLX Technology, Inc. Register 14-102. FA0h PCI Clock Enable, Strong Ordering, Read Cycle Value Bit(s) 3:0 Description PCI_CLKO_EN[3:0] PCI_CLKO_EN[0]=1 enables PCI_CLKO0 PCI_CLKO_EN[1]=1 enables PCI_CLKO1 PCI_CLKO_EN[2]=1 enables PCI_CLKO2 PCI_CLKO_EN[3]=1 enables PCI_CLKO3 Type Serial EEPROM Default RW Yes 0h if STRAP_CLK_MST=0 Fh if STRAP_CLK_MST=1 RW Yes 0 Cache Line Prefetch Line Count Controls the number of lines prefetched during Memory Reads. 4 0 = 1 Cache Line 1 = 2 Cache Lines; used only if the Miscellaneous Control register Cache Line Size field (offset 0Ch[7:0]) is less than or equal to 16 DWords (64 bytes) 5 Disable Completion Timeout Timer Refer to Section 7.7, “Transaction Transfer Failures,” for details. RW Yes 0 6 Enable Long Completion Timeout Timer Refer to Section 7.7, “Transaction Transfer Failures,” for details. RW Yes 1 7 Disable BAR0 RW Yes 0 8 Force Strong Ordering After data is returned to the PEX 8114 in response to a Read request, the PEX 8114 Retries the same transaction until complete and does not attempt to gather data from other outstanding transactions. RW Yes 0 9 Reserved 10 PLL Lock Control 0 Resets on loss of PLL lock, unless bits [11:10]=00b. (Refer to Table 14-25 for methods of handling loss of PLL lock.) RW Yes 0 11 PLL Lock Control 1 Reset after timer timeout on loss of PLL lock. (Refer to Table 14-25 for methods of handling loss of PLL lock.) RW Yes 0 12 Memory Read Line Multiple Enable RW Yes 0 13 Address Stepping Enable RW Yes 0 14 Sticky PCI-X PLL Loss Lock Set when the PCI-X PLL loses PLL lock. RWCS Yes 0 15 Sticky PCI Express PLL Loss Lock Set when the PCI Express PLL loses PLL lock. RWCS Yes 0 RW Yes 7FFh RWC Yes 0 26:16 27 31:28 304 0 Maximum Read Cycle Value Retry Failure Status Reserved 0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Table 14-25. PCI-X-Specific Registers Methods for Handling Loss of PLL Lock Offset FA0h[11:10] Description 00b Default. Ignores loss of PLL lock. 01b A loss of PLL lock immediately causes the PEX 8114 to reset. 10b The PEX 8114 attempts to tolerate loss of PLL lock: • When lock is re-acquired in less than 200 µs, the PEX 8114 does not reset 11b The PEX 8114 does not reset if loss of PLL lock occurs. • When lock is not re-acquired within 200 µs, the PEX 8114 is reset Register 14-103. FA4h Prefetch Bit(s) 7:0 Description Type Serial EEPROM Reserved Default 00h Prefetch Space Count Valid only in PCI mode. Not used in PCI-X mode. Specifies the number of DWords to prefetch for Memory Reads originating on the PCI Bus that are forwarded to the PCI Express interface. Only even values between 0 and 32 are allowed. When the PEX 8114 is configured as a Forward bridge, prefetching occurs for all Memory Reads of Prefetchable and Non-Prefetchable Memory space. This occurs because the BARs are not used for Memory Reads, making it impossible to determine whether the space is prefetchable. In Reverse Transparent Bridge mode, prefetching occurs only for Memory Reads that address Prefetchable Memory space. Prefetching is Quad-word aligned, in that data is prefetched to the end of a Quad-word boundary. The number of DWords prefetched is as follows: • PEX 8114 prefetches 2 DWords when the following conditions are met: 13:8 – Prefetch Space Count field is cleared to 00h, and – PCI_AD0 or PCI_AD1 is High – PCI_REQ64# is asserted (Low) RW Yes 20h • PEX 8114 prefetches 1 DWord when the following conditions are met: – Prefetch Space Count field is cleared to 00h, and – PCI_AD0 or PCI_AD1 is High – PCI_REQ64# is de-asserted (High) • When the Prefetch Space Count field contains an Even value greater than 0 and PCI_AD2 is High, the number of Prefetched DWords is 1 DWord less than the value in the Prefetch Space Count field; otherwise, the number of DWords prefetched is equal to the value in the Prefetch Space Count field. Only Even values between 0 and 32 are allowed. Odd values provide unexpected results. 31:14 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 305 Registers PLX Technology, Inc. 14.17 PCI Arbiter Registers Table 14-26. PCI Arbiter Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Arbiter 0 FA8h Arbiter 1 FACh Arbiter 2 FB0h Register 14-104. FA8h Arbiter 0 Bit(s) Description 2:0 Arbiter Allocation 0 7:3 Reserved 10:8 Arbiter Allocation 1 15:11 Reserved 18:16 Arbiter Allocation 2 23:19 Reserved 26:24 Arbiter Allocation 3 31:27 Reserved Type Serial EEPROM Default RW Yes 000b 0000_0b RW Yes 001b 0000_0b RW Yes 010b 0000_0b RW Yes 011b 0000_0b Register 14-105. FACh Arbiter 1 Bit(s) Description 2:0 Arbiter Allocation 4 7:3 Reserved 10:8 Arbiter Allocation 5 15:11 Reserved 18:16 Arbiter Allocation 6 23:19 Reserved 26:24 Arbiter Allocation 7 31:27 Reserved Type Serial EEPROM Default RW Yes 100b 0000_0b RW Yes 000b 0000_0b RW Yes RW Yes 001b 0000_0b 010b 0000_0b Register 14-106. FB0h Arbiter 2 Bit(s) Description 2:0 Arbiter Allocation 8 7:3 Reserved 10:8 Arbiter Allocation 9 23:11 Reserved 24 31:25 306 Grant Mode Reserved Type Serial EEPROM Default RW Yes 011b 0000_0b RW Yes 100b 0-0h RW Yes 0 0000_000b ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 14.18 Advanced Error Reporting Extended Capability Registers Advanced Error Reporting Extended Capability Registers This section details the Advanced Error Reporting Extended Capability registers. Table 14-27 defines the register map. Table 14-27. Advanced Error Reporting Extended Capability Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Next Capability Offset (138h) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Capability Version (1h) PCI Express Extended Capability ID (0001h) FB4h Uncorrectable Error Status FB8h Uncorrectable Error Mask FBCh Uncorrectable Error Severity FC0h Correctable Error Status FC4h Correctable Error Mask FC8h Advanced Error Capabilities and Control FCCh Header Log_0 FD0h Header Log_1 FD4h Header Log_2 FD8h Header Log_3 FDCh Secondary Uncorrectable Error Status FE0h Secondary Uncorrectable Error Mask FE4h Secondary Uncorrectable Error Severity FE8h Secondary Uncorrectable Error Pointer FECh FF0h Secondary Header Log … FFCh ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 307 Registers PLX Technology, Inc. Register 14-107. FB4h Advanced Error Reporting Enhanced Capability Header Bit(s) Description Type Serial EEPROM Default 15:0 PCI Express Extended Capability ID RO Yes 0001h 19:16 Capability Version RO Yes 1h 31:20 Next Capability Offset RO Yes 138h Type Serial EEPROM Default RWCS Yes 0 Register 14-108. FB8h Uncorrectable Error Status Bit(s) 0 3:1 4 11:5 Training Error Status 0 = No error is detected 1 = Error is detected Reserved 000b Data Link Protocol Error Status 0 = No error is detected 1 = Error is detected RWCS Yes Reserved 0 0000_000b 12 Poisoned TLP Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 13 Flow Control Protocol Error Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 14 Completion Timeout Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 15 Completer Abort Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 16 Unexpected Completion Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 17 Receiver Overflow Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 18 Malformed TLP Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 19 ECRC Error Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 20 Unsupported Request Error Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 31:21 308 Description Reserved 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Advanced Error Reporting Extended Capability Registers Register 14-109. FBCh Uncorrectable Error Mask Bit(s) 0 3:1 4 11:5 Description Training Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error Type Serial EEPROM Default RWS Yes 0 Reserved Data Link Protocol Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error 000b RWS Yes Reserved 0 0000_000b 12 Poisoned TLP Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 13 Flow Control Protocol Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 14 Completion Timeout Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 15 Completer Abort Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 16 Unexpected Completion Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 17 Receiver Overflow Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 18 Malformed TLP Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 19 ECRC Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 20 Unsupported Request Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 31:21 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 309 Registers PLX Technology, Inc. Register 14-110. FC0h Uncorrectable Error Severity Bit(s) 0 3:1 4 11:5 Training Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal Type Serial EEPROM Default RWS Yes 1 Reserved 000b Data Link Protocol Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes Reserved 1 0000_000b 12 Poisoned TLP Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 13 Flow Control Protocol Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 14 Completion Timeout Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 15 Completer Abort Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 16 Unexpected Completion Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 17 Receiver Overflow Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 18 Malformed TLP Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 19 ECRC Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 20 Unsupported Request Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 31:21 310 Description Reserved 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Advanced Error Reporting Extended Capability Registers Register 14-111. FC4h Correctable Error Status Bit(s) 0 5:1 Description Receive Error Status 0 = No error detected 1 = Error detected Type Serial EEPROM Default RWCS Yes 0 Reserved 0-0h 6 Bad TLP Status 0 = No error detected 1 = Error detected RWCS Yes 0 7 Bad DLLP Status 0 = No error detected 1 = Error detected RWCS Yes 0 8 Replay Number Rollover Status 0 = No error detected 1 = Error detected RWCS Yes 0 11:9 12 31:13 Reserved 000b Replay Timer Timeout Status 0 = No error detected 1 = Error detected RWCS Yes Reserved 0 0-0h Register 14-112. FC8h Correctable Error Mask Bit(s) 0 5:1 Description Receive Error Mask 0 = Error reporting is not masked 1 = Error reporting is masked Type Serial EEPROM Default RWS Yes 0 Reserved 0-0h 6 Bad TLP Mask 0 = Error reporting is not masked 1 = Error reporting is masked RWS Yes 0 7 Bad DLLP Mask 0 = Error reporting is not masked 1 = Error reporting is masked RWS Yes 0 8 Replay Number Rollover Mask 0 = Error reporting is not masked 1 = Error reporting is masked RWS Yes 0 11:9 12 31:13 Reserved Replay Timer Timeout Mask 0 = Error reporting is not masked 1 = Error reporting is masked 000b RWS Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Yes 0 0-0h 311 Registers PLX Technology, Inc. Register 14-113. FCCh Advanced Error Capabilities and Control Type Serial EEPROM Default First Error Pointer Identifies the bit position of the first error reported in the Uncorrectable Error Status register (offset FB8h). ROS Yes 1_1111b 5 ECRC Generation Capable 0 = ECRC generation is not supported 1 = ECRC generation is supported, but must be enabled RO Yes 1 6 ECRC Generation Enable 0 = ECRC generation is disabled 1 = ECRC generation is enabled RWS Yes 0 7 ECRC Checking Capable 0 = ECRC checking is not supported 1 = ECRC checking is supported, but must be enabled RO Yes 1 8 ECRC Checking Enable 0 = ECRC checking is disabled 1 = ECRC checking is enabled RWS Yes 0 Bit(s) 4:0 31:9 Description Reserved 0-0h Register 14-114. FD0h Header Log_0 Bit(s) 31:0 Description TLP Header_0 First DWord Header. TLP Header associated with error. Type Serial EEPROM Default ROS Yes 0-0h Type Serial EEPROM Default ROS Yes 0-0h Type Serial EEPROM Default ROS Yes 0-0h Type Serial EEPROM Default ROS Yes 0-0h Register 14-115. FD4h Header Log_1 Bit(s) 31:0 Description TLP Header_1 Second DWord Header. TLP Header associated with error. Register 14-116. FD8h Header Log_2 Bit(s) 31:0 Description TLP Header_2 Third DWord Header. TLP Header associated with error. Register 14-117. FDCh Header Log_3 Bit(s) 31:0 312 Description TLP Header_3 Fourth DWord Header. TLP Header associated with error. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Advanced Error Reporting Extended Capability Registers Register 14-118. FE0h Secondary Uncorrectable Error Status Bit(s) Description Type Serial EEPROM Default 0 Target Abort on Split Completion Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 1 Master Abort on Split Completion Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 2 Received Target Abort Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 3 Received Master Abort Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 4 Reserved 5 Unexpected Split Completion Error Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 6 Uncorrectable Split Completion Message Data Error Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 7 Uncorrectable Data Parity Error is detected Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 8 Uncorrectable Attribute Parity Error is detected Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 9 Uncorrectable Address Parity Error is detected Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 10 Delayed Transaction Discard Timer Expired Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 11 PERR# Assertion Detected 0 = No error is detected 1 = Error is detected RWCS Yes 0 12 SERR# Assertion Detected 0 = No error is detected 1 = Error is detected RWCS Yes 0 13 Internal Bridge Error Status 0 = No error is detected 1 = Error is detected RWCS Yes 0 31:14 0 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 313 Registers PLX Technology, Inc. Register 14-119. FE4h Secondary Uncorrectable Error Mask Bit(s) Description Type Serial EEPROM Default 0 Target Abort on Split Completion Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 1 Master Abort on Split Completion Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 2 Received Target Abort Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 3 Received Master Abort Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 4 Reserved 5 Unexpected Split Completion Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 6 Uncorrectable Split Completion Message Data Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 7 Uncorrectable Data Parity Error Detected Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 314 0 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Advanced Error Reporting Extended Capability Registers Register 14-119. FE4h Secondary Uncorrectable Error Mask (Cont.) Bit(s) Description Type Serial EEPROM Default 8 Uncorrectable Attribute Parity Error Detected Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 9 Uncorrectable Address Parity Error Detected Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 10 Delayed Transaction Discard Timer Expired Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 11 PERR# Assertion Detected Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 12 SERR# Assertion Detected Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 1 13 Internal Bridge Error Mask 0 = No mask is set 1 = Error reporting, first error update, and Header logging are masked for this error RWS Yes 0 31:14 Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 0-0h 315 Registers PLX Technology, Inc. Register 14-120. FE8h Secondary Uncorrectable Error Severity Bit(s) Type Serial EEPROM Default 0 Target Abort on Split Completion Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 1 Master Abort on Split Completion Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 2 Received Target Abort Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 3 Received Master Abort Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 4 Reserved 5 Unexpected Split Completion Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 6 Uncorrectable Split Completion Message Data Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 7 Uncorrectable Data Parity Error Detected Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 8 Uncorrectable Attribute Parity Error Detected Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 9 Uncorrectable Address Parity Error Detected Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 10 Delayed Transaction Discard Timer Expired Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 11 PERR# Assertion Detected Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 12 SERR# Assertion Detected Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 1 13 Internal Bridge Error Severity 0 = Error reported as non-fatal 1 = Error reported as fatal RWS Yes 0 31:14 316 Description Reserved 0 0-0h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Advanced Error Reporting Extended Capability Registers Register 14-121. FECh Secondary Uncorrectable Error Pointer Bit(s) Description 4:0 Secondary Uncorrectable Error Pointer 31:5 Reserved Type Serial EEPROM Default ROS No 0_0000b 0000_000h Register 14-122. FF0h – FFCh Secondary Header Log Bit(s) Description Type Serial EEPROM Default 35:0 Transaction Attribute ROS No 0-0h 39:36 Transaction Command Lower ROS No 0-0h 43:40 Transaction Command Upper ROS No 0-0h 63:44 Reserved 127:64 Transaction Address 0-0h ROS ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved No 0-0h 317 Registers PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 318 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 15 Test and Debug 15.1 Physical Layer Loopback Operation 15.1.1 Overview Physical Layer Loopback functions are used to test SerDes in the PEX 8114, connections between devices, SerDes of external devices, and certain PEX 8114 and external digital logic. The PEX 8114 supports five types of loopback operations, as described in Table 15-1. Additional information regarding each type is provided in the sections that follow. Table 15-1. Loopback Operations Operation Description Internal Loopback Internal Loopback mode connects SerDes serial Tx output to serial Rx input. The Pseudo-Random Bit Sequence (PRBS) generator is used to create a pseudo-random data pattern that is transmitted and returned to the PRBS checker. Analog Loopback Master Analog Loopback Master mode depends upon an external device or dumb connection (such as a cable) to loop back the transmitted data to the PEX 8114. If an external device is used, it must not include its elastic buffer in the loopback data path, because no SKIP Ordered-Sets are transmitted. Use the PRBS generator and checker to create and check the data pattern. The PEX 8114 enters Analog Loopback Master mode when the Physical Layer Port Command register Port 0 Loopback Command bit is set (offset 230h[0]=1). Digital Loopback Master As with Analog Loopback Master mode, Digital Loopback Master mode depends upon an external device to loop back the transmitted data. This method is best utilized with an external device that includes at least its elastic buffer in the loopback data path. The PEX 8114 provides a programmable data pattern generator and checker that inserts the SKIP Ordered-Set at the proper intervals. The PEX 8114 enters Digital Loopback Master mode when the Physical Layer Port Command register Port 0 Loopback Command bit is set (offset 230h[0]=1). Analog Loopback Slave The PEX 8114 enters Analog Loopback Slave mode when an external device transmits training sets with the Loopback Training Control bit set while the Physical Layer Test register Analog Loopback Enable bit is set (offset 228h[4]=1). The received data is looped back from the SerDes 10-bit receive interface to the 10-bit transmit interface. Note: There are no serializers nor deserializers in the loopback data path. Digital Loopback Slave The PEX 8114 enters Digital Loopback Slave mode when an external device transmits training sets with the Loopback Training Control bit set while the Physical Layer Test register Analog Loopback Enable bit is cleared (offset 228h[4]=0). In this mode, the data is looped back at an 8-bit level, which includes the PEX 8114 elastic buffer, 8b/10b decoder, and 8b/10b encoder in the Loopback data path. Note: There are no serializers nor deserializers in the loopback data path. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 319 Test and Debug 15.1.2 PLX Technology, Inc. Loopback Test Modes The PEX 8114 supports all Loopback modes described in the PCI Express Base 1.0a. To establish the PEX 8114 as a Loopback Master, the serial EEPROM is used to Write 1 to the Physical Layer Port Command register Port 0 Ready as Loopback Master bit (offset 230h[3]=1). This enables the PEX 8114 to set its Port 0 Loopback Command bit (offset 230h[0]=1) in the training sets during the Configuration.Linkwidth.Start state. After the PEX 8114 is established as a Loopback Master, the Physical Layer Port Command register Port 0 Ready as Loopback Master bit is set. Depending upon the capability of the Loopback Slave, the PRBS generator or Bit-Pattern generator is used to create a bit stream that is checked by checking logic. When the PEX 8114 is established as a Loopback Slave, it can operate as an Analog or Digital (default) Far-End device. • Analog Loopback mode is selected by setting the Physical Layer Test register Analog Loopback Enable bit (offset 228h[4]=1). In Analog Loopback mode, the received data is looped back from the 10-bit received data, to the 10-bit transmit data. • When Digital Loopback mode is selected (power-on default), the data is looped back from the 8-bit decoded received data to the 8-bit transmit data path. This loopback point allows the elastic buffer 8b/10b decoder, and 8b/10b encoder to be included in the test data path. Digital Loopback mode requires that SKIP Ordered-Sets are included in the data stream. 15.1.2.1 Internal Loopback Figure 15-1 illustrates the Loopback data path when Internal Loopback mode is enabled. The only items in the data path are the serializer and de-serializer. Loopback mode is used when the SerDes Built-In Self-Test (BIST) is enabled [Physical Layer Test register SerDes BIST Enable bit is set (offset 228h[7]=1)]. SerDes BIST is intended to overlap with the serial EEPROM load operation. To achieve this overlap, the SerDes BIST Enable bit is written early in the serial EEPROM load operation. After the SerDes BIST Enable bit is set, SerDes is placed in Loopback mode and the PRBS generator is started. The BIST is run for 512 µs; if an error is detected on a SerDes, then the SerDes[0-3] Quad Diagnostics Data register (offset 238h) logs the number of PRBS errors generated for the group of SerDes lanes. While the SerDes BIST is in progress, the PRBS test data is present on the external TxP and TxN balls. The Tx Pad TxN signals must have an AC-coupled, 50Ω termination to ground. The re-loading of the Serial EEPROM register load has no effect on the SerDes BIST. Figure 15-1. Internal Loopback (Analog near End) Data Path PEX 8114 320 Tx Pad PRBS G en Rx Pad PRBS Chk ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 15.1.2.2 Loopback Test Modes Analog Loopback Master Analog Loopback mode is normally used for Analog Far-End testing; however, the mode can also be used to re-create the previously described BIST by looping back the data with a cable. (Refer to Figure 15-2.) Looping back with a cable includes the internal bond, external balls, any board trace, and connectors in the test data path. (Refer to Figure 15-3.) To cause the PEX 8114 to request to become a Loopback Master, the following must be accomplished: 1. After the link is up, a Configuration Write to the Physical Layer Port Command register Port 0 Loopback Command bit (offset 230h[0]) causes the PEX 8114 to transition from the L0 Link PM state to Recovery, and then to the Loopback state: – If a cable is used for a loopback, the PEX 8114 transitions from the Configuration state to the Loopback state. Connect this cable only after the upstream link is up and Configuration Writes are possible. – If the cable is connected before the upstream device is able to set the Physical Layer Test register Analog Loopback Enable bit (offset 228h[4]=1), the link with the cable can reach the L0 Link PM state and not go to the Loopback state. – Cable length is limited only by the PCI Express drivers and cable properties. 2. After the PEX 8114 is in the Loopback state, the Physical Layer Port Command register Port 0 Ready as Loopback Master bit is set (offset 230h[3]=1): – At this time, the PRBS engine is enabled by setting the Physical Layer Test register PRBS Enable bit (offset 228h[16]=1). – The returned PRBS data is checked by the PRBS checker. Errors are logged in the SerDes[0-3] Quad Diagnostics Data register (offset 238h). Figure 15-2. Analog Far-End Loopback PCI Express Loopback Slave Device PEX 8114 Rx Pad Tx Pad Figure 15-3. Tx Pad PRBS Gen Rx Pad PRBS Chk Cable Loopback PEX 8114 Tx Pad PRBS Gen Rx Pad PRBS Chk ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 321 Test and Debug 15.1.2.3 PLX Technology, Inc. Digital Loopback Master The only difference between the Analog and Digital Loopback Master modes is that the external device is assumed to possess certain digital logic in the Loopback data path. Because this includes the elastic buffer, SKIP Ordered-Sets must be included in the test data pattern. For the PEX 8114, this precludes PRBS engine use. The PEX 8114 provides the User Data Patterns (register offsets 210h through 21Ch) transmitter for Digital Far-End Loopback testing. The following must be accomplished: 1. After Loopback Master mode is established, Configuration Writes are used to fill the Test Data Pattern registers. The Physical Layer Test register Test Pattern Enable bit is set (offset 228h[28]=1); this starts the transmission of the user data pattern on all lanes: – If the Physical Layer Test register Port/SerDes Test Pattern Enable Select bit is also set (offset 228h[5]=1), the test pattern is transmitted on all lanes, regardless of width – If the Port/SerDes Test Pattern Enable Select bit is cleared (offset 228h[5]=0), the test pattern is transmitted only on the lanes 2. SKIP Ordered-Sets are inserted at the interval determined by the value in the SKIP Interval register (default value is 1,180 symbol times) at the nearest data pattern boundary. The Test Pattern checker ignores SKIP Ordered-Sets returned by the Loopback Slave, because the number of SKIP symbols received are different from the number transmitted. 3. All other data is compared to the data transmitted and errors are logged in the SerDes[0-3] Quad Diagnostics Data register. Figure 15-4. Digital Far-End Loopback PCI Express Loopback Slave Device EBuffer PEX 8114 Rx Pad Tx Pad 322 Tx Pad UTP Tx Rx Pad UTP Chk ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 15.1.2.4 Loopback Test Modes Analog Loopback Slave The PEX 8114 becomes an Analog Loopback Slave if it receives training sets with the Loopback Training Control bit set while the Physical Layer Test register Analog Loopback Enable bit is set (offset 228h[4]=1). (Refer to Figure 15-5.) While an Analog Loopback Slave, the PEX 8114 only includes the de-serializer and serializer in the Loopback data path. The Loopback Master must provide the test data pattern and data pattern checking. It is unnecessary for the Loopback Master to include SKIP Ordered-Sets in the data pattern. Note: There is no scrambling nor de-scrambling logic in the Slave analog loopback data path. Figure 15-5. Analog Loopback Slave Mode PCI Express Loopback Master Device PEX 8114 Rx Pad Tx Pad 15.1.2.5 Tx Pad Data Gen Rx Pad Data Chk Digital Loopback Slave The PEX 8114 becomes a Digital Loopback Slave if it receives training sets with the Loopback Training Control bit set while the Physical Layer Test register Analog Loopback Enable bit is cleared (offset 228h[4]=0). (Refer to Figure 15-6.) When the PEX 8114 is a Digital Loopback Slave, it includes the elastic buffer and 8b/10b decoder and encoder in the Loopback data path. The Loopback Master must provide the test data pattern and data pattern checker. Additionally, the Master must transmit valid 8b/10b symbols, for the Loopback data from the Slave to be valid. The Loopback Master must also transmit SKIP Ordered-Sets with the data pattern. The data checker must make provisions for the PEX 8114 to return more or fewer SKIP symbols than it received. Note: There is no scrambling nor de-scrambling logic in the Slave digital loopback data path. Figure 15-6. Digital Loopback Slave Mode PCI Express Loopback Master Device PEX 8114 8b/10b Dec 8b/10b Enc EBuffer Rx Pad Tx Pad Data Tx Tx Pad Rx Pad Data Chk ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 323 Test and Debug 15.2 PLX Technology, Inc. Pseudo-Random and Bit-Pattern Generation The SerDes quad contains a PRBS generator and checker. The PRBS generator is based upon a 7-bit Linear Feedback Shift register (LFSR), which can generate up to (27 – 1) unique patterns. The PRBS logic is assigned to a SerDes within the quad by manipulating the Physical Layer Test register PRBS Association field (offset 228h[9:8]). The PRBS bit stream is used for internal SerDes or Analog Far-End Loopback testing. The PEX 8114 also provides a method of creating a repeating user-defined bit pattern. Each of the four 32-bit Test Pattern registers are loaded with a 32-bit data pattern. After the PEX 8114 is established as a Loopback Master, the Physical Layer Test register Test Pattern Enable bit is set (offset 228h[28]=1). The PEX 8114 proceeds to transmit the data pattern on all lanes, starting with Byte 0 of the Phy User Test Pattern 0 register, and continuing in sequence through the Byte 3 of the Phy User Test Pattern 3 register. SKIP Ordered-Sets are inserted at the proper intervals, which makes this method appropriate for Digital Far-End Loopback testing. The received pattern is checked/compared for errors. The errors are logged and can be retrieved, by reading the SerDes[0-3] Quad Diagnostics Data register, offset 238h, RO bits [31:24, 19:0]. 324 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 15.3 JTAG Interface JTAG Interface The PEX 8114 provides a JTAG Boundary Scan interface, which is utilized to debug board connectivity for each ball. 15.3.1 IEEE 1149.1 and 1149.6 Test Access Port The IEEE 1149.1 Test Access Port (TAP), commonly referred to as the JTAG (Joint Test Action Group) debug port, is an architectural standard described in the IEEE Standard 1149.1-1990. The IEEE Standard 1149.6-2003 defines extensions to 1149.1 to support PCI Express SerDes testing. These standards describe methods for accessing internal bridge facilities, using a four- or five-signal interface. The JTAG debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. These enhancements, which comply with IEEE Standard 1149.1b-1994 Specifications for Vendor-Specific Extensions, are compatible with standard JTAG hardware for boundary-scan system testing. • JTAG Signals – JTAG debug port implements the four required JTAG signals – JTAG_TCK, JTAG_TDI, JTAG_TDO, JTAG_TMS – and optional JTAG_TRST# signal • Clock Requirements – The JTAG_TCK signal frequency ranges from DC to 10 MHz • JTAG Reset Requirements – Refer to Section 15.3.4, “JTAG Reset Input TRST#” ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 325 Test and Debug 15.3.2 PLX Technology, Inc. JTAG Instructions The JTAG debug port provides the IEEE Standard 1149.1-1990 EXTEST, SAMPLE/PRELOAD, BYPASS, and IDCODE instructions. IEEE Standard 1149.6-2003 EXTEST_PULSE and EXTEST_TRAIN instructions are also supported. PRIVATE instructions are for PLX USE ONLY. Invalid instructions behave as BYPASS instructions. Table 15-2 defines the JTAG instructions, along with their input codes. The PEX 8114 returns the IDCODE values listed in Table 15-3. Table 15-2. JTAG Instructions Instruction Input Code EXTEST 0_0000b IDCODE 0_0001b SAMPLE/PRELOAD 0_0010b BYPASS 1_1111b EXTEST_PULSE 0_0011b EXTEST_TRAIN 0_0100b Comments IEEE Standard 1149.1-1990 IEEE Standard 1149.6-2003 PRIVATEa a. Warning: Non-PLX use of PRIVATE instructions can cause a component to operate in a hazardous manner. Table 15-3. PEX 8114 JTAG IDCODE Values Silicon Revision BC BD 326 Unit of Measure Version Part Number PLX Manufacturer Identity Least Significant Bit Bits 1000b 0001_1111_1011_0010b 001_1100_1101b 1 Hex 8h 1FB2h 1CDh 1h Decimal 8 8114 461 1 Bits 1001b 0001_1111_1011_0010b 001_1100_1101b 1 Hex 9h 1FB2h 1CDh 1h Decimal 9 8114 461 1 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 15.3.3 JTAG Boundary Scan JTAG Boundary Scan Scan Description Language (BSDL), IEEE 1149.1b-1994, is a supplement to IEEE Standard 1149.11990 and IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture. BSDL, a subset of the IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL), defines a rigorous description of testability features in components which comply with the Standard. It is used by automated test pattern generation tools for package interconnect tests and Electronic Design Automation (EDA) tools for synthesized test logic and verification. BSDL supports robust extensions used for internal test generation and to write software for hardware debug and diagnostics. The primary components of BSDL include the logical port description, physical ball map, instruction set, and boundary register description. The logical port description assigns symbolic names to the PEX 8114 balls. Each ball includes a logical type of in, out, in out, buffer, or linkage that defines the logical direction of signal flow. The physical ball map correlates the PEX 8114 logical ports to the physical balls of a specific package. A BSDL description can have several physical ball maps, and maps are provided with a unique name. Instruction set statements describe the bit patterns that must be shifted into the Instruction Register to place the PEX 8114 in the various test modes defined by the Standard. Instruction set statements also support descriptions of instructions that are unique to the PEX 8114. The Boundary register description lists each cell or shift stage of the Boundary register. Each cell has a unique number; the cell numbered 0 is the closest to the Test Data Out (TDO) ball and the cell with the highest number is closest to the Test Data In (TDI) ball. Each cell contains further details, including: • Cell type • Logical port associated with the cell • Logical function of the cell • Safe value • Control cell number • Disable value • Result value 15.3.4 JTAG Reset Input TRST# The JTAG_TRST# input ball is the asynchronous JTAG logic reset. When JTAG_TRST# is asserted, it causes the PEX 8114 JTAG TAP Controller to initialize. In addition, when the JTAG TAP Controller is initialized, it selects the PEX 8114 normal logic path (core-to-I/O). It is recommended that the following be taken into consideration when implementing the asynchronous JTAG logic reset on a board: • If JTAG functionality is required, consider one of the following: – JTAG_TRST# input signal to use a Low-to-High transition once during the PEX 8114 boot-up, along with the system PEX_PERST# signal – Hold the PEX 8114 TMS ball High while transitioning the PEX 8114 JTAG_TCK ball five times • If JTAG functionality is not required, directly connect the JTAG_TRST# signal to Ground • If the PEX 8114’s JTAG TAP Controller is not intended to be used by the design, it is recommended that a 1.5KΩ pull-down resistor be connected to the JTAG_TRST# ball, to hold the JTAG TAP Controller in the Test-Logic-Reset state, which enables standard logic operation ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 327 Test and Debug PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. 328 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 16 16.1 Electrical Specifications Introduction This chapter contains the PEX 8114 Power-On Sequencing rules and electrical specifications. 16.2 Power-On Sequence The PEX 8114 requires three voltage sources: • 3.3V for I/O power and Clock PLL power, supplied by the VDD33 and VDD33A balls • 1.35 to 1.8V for SerDes Transmitter Common-mode biasing, supplied by the VTT_PEX[1:0] balls • 1.0V ±0.1V for SerDes/Core power, supplied by the VDD10, VDD10A, and VDD10S balls VDD10, VDD10A, and VDD10S must power-up first and power-down last. If properly sequenced, all supply rails power-up within 50 ms of one another. 16.3 Absolute Maximum Ratings Maximum limits indicate the temperatures and voltages above which permanent damage can occur. Proper operation at these conditions is not guaranteed, and continuous operation of the PEX 8114 at these limits is not recommended. Table 16-1. Absolute Maximum Rating (All Voltages Referenced to VSS System Ground) Item Symbol Absolute Maximum Rating Units I/O Interface Supply Voltage VDD33 -0.5 to +4.6 V VDD33A -0.5 to +4.6 PLL Supply Voltage V a V SerDes Analog Supply Voltage VDD10A -0.3 to +1.65 SerDes Digital Supply Voltage VDD10S -0.3 to +1.65a V VTT_PEX[1:0] 2.5 V VDD10 -0.3 to +1.65 V VI -0.3 to +4.6 V VDD10 1.0 ±0.1 V TA -40 to +85 °C TSTG -65 to +150 °C SerDes Termination Supply Voltage Core (logic) Supply Voltage Input Voltage (3.3V Interface) Core VDD Voltage Operating Ambient Temperature (Industrial) Storage Temperature a. The SerDes Analog and Digital power supplies must track within 0.01V of one another. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 329 Electrical Specifications PLX Technology, Inc. Table 16-2. Capacitance for Logic/Control I/O Item Symbol Conditions Min CIN Input Ball VDD33/A = 0.0V VDD10/A/S = 0.0V COUT Output Ball CI/O Input/Output and Three-State Ball Typ Max Unit 4 6 pF 6 10 pF 6 10 pF Max Unit 375 1.93 150 mW W mW Table 16-3. Power Dissipation Parameter Power Dissipation a. Symbol Conditionsa Min. PD VDD33/A = 3.3V, ±10% VDD10/A/S = 1.0V, ±10% VTT_PEX[1:0] = 1.5V, ±10% 300 1.475 115 Typ PEX_REFCLKn/p = 100 MHz. A 250-MHz clock is synthesized from PEX_REFCLKn/p and used internally to clock the SerDes and Core logic. 16.4 Power Characteristics Table 16-4. PEX 8114 Power Estimates (Watts) (4 Lanes) Traffic Conditions Core/ SerDes Digital (VDD10) PCI Express PCI Express SerDes Digital Analog Termination (VDD10S) (VDD10A) (VTT_PEX) PLL (VDD33A) PCI-X (VDD33) Total (Watts) Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max A. Heavy 1.22 1.38 0.19 0.22 0.05 0.06 0.13 0.16 0.02 0.03 0.34 0.69 1.94 2.53 B. Medium 1.10 1.24 0.16 0.18 0.04 0.05 0.11 0.13 0.02 0.03 0.24 0.50 1.67 2.14 C. Light 0.99 1.12 0.16 0.18 0.04 0.05 0.11 0.13 0.02 0.03 0.17 0.35 1.49 1.86 A. 85% lane bandwidth utilization. All 4 lanes in the active L0 Link PM state, PCI-X @ 133 MHz, 25% switching factor, 5 pF load. B. 35% lane bandwidth utilization. All 4 lanes in the active L0 Link PM state, PCI-X @ 66 MHz, 25% switching factor, 5 pF load. C. 10% lane bandwidth utilization. All 4 lanes in the active L0 Link PM state, PCI-X @ 50 MHz, 25% switching factor, 5 pF load. 330 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 16.5 Digital Logic Interface Operating Characteristics Digital Logic Interface Operating Characteristics Unless specified otherwise, general operating conditions are: VDD33 = 3.3V ±0.3V, VDD10 = 1.0V ±0.1V, TA = -40 to +85 °C Table 16-5. Digital Logic Interface Operating Electrical Characteristics Symbol Parameter Test Conditions Ranges and Limits Units Min Typ Max Operating Voltage (I/O) 3.0 3.3 3.6 V VDD33A Operating Voltage for PLL 3.0 3.3 3.6 V VDD10 Operating Voltage (Core) 0.9 1.0 1.1 V SerDes Termination Supply Voltage 1.35 1.5 1.8 V Input Low Voltage for PCI/PCI-X inputs -0.5 0.3 VDD33 V 0.8 V VDD33 +0.5 V VDD33 VTT_PEX VIL Input Low Voltage for TTL inputsa VIH Input High Voltage for PCI/PCI-X inputs 0.5 VDD33 Input High Voltage for TTL inputsa 2.0 V 0V < VIN < VDD33 IIN -10.0b +10.0b µA ILOAD = 1500 µA 0.1 VDD33 V ILOAD = 8 mAc 0.4 V Input Leakage Current I/O balls set to High Impedance VOL Output Low Voltage PCI/PCI-X outputs Output Low Voltage TTL outputsa VOH Output High Voltage PCI/PCI-X outputs ILOAD = -500 µA 0.9 VDD33 V Output High Voltage TTL outputsa ILOAD = -8 mAd 2.4 V a. CMOS Technology designed as TTL-compatible. b. Current into the ball is shown as “+” and current out of the ball is shown as “-”. c. Exception – ILOAD = +12 mA for EE_DO ball. d. Exception – ILOAD = -12 mA for EE_DO ball. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 331 Electrical Specifications 16.5.1 PLX Technology, Inc. SerDes/Lane Interface DC Characteristics Unless specified otherwise, general operating conditions are: VDD33A = 3.3V ±0.3V, VDD10S = VDD10A = 1.0V ±0.1V, TA = -40 to +85 °C Table 16-6. SerDes Interface DC Electrical Characteristics Symbol Parameter VTT_PEX[1:0] SerDes Termination Supply Voltage Test Conditions Min Typ Max Units 1.35 1.5 165 V VDD10A SerDes Analog Supply Voltagea 0.9 1.0 1.1 V VDD10S SerDes Digital Supply Voltagea 0.9 1.0 1.1 V IDDA SerDes Supply Current PEX_REFCLKn/p = 100 MHz 65 97.5 mA IDDS SerDes Supply Current PEX_REFCLKn/p = 100 MHz 140 210 mA 87 105 mA 1.0 1.2 V 20 mV 100 mV 25 mV -7.96c dB IVTT_PEX SerDes Termination Supply Current PEX_PET Transmit Outputs VTX-DIFFp-p VTX-CM AC_P Differential Peak-to-Peak Output Voltage 1.3V < VTT < 1.6Vb RMS A Peak Output Voltage Absolute Delta between DC Common-mode during L0 Link ACTIVE-IDLE-DELTA PM state and Electrical Idle VTX-CM-DC- VTX-CM-DCLINE-DELTA 0.8 0.0 Maximum Common Mode Voltage Delta between PEX_PETn[3:0] and PEX_PETp[3:0] VTX-DE-RATIO De-Emphasis differential output voltage ratio VTX-IDLE_DIFF_PS Maximum Peak output voltage during link idle state 20 mV VTX-RCV-DETECT Amount of common-mode voltage change allowed during receiver detection 600 mV 90 mA 120 Ω ITX-SHORT 332 Output Short-Circuit current 0.0c -3.5 VTX-OUT = 0.0V ZTX-DIFF-DC Differential Output Impedance 80 ZTX-DC Output Impedance for each transmitter in all power states 40 Ω RLTX-DIFF Differential Return Loss 12 dB RLTX-CM Common-mode Return Loss 6 dB 100 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 SerDes/Lane Interface DC Characteristics Table 16-6. SerDes Interface DC Electrical Characteristics (Cont.) Symbol Parameter Test Conditions Min Typ Max Units 0.175 1.200 V 65 175 mV 150 mV PEX_PER Receive Inputs VRX-DIFFp-p VRX-IDLE-DETDIFFp-p Differential Peak-to-Peak Input Voltage Idle Detect Threshold Voltage VRX-CM AC Receiver Common-Mode Voltage for AC Coupling ZRX-DIFF-DC DC Differential Input Impedance 80 100 120 Ω DC Input Impedance 40 50 60 Ω ZRX-DC ZRX-HIGH-IMP-DC Input Impedance during Power-Down Conditions 200K Ω RLRX-DIFF Differential Return Loss 15 dB RLRX-CM Common-Mode Return Loss 6 dB a. The SerDes Analog and Digital power supplies must track within 0.01V of one another. b. For VTT voltages between 1.0 to 1.8V, refer to Table 16-1. [The VTT test condition for VTX-DIFFp-p (listed above) is derived from Table 16-1.] c. VTX-DE-RATIO can be programmed to exceed the PCI Express r1.0a of MIN -3.0, MAX -4.0. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 333 Electrical Specifications 16.6 PLX Technology, Inc. SerDes Interface AC Specifications Unless specified otherwise, general operating conditions are: VDD33A = 3.3V ± 0.3V, VDD10S = VDD10A = 1.0V ± 0.1V, TA = -40 to +85 °C Table 16-7. SerDes Interface AC Electrical Characteristics Symbol Parameter Test Conditions Min Typ Max Units 399.88 400 400.12 ps PEX_PET Transmit Outputs UI Unit Interval TTX-Rise Differential signal rise time 20 to 80% 0.125 0.3 UI TTX-Fall Differential signal fall time 20 to 80% 0.125 0.3 UI TTX-IDLE-MIN Minimum idle time for transmitter TTX-IDLE-TO- Transmitter recovery time from Idle state to fully active transmit state DIFF-DATA TTX-EYE LTX-SKEW 50 UI 20 Transmitter Eye width 0.7 UI UI Lane-to-lane static output skew for all lanes in port/link 1.3 ns 400.12 ps 10 ms PEX_PER Receive Inputs UI Unit Interval 399.88 400 Maximum time required for receiver to recognize and signal an unexpected idle DIFF-ENTERTIME on link TRX-IDLE-DETTRX-EYE TRX-SKEW Receiver Eye width 0.4 UI Total Skew 20 ns Max Units Table 16-8. PEX_REFCLK AC Specifications Symbol PEX_REFCLK VCM ClkInDC 334 Test Conditions Min 100-MHz Differential Reference Clock Input Typ 100 MHz Input Common Mode Voltage 0.6 0.65 0.7 V Input Clock Duty Cycle 40 50 60 % 1.5 ns 1.6 V TR/TF Input Clock Rise/Fall Times VSW Differential Input Voltage Swinga RTERM a. Parameter Reference Clock Differential Termination 0.25 110 Ω AC coupling is required. ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 SerDes Interface AC Specifications Table 16-9. PCI 33-MHz AC Specifications Symbol Parameter Test Conditions Min Typ Max Units Notes Tcyc PCI CLK Cycle Time 30 – ns Tval CLK to Signal Valid Delay – Bused Signals 2 11 ns 1, 2, 3, 8 Tval(ptp) CLK to Signal Valid Delay – Point-to-Point Signals 2 12 ns 1, 2, 3, 8 Ton Float to Active Delay 2 ns 1, 8, 9 Toff Active to Float Delay ns 1, 9 Tsu Input Setup Time to CLK – Bused Signals 7 ns 3, 4, 10 Tsu(ptp) Input Setup Time to CLK – Point-to-Point Signals 10, 12 ns 3, 4 Th Input Hold Time from CLK 0 ns 4 Trst Reset Active Time after Power Stable 1 ms 5 Trst-clk Reset Active Time after CLK Stable 100 µs 5 Trst-off Reset Active to Output Float Delay ns 5, 6 28 40 Trrsu PCI_REQ64# to PCI_RST# Setup Time 10Tcyc Trrh PCI_RST# to PCI_REQ64# Hold Time 0 Trhfa PCI_RST# High to First Configuration Access 225 clocks Trhff PCI_RST# High to First PCI_FRAME# Assertion 5 clocks Tckskew Clock Skew between Any PCI_CLKO[3:0] Outputs ns 50 ns 130 ps Notes: 1. Refer to the timing measurement conditions in the PCI r3.0, Figure 7-3. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2. Minimum times are measured at the package ball with the load circuit illustrated in the PCI r3.0, Figure 7-7. Maximum times are measured with the load circuit illustrated in the PCI r3.0, Figure 7-5 and Figure 7-6. 3. PCI_GNT# and PCI_REQ# are point-to-point signals and have different input setup times than bused signals. The setup for PCI_GNT# and PCI_REQ# at 66 MHz is 5 ns. All other signals are bused. 4. Refer to the timing measurement conditions in the PCI r3.0, Figure 7-4. 5. When PCI_M66EN is asserted, CLK is stable when it meets the requirements in the PCI r3.0, Section 7.6.4.1. PCI_RST# is asserted and de-asserted asynchronously with respect to CLK. (Refer to the PCI r3.0, Section 4.3.2, for further details.) 6. Float all output drivers when PCI_RST# is active. (Refer to the PCI r3.0, Section 4.3.2, for further details.) 8. When PCI_M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton can be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when PCI_M66EN is de-asserted. 9. For purposes of Active/Float timing measurements, the Hi-Z or “Off” state is defined as when the total current delivered through the component ball is less than or equal to the leakage current specification. 10. Setup time applies when the PEX 8114 is not driving the ball. Devices cannot concurrently drive and receive signals. (Refer to the PCI r3.0, Section 3.10, item 9, for further details.) ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 335 Electrical Specifications Table 16-10. Symbol PLX Technology, Inc. PCI 66-MHz AC Specifications Parameter Test Conditions Min Typ Max Units Notes Tcyc PCI CLK Cycle Time 15 30 ns Tval CLK to Signal Valid Delay – Bused Signals 2 6 ns 1, 2, 3, 8 Tval(ptp) CLK to Signal Valid Delay – Point-to-Point Signals 2 6 ns 1, 2, 3, 8 Ton Float to Active Delay 2 ns 1, 8, 9 Toff Active to Float Delay ns 1, 9 Tsu Input Setup Time to CLK – Bused Signals 3 ns 3, 4, 10 Tsu(ptp) Input Setup Time to CLK – Point-to-Point Signals 5 ns 3, 4 Th Input Hold Time from CLK 0 ns 4 Trst Reset Active Time after Power Stable 1 ms 5 Trst-clk Reset Active Time after CLK Stable 100 µs 5 Trst-off Reset Active to Output Float Delay ns 5, 6 14 40 Trrsu PCI_REQ64# to PCI_RST# Setup Time 10Tcyc Trrh PCI_RST# to PCI_REQ64# Hold Time 0 Trhfa PCI_RST# High to First Configuration Access 225 clocks Trhff PCI_RST# High to First PCI_FRAME# Assertion 5 clocks Tckskew Clock Skew between Any PCI_CLKO[3:0] Outputs ns 50 ns 130 ps Notes: 1. Refer to the timing measurement conditions in the PCI r3.0, Figure 7-3. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2. Minimum times are measured at the package ball with the load circuit illustrated in the PCI r3.0, Figure 7-7. Maximum times are measured with the load circuit illustrated in the PCI r3.0, Figure 7-5 and Figure 7-6. 3. PCI_GNT# and PCI_REQ# are point-to-point signals and have different input setup times than bused signals. The setup for PCI_GNT# and PCI_REQ# at 66 MHz is 5 ns. All other signals are bused. 4. Refer to the timing measurement conditions in the PCI r3.0, Figure 7-4. 5. When PCI_M66EN is asserted, CLK is stable when it meets the requirements in the PCI r3.0, Section 7.6.4.1. PCI_RST# is asserted and de-asserted asynchronously with respect to CLK. (Refer to the PCI r3.0, Section 4.3.2, for further details.) 6. Float all output drivers when PCI_RST# is active. (Refer to the PCI r3.0, Section 4.3.2, for further details.) 8. When PCI_M66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton can be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when PCI_M66EN is de-asserted. 9. For purposes of Active/Float timing measurements, the Hi-Z or “Off” state is defined as when the total current delivered through the component ball is less than or equal to the leakage current specification. 10. Setup time applies when the PEX 8114 is not driving the ball. Devices cannot concurrently drive and receive signals. (Refer to the PCI r3.0, Section 3.10, item 9, for further details.) 336 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Table 16-11. Symbol SerDes Interface AC Specifications PCI-X 133-MHz AC Specifications Parameter Test Conditions Min Typ Max Units Notes Tcyc PCI CLK Cycle Time 7.5 30 ns Tval CLK to Signal Valid Delay – Bused Signals 0.7 3.8 ns 1, 2, 3, 10, 11 Tval(ptp) CLK to Signal Valid Delay – Point-to-Point Signals 0.7 3.8 ns 1, 2, 3, 10, 11 ns 1, 7, 10, 11 ns 1, 7, 11 Ton Float to Active Delay Toff Active to Float Delay Tsu Input Setup Time to CLK – Bused Signals 1.2 ns 3, 4, 8 Tsu(ptp) Input Setup Time to CLK – Point-to-Point Signals 1.2 ns 3, 4 Th Input Hold Time from CLK 0.5 ns 4 Trst Reset Active Time after Power Stable 1 ms 5 Trst-clk Reset Active Time after CLK Stable 100 µs 5 Trst-off Reset Active to Output Float Delay ns 5, 6 0 7 40 Trrsu PCI_REQ64# to PCI_RST# Setup Time 10 Trrh PCI_RST# to PCI_REQ64# Hold Time 0 Trhfa PCI_RST# High to First Configuration Access 226 clocks Trhff PCI_RST# High to First PCI_FRAME# Assertion 5 clocks Tpvrh Power Valid to PCI_RST# High 100 ms Tprsu PCI-X Initialization Pattern to PCI_RST# Setup Time 10 clocks Tprh PCI_RST# to PCI-X Initialization Pattern Hold Time 0 Trlcx Delay from PCI_RST# Low to CLK Frequency Change 0 Tckskew Clock Skew between Any PCI_CLKO[3:0] Outputs ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved clocks 50 50 ns ns 9 9 ns 130 ps 337 Electrical Specifications PLX Technology, Inc. Notes: 1. Refer to the timing measurement conditions in the PCI-X r1.0b, Figure 9-6. 2. Minimum times are measured at the package ball (not the test point) with the load circuit illustrated in the PCI-X r1.0b, Figure 9-10. Maximum times are measured with the test point and load circuit illustrated in the PCI-X r1.0b, Figure 9-8 and Figure 9-9. 3. Setup time for point-to-point signals applies only to PCI_GNT# and PCI_REQ#. All other signals are bused. 4. Refer to the timing measurement conditions in the PCI-X r1.0b, Figure 9-7. 5. PCI_RST# is asserted and de-asserted asynchronously with respect to CLK. 6. Float All output drivers when PCI_RST# is active. 7. For purposes of Active/Float timing measurements, the Hi-Z or “Off” state is defined as when the total current delivered through the component ball is less than or equal to the leakage current specification. 8. Setup time applies only when the PEX 8114 is not driving the ball. Devices cannot concurrently drive and receive signals. 9. Maximum value is also limited by delay to the first transaction (Trhff). The PCI-X initialization pattern controls signals and PCI_REQ64# after the rising edge of PCI_RST# must be de-asserted no later than two clocks before the first PCI_FRAME# and float no later than one clock before PCI_FRAME# is asserted. 10. A PCI-X device is permitted the minimum values shown for Tval, Tval(ptp), and Ton only in PCI-X mode. In Conventional PCI mode, the device must meet the requirements specified in the PCI r3.0 for the appropriate clock frequency. 11. The PEX 8114 must meet this specification, independent of the amount of outputs switched simultaneously. 338 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Chapter 17 17.1 Thermal Characteristics Table 17-1. 17.2 Thermal and Mechanical Specifications PEX 8114 Package Thermal Resistance Airflow, Θj-c = 4.6 °C/Wa Theta 0 m/s 1 m/s 2 m/s °C/W (Θj-a)b 17.8 15.9 14.8 a. Relevant for packages used with external heat sinks. b. Relevant for packages used without external heat sinks. c. The PEX 8114 does not require a heat sink during standard operating conditions. d. Θj maximum = 125 °C. Package Specifications Table 17-2 defines the PEX 8114 package specifications. Table 17-2. PEX 8114 Package Specifications Parameter Specification Package Type Plastic Ball Grid Array (PBGA) Number of Balls 256 Package Dimensions 17 x 17 mm2 (approximately 1.86 mm high) Ball matrix pattern 16 x 16 Ball pitch 1.00 mm Ball diameter 0.50 ±0.10 mm Ball spacing 0.40 mm Solder mask opening 0.45 ±0.10 mm ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 339 Thermal and Mechanical Specifications 17.3 Mechanical Dimensions Figure 17-1. 340 PLX Technology, Inc. PEX 8114 Mechanical Dimensions ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Appendix A Serial EEPROM Map For serial EEPROM addresses without corresponding register callout (indicated as Reserved), those register locations must be padded with zeros (0000h) when loading the serial EEPROM. The last DWord in each serial EEPROM map is the CRC value. The offset for the CRC is at 03ECh. A.1 Table A-1. Serial EEPROM Map Serial EEPROM Map Register Address Register Name Serial EEPROM Byte Offset 000h Product Identification 0000h 004h PCI Command/Status 0004h, 0378h (refer to Note) 008h Class Code and PCI Revision ID 0008h 00Ch Miscellaneous Control 000Ch 010h Base Address 0 0010h 014h Base Address 1 0014h 018h Bus Number 0018h 01Ch Secondary Status, I/O Limit, and I/O Base 001Ch 020h Memory Base and Limit 0020h 024h Prefetchable Memory Base and Limit 0024h 028h Prefetchable Memory Base Upper 32 Bits 0028h 02Ch Prefetchable Memory Limit Upper 32 Bits 002Ch 030h I/O Base and Limit Upper 16 Bits 0030h 034h New Capability Pointer (no serial EEPROM Write) 0034h 038h Expansion ROM Base Address (Not Supported) 0038h 03Ch Bridge Control and Interrupt Signal 040h Power Management Capability 003Ch, 037Ch (refer to Note) 0040h 044h Power Management Status and Control 0044h, 03B8h, 03BCh, 03C0h, 03C4h (refer to Note) 048h Message Signaled Interrupt Capability 0048h 04Ch MSI Address 004Ch 050h MSI Upper Address 0050h 054h MSI Data 0054h 058h PCI-X Capability, Secondary Status 0058h 05Ch PCI-X Bridge Status 005Ch 060h Upstream Split Transaction Control 0060h 064h Downstream Split Transaction Control 0064h 068h PCI Express Capability List and Capability 0068h 06Ch Device Capability 006Ch, 03A4h (refer to Note) 070h Device Status and Control 0070h, 03A8h (refer to Note) 0074h 074h Link Capability 078h Link Status and Control 07Ch Slot Capability (Reverse Transparent Bridge Mode Only) 007Ch 080h Slot Status and Control (Reverse Transparent Bridge Mode Only) 0080h 084h - 0FCh 0078h, 03ACh (refer to Note) Register Addresses Skipped ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 341 Serial EEPROM Map Table A-1. PLX Technology, Inc. Serial EEPROM Map (Cont.) Register Address Serial EEPROM Byte Offset 100h Device Serial Number Extended Capability 104h Serial Number (Lower DW) 0088h 108h Serial Number (Higher DW) 008Ch 10Ch Reserved 0090h 110h Reserved 0094h 114h Reserved 0098h 118h Reserved 009Ch 11Ch Reserved 00A0h 120h Reserved 00A4h 124h Reserved 00A8h 128h Reserved 00ACh 12Ch Reserved 00B0h 130h Reserved 00B4h 134h Reserved 00B8h 138h Power Budget Extended Capability 00BCh 13Ch Data Select 0084h 00C0h, 03CCh, 03D0h, 03D4h, 03D8h, 03DCh, 03E0h, 03E4h, 03E8h (refer to Note) 140h Power Budget Data 00C4h 144h Power Budget Capability 00C8h 148h Virtual Channel Extended Capability 00CCh 14Ch Port VC Capability 1 00D0h 150h Port VC Capability 2 (Not Supported) 154h Port VC Status and Control (Not Supported) 00D4h 00D8h, 03C8h (refer to Note) 158h VC0 Resource Capability (Not Supported) 00DCh 15Ch VC0 Resource Control 00E0h VC0 Resource Status 00E4h 160h 164h - 1C4h 342 Register Name Register Addresses Skipped 1C8h ECC Check Disable 00E8h 1CCh Device-Specific Error 32-Bit Error Status (Factory Test Only) 00ECh 1D0h Device-Specific Error 32-Bit Error Mask (Factory Test Only) 00F0h 1D4h Reserved 00F4h 1D8h Reserved 00F8h 1DCh Reserved 00FCh 1E0h Power Management Hot Plug User Configuration 0100h 1E4h Egress Control and Status 0104h 1E8h Bad TLP Count 0108h 1ECh Bad DLLP Count 010Ch 1F0h TLP Payload Length Count 0110h 1F4h Reserved 0114h 1F8h ACK Transmission Latency Limit 0118h 1FCh Reserved 011Ch 200h Reserved 0120h 204h Reserved 0124h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Table A-1. Serial EEPROM Map (Cont.) Register Address 208h Serial EEPROM Map Register Name Serial EEPROM Byte Offset Reserved 0128h 20Ch Reserved 012Ch 210h Phy User Test Pattern 0 0130h 214h Phy User Test Pattern 1 0134h 218h Phy User Test Pattern 2 0138h 21Ch Phy User Test Pattern 3 013Ch 220h Physical Layer Command and Status 0140h 224h Port Configuration 0144h 228h Physical Layer Test 0148h 22Ch Factory Test Only 014Ch 230h Physical Layer Port Command 0150h 234h SKIP Ordered-Set Interval 0154h 238h SerDes[0-3] Quad Diagnostics Data 0158h 23Ch Reserved 015Ch 240h Reserved 0160h 244h Reserved 0164h 248h SerDes Nominal Drive Current Select 0168h 24Ch SerDes Drive Current Level 1 016Ch 250h Reserved 0170h SerDes Drive Equalization Level Select 1 0174h 254h 258h - 25Ch 260h 264h - 2E4h Register Addresses Skipped 0178h Serial EEPROM Status and Control Register Addresses Skipped 017Ch, 0388h (refer to Note) 2E8h Bus Number CAM 8 2ECh Reserved 0180h 2F0h Reserved 0184h 2F4h Reserved 0188h 2F8h Reserved 018Ch 2FCh Reserved 0190h 300h Reserved 0194h 304h Reserved 0198h 308h Reserved 019Ch 30Ch Reserved 01A0h 310h Reserved 01A4h 314h Reserved 01A8h 318h 31Ch - 3C4h I/O CAM_8 01ACh, 038Ch (refer to Note) Register Addresses Skipped 3C8h AMCAM_8 Memory Limit and Base 01B0h, 0390h (refer to Note) 3CCh AMCAM_8 Prefetchable Memory Limit and Base[31:0] 01B4h, 0394h (refer to Note) 3D0h AMCAM_8 Prefetchable Memory Base[63:32] 01B8h, 0398h (refer to Note) 3D4h AMCAM_8 Prefetchable Memory Limit[63:32] 01BCh, 039Ch (refer to Note) 3D8h - 544h 548h Register Addresses Skipped Reserved ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 01C0h 343 Serial EEPROM Map Table A-1. Serial EEPROM Map (Cont.) Register Address 54Ch - 65Ch 344 PLX Technology, Inc. Register Name Serial EEPROM Byte Offset Register Addresses Skipped 660h TIC Control 01C4h 664h Reserved 01C8h 668h TIC Port Enable (Factory Test Only) 01CCh 66Ch Reserved 01D0h 670h Reserved 01D4h 674h Reserved 01D8h 678h Reserved 01DCh 67Ch Reserved 01E0h 680h Reserved 01E4h 684h Reserved 01E8h 688h Reserved 01ECh 68Ch Reserved 01F0h 690h Reserved 01F4h 694h Reserved 01F8h 698h Reserved 01FCh 69Ch Reserved 0200h 6A0h I/OCAM_8 Base and Limit Upper 16 Bits 6A4h Reserved 0208h 0204h, 03A0h (refer to Note) 6A8h Reserved 020Ch 6ACh Reserved 0210h 6B0h Reserved 0214h 6B4h Reserved 0218h 6B8h Reserved 021Ch 6BCh Reserved 0220h 6C0h Reserved 0224h 6C4h Reserved 0228h 6C8h Reserved 022Ch 6CCh Reserved 0230h 6D0h Reserved 0234h 6D4h Reserved 0238h 6D8h Reserved 023Ch 6DCh Reserved 0240h 6E0h Reserved 0244h 6E4h Reserved 0248h 6E8h Reserved 024Ch 6ECh Reserved 0250h 6F0h Reserved 0254h 6F4h Reserved 0258h 6F8h Reserved 025Ch 6FCh Reserved 0260h 700h BAR0_8 0264h, 0380h (refer to Note) 704h BAR1_8 0268h, 0384h (refer to Note) ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved September, 2010 Table A-1. Serial EEPROM Map (Cont.) Register Address 708h - 9F0h Serial EEPROM Map Register Name Serial EEPROM Byte Offset Register Addresses Skipped 9F4h INCH FC Update Pending Timer 026Ch 9F8h Reserved 0270h 9FCh INCH Mode 0274h A00h INCH Threshold VC0 Posted 0278h A04h INCH Threshold VC0 Non-Posted 027Ch A08h INCH Threshold VC0 Completion 0280h, 03B0h (refer to Note) A0Ch - B7Ch Register Addresses Skipped 0284h B80h Reserved B84h Reserved 0288h B88h Reserved 028Ch B8Ch Reserved 0290h B90h Reserved 0294h B94h Reserved 0298h B98h Reserved 029Ch Reserved 02A0h B9Ch BA0h - BE8h Register Addresses Skipped BECh Reserved 02A4h BF0h Reserved 02A8h BF4h Reserved 02ACh BF8h Reserved 02B0h BFCh Reserved 02B4h C00h PCI Express Interface ITCH VC&T Threshold_1 02B8h C04h PCI Express Interface ITCH VC&T Threshold_2 02BCh C08h Reserved 02C0h C0Ch Reserved 02C4h C10h Reserved 02C8h C14h - F50h Register Addresses Skipped F54h Reserved 02CCh F58h Reserved 02D0h F5Ch Reserved 02D4h F60h Reserved 02D8h F64h Reserved 02DCh F68h Reserved 02E0h F6Ch Reserved 02E4h F70h PCI-X Interface ITCH VC&T Threshold_1 02E8h F74h PCI-X Interface ITCH VC&T Threshold_2 02ECh F78h Reserved 02F0h F7Ch Reserved 02F4h F80h PCI-X Interface Device-Specific Error 32-Bit Error Status (Factory Test Only) 02F8h F84h PCI-X Interface Device-Specific Error 32-Bit Error Mask (Factory Test Only) 02FCh F8Ch PCI-X Interface Completion Buffer Timeout 0300h ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved 345 Serial EEPROM Map Table A-1. PLX Technology, Inc. Serial EEPROM Map (Cont.) Register Address Register Name Serial EEPROM Byte Offset F8Ch Root Control 0304h F90h Root Status (no serial EEPROM Write) 0308h F94h Root Error Command 030Ch F98C Root Error Status 0310h F9Ch Error Identification (no serial EEPROM Write) 0314h FA0h PCI Clock Enable, Strong Ordering, Read Cycle Value 0318h FA4h Prefetch 031Ch FA8h Arbiter 0 0320h FACh Arbiter 1 0324h FB0h Arbiter 2 0328h FB4h Advanced Error Reporting Enhanced Capability Header 032Ch FB8h Uncorrectable Error Status 0330h FBCh Uncorrectable Error Mask 0334h FC0h Uncorrectable Error Severity 0338h FC4h Correctable Error Status 033Ch 0340h FC8h Correctable Error Mask FCCh Advanced Error Capabilities and Control FD0h Header Log_0 0348h FD4h Header Log_1 034Ch 0344h, 03B4h (refer to Note) FD8h Header Log_2 0350h FDCh Header Log_3 0354h FE0h Secondary Uncorrectable Error Status 0358h FE4h Secondary Uncorrectable Error Mask 035Ch FE8h Secondary Uncorrectable Error Severity 0360h FECh Secondary Uncorrectable Error Pointer (no serial EEPROM Write) 0364h FF0h 0368h FF4h 036Ch FF8h Secondary Header Log (no serial EEPROM Write) NA 0370h 0374h FFCh Location of Serial EEPROM Check Sum 03ECh Note: Multiple Writes to the register are required to trigger the state machine, indicating that the serial EEPROM is downloaded and to proceed to the next step in the sequence of events. 346 ExpressLane PEX 8114-BC/BD PCI Express-to-PCI/PCI-X Bridge Data Book, Version 3.2 Copyright © 2010 by PLX Technology, Inc. All Rights Reserved Appendix B Sample C Code Implementation of CRC Generator const unsigned long LCRCpoly = 0xDB710641; ///////////////////////////////////////////////////////////////// // Function name : fCalcLCRC // Description : // Return type : unsigned long // // Argument : unsigned long lfsr // Argument : unsigned long plain // unsigned long fCalcLCRC( unsigned long lfsr, unsigned long plain ) { int j; for( j=0; j