VMMK-3803-TR2G

VMMK-3803 3 - 11 GHz UWB Low Noise Amplifier in SMT Package Data Sheet Description Features The VMMK-3803 is a small and easy-to-use, broadband, low noise amplifier operating in various frequency bands from 3 to 11 GHz with typical noise figure of 1.5 dB. It is housed in the Avago Technologies’ industry-leading and revolutionary sub-miniature chip scale package (GaAsCap wafer scale leadless package) which is small and ultra thin yet can be handled and placed with standard 0402 pick and place assembly equipment. The VMMK-3803 provides a typical gain of 20 dB with good linearity of 0.9 dBm typical IIP3 and input and output return losses and can be operated from 3 to 5 V power supply. It is fabricated using Avago Technologies unique 0.25 μm E-mode PHEMT technology which eliminates the need for negative gate biasing voltage. • 1 x 0.5 mm surface mount package • Ultrathin (0.25 mm) • Wide frequency range • Self-Biasing: 3 to 5 V • In and output match: 50 ohm Specifications (6 GHz, Vdd = 3 V, Vpd = 3 V, Zin = Zout = 50 Ω) • Low noise figure: 1.5 dB typ. • Small signal gain: 20 dB typ. • Output Power at 1dB compression = 7 dBm Applications WLP0402, 1 mm x 0.5 mm x 0.25 mm • 3.1-10.6 GHz UWB LNA • 3.5 and 5-6 GHz WLAN and WiMax OY • 10.5 GHz PMP • 802.16 & 802.20 BWA systems • Radar and ECM systems • Generic IF amplifier Pin Connections (Top View) Input Input Note: “O” = Device Code “Y” = Month Code OY Amp Output/Vdd Output/Vdd Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 60 V ESD Human Body Model = 200 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. Electrical Specifications Table 1. Absolute Maximum Rating [1] Symbol Parameters/Condition Unit Absolute Max Vdd Supply Voltage (RF Output) V 7 Vpd Power Down Voltage V 7 Supply Current mA 45 Idd [2] Pin, max [3] CW RF Input Power (RF Input) dBm 15 Pdiss Total Power Dissipation mW 315 Tch Max Channel Temperature °C +150 θjc [4] Thermal Resistance °C/W 90.6 Notes 1. Operation of this device above any one of these parameters may cause permanent damage 2. Bias is assumed DC quiescent conditions 3. With the DC (typical bias) and RF applied to the device at board temperature Tb = 25° C 4. Thermal resistance is measured from junction to board using IR method Table 2. DC and RF Specifications [1] TA = 25° C, Zin = Zout = 50 Ω, Freq = 6 GHz, Vdd = 3 V, Vpd = 3 V (unless otherwise specified) Symbol Parameters/Condition Unit Minimum Typical Maximum Idd [2] Supply Current mA 14 20 26 Idd_Off [2] Leakage Current (Vpd = 0 V) mA Ga [2,3] Gain dB NF [2,3] Noise Figure S11 [4] Input Return Loss S22 [4] IIP3 [4,5] P-1dB [4] 0.1 17 20 23 dB 1.5 1.9 dB 15 Output Return Loss dB 9 Input 3rd Order Intercept Point dBm 0.9 Output Power at 1dB Compression dBm 7 Notes 1. Losses of the test system have been de-embedded from final data 2. Measured data obtained from wafer-probing using a G-S, S-G pyramid probe 3. Ga and NF obtained from Noise Figure Analyzer 4. S-parameters, P1dB, and IIP3 data obtained using 300 mm G-S-G probing on PCB substrate 5. IIP3 test condition: Center frequency = 6 GHz, 2 tone offset = 10 MHz, Pin = -20 dBm 2 Product Consistency Distribution Charts at 6.0 GHz, Vdd = 3 V, Vpd = 3 V unless specified. Measured data obtained from wafer-probing using a G-S, S-G pyramid probe. LSL 0.011 0.015 USL 0.018 0.021 0.024 LSL 0.027 0.03 Idd @ Vdd = 3 V, Vpd = 3 V, Mean = 20 mA, LSL = 14 mA, USL = 26 mA 17 18 USL 19 20 21 22 23 24 Ga @ 6 GHz, Mean = 20 dB, LSL = 17 dB, USL = 23 dB (Data obtained using Noise Figure Analyzer) USL Notes: Distribution data based on 48 Kpcs part sample size from MPV lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 1 1.1 1.2 1.4 1.6 NF @ 6 GHz, Mean = 1.5 dB, USL = 1.9 dB 3 1.8 2 2.1 VMMK-3803 Typical Performance TA = 25° C, Vpd = 3 V, Zin = Zout = 50 Ω (unless noted); data obtained using 300 mm G-S-G probing on PCB substrate & broadband bias tees, losses calibrated out to the package reference plane.plane. -20 24 -30 S12 (dB) S21 (dB) 16 12 8 3V 4V 5V 6V 4 0 0 3 6 9 12 Frequency (GHz) 15 -60 18 0 0 -5 -5 -15 3V 4V 5V 6V -25 3 6 9 12 Frequency (GHz) 15 18 0 3 6 9 12 Frequency (GHz) 15 15 18 -15 -20 -30 -35 18 2 2 NFmin (dB) 2.5 1.5 1 6 8 Frequency (GHz) Figure 5. Noise Figure (50 ohm) over Vdd 3 6 9 12 Frequency (GHz) 10 1.5 1 3V 4V 5V 4 0 Figure 4. Output Return Loss over Vdd 2.5 2 3V 4V 5V 6V -25 Figure 3. Input Return Loss over Vdd 0.5 0 -10 S22 (dB) S11 (dB) -45 Figure 2. Reverse Isolation over Vdd -20 NF (dB) -40 -55 -10 4 -35 -50 Figure 1. Small Signal Gain over Vdd -30 3V 4V 5V 6V -25 20 12 0.5 3V 4V 5V 2 4 Figure 6. NFmin over Vdd 6 8 Frequency (GHz) 10 12 VMMK-3803 Typical Performance Zin = Zout = 50 Ω, Vpd = 3 V, TA = 25° C for varying Vdd data, Vdd=3V for varying Temp data; obtained using 300 mm G-S-G PCB substrate & broadband bias tees, losses calibrated out to the package reference plane. 12 8 6 4 8 IIP3 (dBm) P1dB (dBm) 10 6 4 0 2 4 6 8 Frequency (GHz) 10 2 4 6 8 Frequency (GHz) 10 12 3 2.5 2 15 NF (dB) S21 (dB) -8 12 25° C -40° C +85° C 20 10 1.5 1 5 25° C at 3 V -35° C at 3 V +85° C at 3 V 0.5 0 0 2 4 6 8 10 12 Frequency (GHz) 14 16 18 0 20 Figure 9. S21 over Temp 2 3 4 5 6 7 8 Frequency (GHz) 9 10 11 12 Figure 10. Noise Figure over Temp 12 8 6 10 4 8 IIP3 (dBm) P1dB (dBm) 3V 4V 5V Figure 8. Input IP3 over Vdd 25 6 4 2 4 6 8 Frequency (GHz) Figure 11. Output P1dB over Temp 10 2 0 -2 -4 25° C -40° C 85° C 2 5 -2 -6 Figure 7. Output P1dB over Vdd 0 0 -4 3V 4V 5V 2 2 25° C -40° C 85° C -6 12 -8 2 4 Figure 12. Input IP3 over Temp 6 8 Frequency (GHz) 10 12 Typical Scattering Parameters and Noise Parameters TA = 25° C, Vdd = 3 V, Vpd = 3 V, Zin = Zout = 50 Ω; data obtained using 300 mm G-S-G probing on PCB substrate & broadband bias tees, losses calibrated out to the package reference plane. Freq (GHz) S11 (dB) (mag) 0.5 1 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 12 13 14 15 16 17 18 -1.071 -1.068 -1.151 -2.194 -3.833 -5.869 -8.099 -10.46 -12.98 -15.61 -18.59 -21.86 -24.5 -25.11 -25.75 -22.45 -20.23 -18.22 -16 -13.79 -11.97 -8.92 -6.614 -5.764 -5.333 -5.106 -5.002 -5.002 0.884 0.8843 0.8759 0.7768 0.6432 0.5088 0.3936 0.3 0.2243 0.1658 0.1176 0.0807 0.0596 0.0555 0.0516 0.0754 0.0974 0.1228 0.1584 0.2043 0.2521 0.3581 0.467 0.515 0.5412 0.5555 0.5622 0.5622 (ang) S21 (dB) (mag) -17.999 -28.599 -64.841 -82.84 -100.89 -116.6 -129.96 -141.47 -150.4 -160.11 -166.04 -167.23 -160.39 -149.66 -142.86 -140.76 -152.95 -169.1 174.25 156.38 137.68 100.89 65.61 38.532 17.245 -0.6043 -15.312 -28.024 15.88 16.228 19.703 20.424 20.494 20.166 19.68 19.205 18.755 18.399 18.111 17.923 17.775 17.709 17.606 17.709 17.786 17.843 17.902 17.934 17.788 17.121 15.39 13.256 10.905 8.5552 6.3253 4.239 6.2228 6.4776 9.6641 10.5006 10.5852 10.1931 9.6383 9.1254 8.6649 8.317 8.0454 7.8735 7.7401 7.6816 7.5906 7.6817 7.7502 7.8006 7.8542 7.8828 7.7516 7.179 5.8818 4.6006 3.5095 2.6777 2.0714 1.6291 (ang) S12 (dB) (mag) 91.657 54.832 -0.2142 -26.683 -50.965 -72.011 -90.299 -106.48 -121.1 -135.11 -148.18 -160.97 -173.68 173.48 160.8 147.9 134.22 120.1 105.21 89.54 73.292 38.405 3.9724 -25.269 -50.943 -73.397 -93.815 -112.86 -39.83 -40.72 -61.94 -44.73 -39.49 -36.71 -35.19 -34.11 -33.43 -32.69 -32.22 -31.67 -31.24 -30.84 -30.75 -29.95 -29.58 -29.34 -29.24 -29.12 -29.37 -30.31 -32.58 -36.42 -40.09 -45.04 -43.88 -41.31 0.0102 0.0092 0.0008 0.0058 0.0106 0.0146 0.0174 0.0197 0.0213 0.0232 0.0245 0.0261 0.0274 0.0287 0.029 0.0318 0.0332 0.0341 0.0345 0.035 0.034 0.0305 0.0235 0.0151 0.0099 0.0056 0.0064 0.0086 (ang) S22 (dB) (mag) (ang) 25.085 -5.7032 26.203 94.308 80.488 67.726 57.244 48.809 41.646 37.431 31.778 26.223 20.235 14.279 11.758 3.8768 -3.334 -11.824 -20.194 -29.569 -40.032 -63.682 -89.863 -115.26 -141.77 163.4 123.41 86.597 -5.979 -7.5392 -6.6846 -6.9512 -7.8145 -8.6172 -9.1311 -9.35 -9.231 -9.231 -9.0199 -8.7328 -8.4272 -8.1787 -8.1809 -7.6181 -7.3711 -7.1844 -6.9803 -6.8455 -6.9454 -7.4568 -9.1485 -11.258 -13.159 -14.462 -14.699 -14.485 0.5024 0.4198 0.4632 0.4492 0.4067 0.3708 0.3495 0.3408 0.3455 0.3455 0.354 0.3659 0.379 0.39 0.3899 0.416 0.428 0.4373 0.4477 0.4547 0.4495 0.4238 0.3488 0.2736 0.2198 0.1892 0.1841 0.1887 -32.091 -21.41 -30.788 -42.359 -50.364 -54.537 -57.475 -60.009 -62.991 -67.759 -72.539 -78.294 -85.286 -93.407 -100.46 -109.34 -119.64 -130.1 -141.68 -154.5 -167.89 162.538 127.677 97.5178 70.0208 42.6539 17.9161 -3.435 Freq (GHz) Fmin (dB) Rn Γopt (mag) Γopt (ang) Associated gain (dB) 2 0.93 0.279 0.504 35.48 23.81 2.5 1.02 0.241 0.440 41.07 22.90 3 0.98 0.168 0.574 33.56 20.48 4 1.06 0.169 0.378 54.74 20.17 5 1.33 0.152 0.304 80.24 19.46 5.5 1.36 0.156 0.306 86.48 19.07 6 1.45 0.142 0.234 88.16 18.92 7 1.52 0.120 0.141 126.58 18.80 8 1.69 0.120 0.143 126.9 18.88 9 1.77 0.117 0.108 152.56 19.22 10 1.93 0.122 0.111 -161.83 19.38 10.5 1.94 0.162 0.113 -141.3 19.50 11 1.91 0.142 0.113 -151.1 19.17 12 2.06 0.220 0.082 -61.09 18.16 13 2.4 0.260 0.165 -58.95 16.77 6 VMMK-3803 Applications Information Biasing and Operation Table 3. VMMK-3803 Demo Board BOM The VMMK-3803 is biased with a positive supply connected to the output pin Vd through an external user supplied bias decoupling network. Typical bias is 3 V at 20 mA. The “on” state also requires that the input port of the VMMK-3803 also be biased at 3 V for normal gain operation. 0V on the input puts the VMMK-3803 in the “off” state. Component Value DUT VMMK-3803 C1 100 pF C2 100 pF R1 10 kohm An example of simple user supplied bias tees is shown in Figure 13. The output bias decoupling network feeding Vdd consists of a shunt 6.8 nH inductor. At the input, a 10 Kohm resistor is needed to feed the power-down control voltage. The input and output dc blocking capacitors are each 100 pF. The “on” and “off” S Parameters shown in the preceding tables reflect the operation of the circuit shown in Figure 14. C5 0.1 mF C6 100 pF L1 6.8 nH Figure 13. Demo Board (available to qualified customers upon request) Vpd 0.1 µF Vdd 0.1 µF 100 pF 10 K 6.8 nH Output Input Amp 100 pF Input Pad 50 Ohm line Ground Pad Output Pad 100 pF The input and output bias decoupling network can be easily constructed using small surface mount components. The value of the shunt inductors can have a major effect on both low and high frequency operation. The demo board uses small value inductors that have self resonant frequencies higher than the maximum desired frequency of operation. If the self-resonant frequency of the inductor is too close to the operating band, the value of the inductor will need to be adjusted so that the selfresonant frequency is significantly higher than the highest frequency of operation. Typically a passive component company like Murata does not specify S parameters at frequencies higher than 5 or 6 GHz for larger values of inductance making it difficult to properly simulate amplifier performance at higher frequencies. It has been observed that the Murata LQW15AN series of 0402 inductors actually works quite well above their normally specified frequency. The parallel combination of the 100 pF and 0.1 mF bypass capacitors provide a low impedance in the band of operation and at lower frequencies and should be placed as close as possible to the inductor. The low frequency bypass provides good rejection of power supply noise and also provides a low impedance termination for third order low frequency mixing products that will be generated when multiple in-band signals are injected into any amplifier. 50 Ohm line Figure 14. Example demonstration circuit of VMMK-3803 for broadband operation (3GHz to 11GHz). A layout of a typical demo board is shown in Figure 15. Figure 15. Biasing the VMMK-3803 7 S Parameter Measurements ESD Precautions The S-parameters are measured on a 0.016 inch thick RO4003 printed circuit test board, using G-S-G (ground signal ground) probes. Coplanar waveguide is used to provide a smooth transition form the probes to the device under test. The presence of the ground plane on top of the test board results in excellent grounding at the device under test. A combination of SOLT (Short – Open – Load – Thru) and TRL (Thru – Reflect – Line) calibration techniques are used to correct for the effects of the test board, resulting in accurate device S parameters. Note: These devices are ESD sensitive. The following precautions are strongly recommended. Ensure that an ESD approved carrier is used when die are transported from one destination to another. Personal grounding is to be worn at all times when handling these devices. For more detail, refer to Avago application note A004R: Electro-static Discharge Damage and Control. Package and Assembly Note Part Number Devices Per Container Container For detailed description of the device package, handling and assembly, refer to Application Note 5378. VMMK-3803-BLKG 100 Antistatic Bag VMMK-3803-TR1G 5000 7” Reel 8 Ordering Information fy the device rial with one tal. Soldering ion than FR5 materials with e of the base vice circuitry aAs package to damaging RO4003 and al and should g source leads leads of the unt. The recern is shown ned footprint t borders the en. re any plated ng and tests in .003”) and re 5 provides VMMK-3XXX ness RO4350 e also applies t frequencies 1XXX FETs at uctance may ay be placed bility. Consult ation. of the VMMK that the VIAs om under the of the VIAs is e VIAs should Outline Drawing 1.004 MIN, 1.085 MAX PIN ONE INDICATOR 0.125 0.125 GROUND PAD 0.500 MIN, 0.585 MAX 0.470 OUTPUT PAD 0.390 0.160 INPUT PAD 0.160 Notes: Solderable area of the device shown in yellow. Dimensions in mm. Tolerance ± 0.015mm Recommended SMT Attachment Suggested PCB Material and Land Pattern The VMMK Packaged Devices are compatible with high volume surface mount PCB assembly processes. 1.2 (0.048) 0.400 (0.016) 0.100 (0.004) 0.076 max (0.003) 2pl see discussion 0.381 (0.015) 2pl 1. Follow ESD precautions while handling packages. 0.100 (0.004) 0.500 (0.020) Part of Input Circuit Manual Assembly for Prototypes 2. Handling should be along the edges with tweezers or from topside if using a vacuum collet. 0.500 (0.020) 0.200 (0.008) Part of Output Circuit 0.200 (0.008) 0.7 (0.028) 0.254 dia PTH (0.010) 4pl Solder Mask 0.400 dia (0.016) 4pl Figure 5. Recommended PCB layout for VMMK devices Notes: 1. 0.010” Rogers RO4350 As a general rule, if a VIA is within .004” (100u) of the edge of the soldermask but not under the device, then the VIA should be filled. Any VIA which is covered by the solder mask and is beyond .004” (100u) of the solder mask edge can be uncapped and unfilled as it is not at risk of wicking away solder from the device. If for any reason it is required to include a VIA or VIAs under a VMMK device, then the VIAs should be filled and capped. A capped VIA is a “plated over” filled VIA. If a filled but uncapped VIA is placed under the device, there will not be enough solderable surface area for device attachment. If an unfilled and uncapped VIA is placed directly under the ground pad, then the liquid solder will flow into the open VIA hole during the reflow process and deplete the solder volume to varying degrees from under the ground pad. Depletion of the solder volume 9 due to unfilled VIAs may lead to a weak solder joint, poor grounding of the device, and/or stresses compromising the structural integrity of the package. 3. Recommended attachment is solder paste. Please see recommended solder reflow profile. Conductive epoxy is not recommended. Hand soldering is not recommended. 4. Apply solder paste using either a stencil printer or dot placement. The volume of solder paste will be dependent on PCB and component layout and should be controlled to ensure consistent mechanical and electrical performance. Excessive solder will degrade RF performance. 5. Follow solder paste and vendor’s recommendations when developing a solder reflow profile. A standard profile will have a steady ramp up from room temperature to the pre-heat temp to avoid damage due to thermal shock. 6. Packages have been qualified to withstand a peak temperature of 260°C for 20 to 40 sec. Verify that the profile will not expose device beyond these limits. 7. Clean off flux per vendor’s recommendations. 8. Clean the module with Acetone. Rinse with alcohol. Allow the module to dry before testing. Package Dimension Outline D E A Dimensions Symbol Min (mm) Max (mm) E 0.500 0.585 D 1.004 1.085 A 0.225 0.275 Note: All dimensions are in mm Reel Orientation Device Orientation REEL USER FEED DIRECTION 4 mm Notes: “O” = Device Code “Y” = Month Code • OY TOP VIEW CARRIER TAPE • OY 10 • OY • OY USER FEED DIRECTION 8 mm END VIEW Tape Dimensions T Do Note: 1 Po B A A P1 Scale 5:1 Bo W Note: 2 F E 5° (Max) B D1 Ao R0.1 5° (Max) Scale 5:1 A–A SECTION Symbol Spec. Ao Bo Ko 0.73 ± 0.05 1.26 ± 0.05 0.35 + 0.05 - 0 – 4.0 ± 0.10 4.0 ± 0.10 2.0 ± 0.05 1.55 ± 0.05 0.5 ± 0.05 1.75 ± 0.10 3.50 ± 0.05 40.0 ± 0.10 8.0 ± 0.20 0.20 ± 0.02 K1 Po P1 P2 Do D1 E F Po W T Unit: mm Notes: 1. 10 Sprocket hole pitch cumulative tolerance is ±0.1 mm. 2. Pocket position relative to sprocket hole measured as true position of pocket not pocket hole. 3. Ao & Bo measured on a place 0.3 mm above the bottom of the pocket to top surface of the carrier. 4. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 5. Carrier camber shall be not than 1 m per 100 mm through a length of 250 mm. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. AV02-2920EN - February 10, 2014 Ko B–B SECTION Note: 2 P2