AZ100LVEL16VR

ARIZONA MICROTEK, INC. AZ100LVEL16VR ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable FEATURES • • • • • • • • Green and RoHS Compliant / Lead (Pb) Free Packages Available Enhanced Enable Operation High Bandwidth for ≥1GHz Similar Operation as AZ100EL16VO Minimizes External Components Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Available in a MLP 16 or MLP 8 Package S–Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website PACKAGE MLP 16 (3x3) MLP 16 (3x3) RoHS Compliant / Lead (Pb) Free MLP 8 (2x2) Green / RoHS Compliant / Lead (Pb) Free DIE 1 2 3 PACKAGE AVAILABILITY PART NO. AZ100LVEL16VRL AZ100LVEL16VRL+ AZ100LVEL16VRNEG AZ100LVEL16VRX MARKING AZM 16R AZM+ 16R R5G N/A NOTES 1,2 1,2 1,2 3 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “Y” for year followed by “WW” for week. Waffle Pack DESCRIPTION The AZ100LVEL16VR is a specialized oscillator gain stage with high gain output buffer including an enable function. The QHG/QHG outputs have voltage gain several times greater than the Q/Q outputs. ¯ ¯ MLP 16, 3x3 mm Package (VRL) or DIE (VRX) The AZ100LVEL16VR provides a selectable QHG/QHG enable that allows continuous oscillator operation via ¯ the Q/Q outputs. The enable truth table on the next page shows the operating modes. Leaving EN-SEL open (NC) ¯ selects PECL/ECL operation for the EN pad/pin. In this mode the QHG/QHG outputs are enabled when EN is left ¯ open (NC) or set to a PECL/ECL low. Connecting EN-SEL to VCC, VEE or VBB selects CMOS operation for the EN pad/pin. When EN-SEL is tied to VEE, the QHG/QHG outputs are disabled when EN is left open (NC). When EN-SEL is tied to VCC or VBB, the QHG/Q ¯ ¯ 1 HG outputs are enabled when EN is left open. This default logic condition can be overridden by a ≤20kΩ resistor connected to the opposite supply. The AZ100LVEL16VR also provides a VBB and 470Ω internal bias resistors from D to VBB and D to VBB. The ¯ VBB pin supports 1.5mA sink/source current. VBB should be bypassed to ground or VCC with a 0.01 μF capacitor. Outputs Q/Q each have a selectable on-chip pull-down current source. See the current source truth table on the ¯ next page for the supported values. External resistors may also be used to increase pull-down current to a maximum total of 25mA for the Q/Q outputs. ¯ Each of the QHG/QHG outputs has an optional on-chip pull-down current source of 10 mA. When pad/pin VEEP is ¯ left open (NC), the output current sources are disabled and the QHG /QHG operate as standard PECL/ECL. When VEEP ¯ is connected to VEE, the current sources are activated. The QHG /QHG pull-down current can be decreased by using a ¯ resistor between VEEP and VEE. 1 This operational mode (EN-SEL to VCC or VBB) is not supported for date codes prior to 0428 (July 2004). EN-SEL to VEE is supported for all date codes. 1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541 www.azmicrotek.com AZ100LVEL16VR MLP 16 (VRL) AND DIE (VRX) AZ100LVEL16VRL MLP 16 Q Q D D 470 4mA EA. Q CS-SEL QHG QHG 10mA EA. Q 15 NC 14 VCC 13 12 CS-SEL 16 NC D D 1 2 3 4 5 EN VBB Leave Pad Open or Connect to VEE 11 10 9 QHG QHG EN-SEL EN CMOS / TTL THRESHOLD VEEP VEE EN-SEL VBB 6 NC 7 VEE 8 VEEP AZ100LVEL16VRL, VRX TOP VIEW ENABLE TRUTH TABLE EN-SEL EN Q/Q QHG QHG ¯ ¯ NC PECL Low, VEE or NC Data Data Data NC PECL High or VCC Data Low High VEE1 Data Low High CMOS Low, VEE or NC VEE1 CMOS High or VCC Data Data Data VCC or VBB1,2 CMOS Low or VEE Data Low High VCC or VBB 1,2 CMOS High, VCC or NC Data Data Data 1 EN-SEL connections must be ≤1Ω. 2 Date codes prior to 0428 do not support this operating mode. PIN DESCRIPTION PIN CURRENT SOURCE TRUTH TABLE CS-SEL Q Q ¯ NC 4mA typ. 4mA typ. VEE1 8mA typ. 8mA typ. VCC1 0 4mA typ. 1 Connections to VCC or VEE must be ≤1Ω. D/D ¯ Q/Q ¯ QHG/QHG ¯ VBB EN-SEL EN CS-SEL VEEP VEE VCC FUNCTION Data Inputs Data Outputs Data Outputs w/High Gain Reference Voltage Output Enable Logic Select Enable Input Selects Q and Q Current Source ¯ Magnitude Optional QHG and QHG Current ¯ Sources Negative Supply Positive Supply April 2007 * REV - 15 www.azmicrotek.com 2 AZ100LVEL16VR MLP 16 (VRL) AND DIE (VRX) D EN (EN-SEL NC) EN (EN-SEL CONNECTED TO VEE or V CC) (PECL) (CMOS) Q Q QHG QHG TIMING DIAGRAM DIE PAD COORDINATES EL16VR A B C D Notes: M L K J NAME A B C D E F G H I J K L M SIGNAL D D ¯ VBB EN VEE VEEP EN-SEL QHG ¯ QHG CS-SEL VCC Q Q ¯ DIE SIZE: 950u X 940u DIE THICKNESS: 14 MILS BOND PAD: 85u X 85u I H G E F X (Microns) -342.5 -342.5 -342.5 -342.5 -33.5 126.5 312.5 312.5 312.5 312.5 302.5 142.5 -140.5 Y (Microns) 312.5 144.5 -87.0 -255.0 -312.5 -312.5 -248.5 -98.5 51.5 201.5 342.5 342.5 342.5 1. Other die thicknesses available. Contact factory for further information. 2. The die backside may be left open or connected to VEE. April 2007 * REV - 15 www.azmicrotek.com 3 AZ100LVEL16VR MLP 8, 2x2 mm Package (VRNE) A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open (NC), the Q and QHG/QHG outputs follow the data input. When EN is LOW, the QHG output is forced high and the Q ¯ ¯ ¯ ¯ ¯ HG output is forced low while Q continues to follow the data input. The Q output has an internal 4 mA current source to VEE, in most cases eliminating the need for an external pull-down resistor. ¯ The data input D is tied to the VBB pin through a 470 Ω internal bias resistor while the inverting input D is connected directly to VBB. Bypassing VBB to ground with a 0.01 μF capacitor is recommended. NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established. PIN DESCRIPTION 4mA Q D 470 QHG QHG VBB EN VEE PIN D Q ¯ QHG/QHG ¯ VBB EN VEE VCC FUNCTION Data Input Data Output Data Outputs w/High Gain Reference Voltage Output Enable Input Negative Supply Positive Supply AZ100LVEL16VRNE D (CMOS Input Levels) D 1 2 3 4 Leave Pad open or connect to VEE AZ100LVEL16VRNE MLP 8, 2x2 mm EN Q QHG QHG 8 7 6 5 Q VCC QHG QHG VBB EN VEE TIMING DIAGRAM TOP VIEW April 2007 * REV - 15 www.azmicrotek.com 4 AZ100LVEL16VR Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC VD/D ¯ VEN VEE VD/D ¯ VEN IOUT IHGOUT TA TSTG Characteristic PECL Power Supply (VEE = 0V) PECL D/D Input Voltage ¯ (VEE = 0V) PECL EN Input Voltage (VEE = 0V) ECL Power Supply (VCC = 0V) ECL D/D Input Voltage ¯ (VCC = 0V) ECL EN Input Voltage (VCC = 0V) Output Current, Q/Q ¯ — Continuous — Surge ¯ Output Current, QHG/QHG — Continuous — Surge Operating Temperature Range Storage Temperature Range Rating 0 to +6.0 ±0.75 with respect to VBB 0 to +6.0 -6.0 to 0 ±0.75 with respect to VBB -6.0 to 0 25 50 50 100 -40 to +85 -65 to +150 Unit Vdc Vdc Vdc Vdc Vdc Vdc mA mA °C °C 100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1. 2. 3. Characteristic 1 -40°C Min -1045 -1925 Max -835 -1555 Min -1025 -1900 0° C Max -835 -1620 Min -1025 -1900 25° C Max -835 -1620 -740 VCC -1475 VEE + 800 -1250 150 Min -1025 -1900 85° C Max -835 -1620 -740 VCC -1475 VEE + 800 -1250 150 Unit mV mV mV mV mV μA μA Output HIGH Voltage Output LOW Voltage1 Input HIGH Voltage -1165 -740 -740 -1165 D/D, EN (ECL)2 ¯ -1165 VCC VCC VEE+2000 EN (CMOS)3 VEE+2000 VEE+2000 Input LOW Voltage -1900 -1475 -1900 -1475 -1900 D/D, EN (ECL)2 ¯ VEE VEE + 800 VEE VEE + 800 VEE EN (CMOS)3 Reference Voltage -1390 -1250 -1390 -1250 -1390 Input HIGH Current EN 150 150 Input LOW Current 0.5 0.5 0.5 EN (ECL)2 -150 -150 -150 EN (CMOS)3 Power Supply Current1 48 48 Specified with VEEP and CS-SEL NC, QHG/QHG terminated through 50Ω resistors to VCC - 2V. ¯ EN-SEL = NC. EN-SEL = VCC or VEE. -1165 VEE+2000 -1900 VEE -1390 0.5 -150 48 54 mA 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1. 2. 3. 4. Characteristic 1,2 -40°C Min 2255 1375 Max 2465 1745 Min 2275 1400 0° C Max 2465 1680 Min 2275 1400 2135 2000 1400 GND 1910 25°C Max 2465 1680 2560 VCC 1825 800 2050 150 Min 2275 1400 2135 2000 1400 GND 1910 85°C Max 2465 1680 2560 VCC 1825 800 2050 150 Unit mV mV mV mV mV μA μA Output HIGH Voltage Output LOW Voltage1,2 Input HIGH Voltage1 2135 2560 2135 2560 D/D, EN (PECL)3 ¯ EN (CMOS)4 2000 VCC 2000 VCC Input LOW Voltage1 D/D, EN (PECL)3 ¯ 1400 1825 1400 1825 EN (CMOS)4 GND 800 GND 800 Reference Voltage1 1910 2050 1910 2050 Input HIGH Current EN 150 150 Input LOW Current 0.5 0.5 EN (PECL)3 -150 -150 EN (CMOS)4 Power Supply Current2 48 48 For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value. ¯ Specified with VEEP and CS-SEL NC, QHG/QHG terminated through 50Ω resistors to VCC - 2V. EN-SEL = NC. EN-SEL = VCC or VEE. 0.5 -150 48 0.5 -150 54 mA April 2007 * REV - 15 www.azmicrotek.com 5 AZ100LVEL16VR 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol VOH VOL VIH VIL VBB IIH IIL IEE 1. 2. 3. 4. Characteristic 1,2 -40°C Min 3955 3075 Max 4165 3445 Min 3975 3100 0° C Max 4165 3380 Min 3975 3100 3835 2000 3100 GND 3610 25°C Max 4165 3380 4260 VCC 3525 800 3750 150 Min 3975 3100 3835 2000 3100 GND 3610 85°C Max 4165 3380 4260 VCC 3525 800 3750 150 Unit mV mV mV mV mV μA μA Output HIGH Voltage Output LOW Voltage1,2 Input HIGH Voltage1 3835 4260 3835 4260 D/D, EN (PECL)3 ¯ EN (CMOS)4 2000 VCC 2000 VCC Input LOW Voltage1 3100 3525 3100 3525 D/D, EN (PECL)3 ¯ EN (CMOS)4 GND 800 GND 800 1 Reference Voltage 3610 3750 3610 3750 Input HIGH Current EN 150 150 Input LOW Current 0.5 0.5 EN (PECL)3 -150 -150 EN (CMOS)4 Power Supply Current2 48 48 For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. ¯ Specified with VEEP and CS-SEL NC, QHG/QHG terminated through 50Ω resistors to VCC - 2V. EN-SEL = NC. EN-SEL = VCC or VEE. 0.5 -150 48 0.5 -150 54 mA AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V) Symbol tPLH / tPHL Characteristic Min -40°C Typ Max Min 0° C Typ Max Min 25° C Typ Max Min 85° C Typ Max Unit ps ps mV ps Propagation Delay 400 400 400 400 (SE) D to Q/Q Outputs1 ¯ ¯ 450 450 450 450 D to QHG/QHG Outputs2 (SE) tSKEW Duty Cycle Skew4 (SE) 5 20 5 20 5 20 5 20 VPP (AC) Differential Input Swing5 80 1000 80 1000 80 1000 80 1000 Output Rise/Fall1,2 tr / t f 100 240 100 240 100 240 100 240 (20% - 80%) 1. Specified with CS-SEL connected to VEE, Q/Q terminated with an AC coupled 50Ω load. ¯ ¯ 2. Specified with VEEP NC, QHG/QHG terminated through 50Ω resistors to VCC - 2V. 3. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 4. The peak-to-peak differential input swing is the range for which AC parameters are guaranteed. VD and VD must remain within the range of ± 750 ¯ ¯ ¯ mV with respect to VBB. The device has a voltage gain of ≈ 20 to the Q/Q outputs and a voltage gain of ≈ 100 to the QHG/QHG outputs. AC PP INPUT D D V PP ( AC) April 2007 * REV - 15 www.azmicrotek.com 6 AZ100LVEL16VR Typical Large Signal Outputs, QHG/QHG ¯ 1000 900 800 700 600 500 400 300 200 100 0 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) VOUTpp (mV) Measured with 750mv differential input, VEEP NC, QHG/QHG each terminated to VCC¯ 2V via 50 Ω resistors. April 2007 * REV - 15 www.azmicrotek.com 7 AZ100LVEL16VR 0.95 0 0.9 -10 Magnitude 0.85 -20 S11 MAG 8mA S11 MAG 4mA S11 PHASE 8mA S11 PHASE 4mA 0.8 -30 0.75 -40 0.7 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 -50 Frequency (MHz) (50 Ω external AC, 4 & 8mA internal DC Load on Q) ¯ 0.025 225 S11, D to Q ¯ 0.02 200 Magnitude 0.015 175 S12 MAG 8mA S12 MAG 4mA S12 PHASE 8mA S12 PHASE 4mA 0.01 150 0.005 125 0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 100 Frequency (MHz) (50 Ω external AC, 4 & 8mA internal DC Load on Q) ¯ S12, D to Q ¯ April 2007 * REV - 15 www.azmicrotek.com 8 Phase Phase AZ100LVEL16VR 40 200 35 175 30 150 25 125 S21 MAG 8mA S21 MAG 4mA S21 PHASE 8mA S21 PHASE 4mA Magnitude 20 100 15 75 10 50 5 25 0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 0 Frequency (MHz) (50 Ω external AC, 4 & 8mA internal DC Load on Q) ¯ S21, D to Q ¯ 0.8 200.00 0.75 190.00 0.7 180.00 0.65 170.00 S22 MAG 8mA S22 MAG 4mA S22 PHASE 8mA S22 PHASE 4mA Magnitude Phase Phase 0.6 160.00 0.55 150.00 0.5 140.00 0.45 130.00 0.4 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 120.00 Frequency (MHz) (50 Ω external AC, 4 & 8mA internal DC Load on Q) ¯ S22, D to Q ¯ April 2007 * REV - 15 www.azmicrotek.com 9 AZ100LVEL16VR AC Coupling Capacitor 3.3 or 5 V CMOS C2 R1 See table LVEL16VR Front End D D VBB C1 0.01 μF Application Circuit for CMOS Inputs R11 Input Type AC Coupled (C2 in circuit) DC Coupled (C2 shorted) 3.3 V 1.1 kΩ 2.0 kΩ CMOS 5 V CMOS 1.6 kΩ 3.3 kΩ 1 R1 should be chosen so that the input swing on the D input with respect to D is in the range of ±80 to ±1000 mV, per the ¯ AC Characteristics table and the D input is < ±750 mV with respect to VBB. Recommended Component Values for CMOS Single Ended Inputs April 2007 * REV - 15 www.azmicrotek.com 10 AZ100LVEL16VR PACKAGE DIAGRAM MLP 8 2x2mm Pin 1 Dot By Marking 2.000±0.050 2.000±0.050 MLP 8 (2x2mm) TOP VIEW 0.350±0.050 0.250±0.050 8 7 0.500 bsc 6 5 1 Pin 1 Identification R0.100 TYP 2 1.200±0.050 exp. pad 3 4 0.600±0.050 exp. pad BOTTOM VIEW 1.750 Ref. 0.750±0.050 0.000-0.050 1 2 34 0.203±0.025 SIDE VIEW Note: All dimensions are in mm April 2007 * REV - 15 www.azmicrotek.com 11 AZ100LVEL16VR PACKAGE DIAGRAM MLP 16 D 2. INDEX AREA (D/2 x E/2) A D 2 E 2 E 3x e e B D2 D2/2 E2/2 E2 2 1 5. 2x 2x aaa C aaa C TOP VIEW bbb M C A B 16 x b 3. 3x e BOTTOM VIEW L ccc C A 4. 0.08 C SIDE VIEW A3 C SEATING PLANE A1 NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME T14-1994. 2. THE TERMINAL #1 AND PAD NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. 3. DIMENSION b APPLIES TO METALLIZED PAD AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM PAD TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. 5. INSIDE CORNERS OF METALLIZED PAD MAY BE SQUARE OR ROUNDED MILLIMETERS DIM A A1 A3 b D D2 E E2 e L aaa bbb ccc MIN MAX 0.80 1.00 0.05 0.00 0.25 REF 0.18 0.30 3.10 2.90 1.95 0.25 3.10 2.90 1.95 0.25 0.50 BSC 0.50 0.30 0.25 0.10 0.10 April 2007 * REV - 15 www.azmicrotek.com 12 AZ100LVEL16VR Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. April 2007 * REV - 15 www.azmicrotek.com 13