AZV99NG

ARIZONA MICROTEK, INC. AZV99 PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable FEATURES • • • • • • • Green and RoHS Compliant / Lead (Pb) Free Packages Available Similar Operation as AZ100LVEL16VT except with LVDS Outputs Operating Range of 3.0V to 5.5V Minimizes External Components Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Available in a 2x2 or 3x3mm MLP Package S–Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website PACKAGE MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 16 (3x3) Green / RoHS Compliant / Lead (Pb) Free TSSOP 8 RoHS Compliant / Lead (Pb) Free DIE DIE 1 2 3 4 5 PACKAGE AVAILABILITY PART NUMBER AZV99NG AZV99NA AZV99NBG MARKING V1G V9 V8G V2G AZMG V99 AZ+ V99 N/A N/A NOTES 1,2 1,2 1,2 AZV99NDG 1,2 AZV99LG AZV99T+ AZV99XP AZV99XR 1,2 1,2,3 4 5 DESCRIPTION Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “Y” for year followed by “WW” for week. Date Code “YWW” on underside of part. Waffle Pack. Die thickness 180 μm. Die on 7 inch Tape & Reel, 3k parts per reel. Die thickness 180 μm. The AZV99 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable input (EN) allows continuous oscillator operation by only controlling the QHG /QHG outputs. ¯ ¯ The AZV99 also provides a VBB and 470Ω internal bias resistors from D to VBB and D to VBB. The VBB pin can support 1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended. MLP 16, 3x3 mm Package (L) or DIE (X) The MLP 16 and die versions of the AZV99 provide a selectable enable (EN). Enable polarity and threshold can be selected to accommodate either CMOS/TTL or PECL input levels. See the enable truth table for enable function. If enable pull-up is desired in the CMOS/TTL mode, an external ≤20kΩ resistor connecting EN to VCC will override the on-chip pull-down resistor. Outputs Q/Q each have a selectable on-chip pull-down current source. See the current source truth table for ¯ current source functions. External resistors may also be used to increase pull-down current to a maximum of 25mA (includes internal on-chip current source). 1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414 www.azmicrotek.com AZV99 MLP 8, 2x2 mm Package, NA, NB & ND Options The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (EN When the ¯¯¯). ¯¯¯ input is LOW, the Q and QHG/QHG outputs pass data from the inputs. When ¯¯¯ is HIGH, the Q output EN ¯ ¯ EN ¯ continues to pass data while the QHG output is forced high and the QHG output is forced low. ¯ Only the Q output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of ¯ CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current source). The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D input is internally ¯ bonded directly to the VBB pin bypassing the 470Ω bias resistor. TSSOP 8 Package (T), MLP 8 Package, (N) The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When the EN input is HIGH, the Q and QHG/QHG outputs pass data from the inputs. When EN is LOW, the Q output ¯ ¯ ¯ continues to pass data while the QHG output is forced high and the QHG output is forced low. ¯ Only the Q output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of ¯ CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current source). The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D input is internally ¯ bonded directly to the VBB pin bypassing the 470Ω bias resistor. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. PIN DESCRIPTION Q 4mA EA. PIN D/D ¯ Q/Q ¯ QHG/QHG ¯ VBB EN-SEL EN/EN ¯¯ CS-SEL VEE VCC FUNCTION Data Inputs PECL Data Outputs LVDS Data Outputs Reference Voltage Output Selects Enable Logic Enable Input Selects Q and Q Current Source Magnitude ¯ Negative Supply Positive Supply Q D D 470 CS-SEL QHG QHG VBB VEE EN/EN CMOS/TTL THRESHOLD EN-SEL ENABLE TRUTH TABLE EN-SEL EN/EN ¯¯¯ Q/Q ¯ QHG QHG ¯ CURRENT SOURCE TRUTH TABLE CS-SEL Q Q ¯ NC 4mA typ. 4mA typ. VEE1 8mA typ. 8mA typ. 0 4mA typ. VCC1 1 CS-SEL connections must be less than 1Ω. NC PECL Low or NC Data Data Data NC PECL High or VCC Data High Low CMOS/TTL Low, VEE or NC VEE1 Data High Low VEE1 CMOS/TTL High or VCC2 Data Data Data 1 EN-SEL connections must be less than 1Ω. 2 An external ≤20kΩ pull-up resistor between EN and VCC ensures a High when the EN pin is not driven. June 2009 * REV - 13 www.azmicrotek.com 2 AZV99 Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC VI VD/D ¯ IOUT TA TSTG Characteristic Power Supply Input Voltage D/D Input Voltage ¯ Output Current — Continuous Q/Q ¯ — Surge Q/Q ¯ ¯ — Continuous QHG/QHG ¯ — Surge QHG/QHG Operating Temperature Range Storage Temperature Range Rating 0 to +6.0 0 to +6.0 ±0.75 with respect to VBB 25 50 5 10 -40 to +85 -65 to +150 Unit Vdc Vdc Vdc mA °C °C 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) Symbol VOH VOL VIH VIL VBB IIL IIH IEE 1. 2. 3. Characteristic 1,2 -40°C Min 2255 1375 2135 2000 1400 GND 1910 0.5 Max 2465 1745 2560 VCC 1825 800 2050 150 48 Min 2275 1400 2135 2000 1400 GND 1910 0.5 0° C Max 2465 1680 2560 VCC 1825 800 2050 150 48 Min 2275 1400 2135 2000 1400 GND 1910 0.5 25°C Max 2465 1680 2560 VCC 1825 800 2050 150 48 Min 2275 1400 2135 2000 1400 GND 1910 0.5 85°C Max 2465 1680 2560 VCC 1825 800 2050 150 52 Unit mV mV mV mV mV μA μA mA Output HIGH Voltage Q/Q ¯ Output LOW Voltage1,2 Q/Q ¯ Input HIGH Voltage D/D1, EN (EN-SEL open)1 ¯ EN (EN-SEL tied to VEE) Input LOW Voltage D/D1, EN (EN-SEL open)1 ¯ EN (EN-SEL tied to VEE) Reference Voltage1 Input LOW Current EN3 Input HIGH Current EN3 Power Supply Current2 Voltage levels vary 1:1 with VCC. Specified with CS-SEL open. Specified with EN-SEL open. 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol VOH VOL VIH VIL VBB IIL IIH IEE 1. 2. 3. Characteristic 1,2 -40°C Min 3955 3075 3835 2000 3100 GND 3610 0.5 Max 4165 3445 4260 VCC 3525 800 3750 150 48 Min 3975 3100 3835 2000 3100 GND 3610 0.5 0° C Max 4165 3380 4260 VCC 3525 800 3750 150 48 Min 3975 3100 3835 2000 3100 GND 3610 0.5 25°C Max 4165 3380 4260 VCC 3525 800 3750 150 48 Min 3975 3100 3835 2000 3100 GND 3610 0.5 85°C Max 4165 3380 4260 VCC 3525 800 3750 150 52 Unit mV mV mV mV mV μA μA mA Output HIGH Voltage Q/Q ¯ Output LOW Voltage1,2 Q/Q ¯ Input HIGH Voltage D/D1, EN (EN-SEL open)1 ¯ EN (EN-SEL tied to VEE) Input LOW Voltage D/D1, EN (EN-SEL open)1 ¯ EN (EN-SEL tied to VEE) Reference Voltage1 Input LOW Current EN3 Input HIGH Current EN3 Power Supply Current2 Voltage levels vary 1:1 with VCC. Specified with CS-SEL open. Specified with EN-SEL open. June 2009 * REV - 13 www.azmicrotek.com 3 AZV99 ¯ LVDS DC Characteristics for QHG/QHG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V) Symbol Characteristic -40°C Min Max 1600 Min 0° C Max 1600 Min 25°C Max 1600 1375 50 450 900 Min 900 1125 -50 250 500 85°C Max 1600 1375 50 450 900 Unit mV mV mV mV mV mV VOH Output HIGH Voltage VOL Output LOW Voltage 900 900 900 VOC Output Common Mode Voltage2 1125 1375 1125 1375 1125 Change in Common Mode Voltage3 -50 50 -50 50 -50 ΔVOC VOUT Single-Ended Output Swing 250 450 250 450 250 VDIFF_OUT Differential Output Swing 500 900 500 900 500 1. Specified with 100Ω resistor connecting QHG and QHG together. ¯ ¯ 2. Common mode voltage is the center voltage between QHG and QHG during a steady state. 3. Change in common mode voltage is the difference between common mode voltages at opposite binary states. AC Characteristics (VEE = GND, VCC = +3.0V to +5.5V) Symbol tPLH / tPHL tSKEW VPP (AC) tr / t f 1. 2. 3. 4. Characteristic Propagation Delay D to Q/Q Outputs1 ¯ D to QHG/QHG Outputs2 ¯ Duty Cycle Skew Q/Q3 ¯ Differnetial Input Swing4 Output Rise/Fall Times (20% - 80%) (SE) (SE) (SE) 80 Min -40°C Typ Max 400 550 20 1000 Min 0° C Typ Max 400 550 20 1000 Min 25° C Typ Max 400 550 20 1000 Min 85° C Typ Max 430 630 20 1000 Unit ps ps mV ps 5 5 80 5 80 5 80 100 260 100 260 100 260 100 260 Q/Q1 ¯ ¯ 180 280 180 280 180 280 180 280 QHG/QHG2 Specified with CS-SEL connected to VEE and Q/Q with AC coupled 50Ω loads. ¯ ¯ Specified with 100Ω resistor connecting QHG and QHG together. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and VD must remain within the range of ±750 mV ¯ with respect to VBB. AC PP INPUT D D V PP ( AC) June 2009 * REV - 13 www.azmicrotek.com 4 AZV99 0.95 0 0.9 -10 0.85 -20 S11 MAG 8mA S11 MAG 4mA S11 PHASE 8mA S11 PHASE 4mA Magnitude 0.8 -30 0.75 -40 0.7 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 -50 Frequency (MHz) S11, D to Q, 50 Ω AC load on Q ¯ ¯ 0.025 250.00 0.02 200.00 0.015 150.00 S12 MAG 8mA S12 MAG 4mA S12 PHASE 8mA S21 PHASE 4mA Magnitude 0.01 100.00 0.005 50.00 0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 0.00 Frequency (MHz) S12, D to Q, 50 Ω AC load on Q ¯ ¯ June 2009 * REV - 13 www.azmicrotek.com 5 Phase Phase AZV99 40 180 35 160 30 140 25 120 S21 MAG 8mA S21 MAG 4mA S21 PHASE 8mA S21 PHASE 4mA Magnitude 20 100 15 80 10 60 5 40 0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 20 Frequency (MHz) S21, D to Q, 50 Ω AC load on Q ¯ ¯ 0.8 180.00 0.7 160.00 Magnitude Phase 0.6 140.00 S22 MAG 8mA S22 MAG 4mA S22 PHASE 8mA S22 PHASE 4mA 0.5 120.00 0.4 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 100.00 Frequency (MHz) S22, D to Q, 50 Ω AC load on Q ¯ ¯ June 2009 * REV - 13 www.azmicrotek.com 6 Phase AZV99 AC Coupling Capacitor 3.3 or 5 V CMOS C2 R1 See table AZV99 Front End D D VBB C1 0.01 μF Application Circuit for CMOS Inputs R11 Input Type AC Coupled (C2 in circuit) DC Coupled (C2 shorted) 3.3 V 1.1 kΩ 2.0 kΩ CMOS 5 V CMOS 1.6 kΩ 3.3 kΩ 1 R1 should be chosen so that the input swing on the D input with respect to D is in the range of ±80 to ±1000 mV, per the ¯ AC Characteristics table and the D input is < ±750 mV with respect to VBB. Recommended Component Values for CMOS Single Ended Inputs June 2009 * REV - 13 www.azmicrotek.com 7 AZV99 TIMING DIAGRAM D EN/ EN { EN-SEL OPEN (EN) (PECL) (CMOS/TTL) EN-SEL SHORTED TO VEE (EN) Q Q QHG QHG PINOUT FOR AZV99L MLP 16, 3x3mm AZV99L Q 16 NC D D VBB 1 2 3 4 5 EN 6 NC 7 VEE 8 NC Q 15 NC 14 VCC 13 12 CS-SEL 11 QHG 10 QHG 9 EN-SEL TOP VIEW Bottom Center Pad may be left open or tied to VEE June 2009 * REV - 13 www.azmicrotek.com 8 AZV99 LOGIC DIAGRAMS AND PINOUTS FOR AZV99NA, AZV99NB, AZV99ND 4mA 4mA Q D D 470 470 VEE QHG QHG Q D 470 VEE QHG QHG VBB EN VBB/D AZV99NA EN AZV99NB AZV99ND EN operation follows PECL functionality. See the Timing Diagram. MLP 8, 2x2mm D D VBB EN 1 2 VEE 3 4 6 5 QHG QHG EN VEE 3 4 6 5 QHG QHG AZV99NA 8 7 Q VCC D VBB/D 1 2 MLP 8, 2x2mm AZV99NB 8 7 Q VCC TOP VIEW TOP VIEW Bottom Center Pad is the VEE return. Bottom Center Pad may be left open or tied to VEE. Pin 4 is the VEE return. MLP 8, 2x2mm Q D VBB/D EN 1 2 3 4 AZV99ND 8 7 6 VCC QHG QHG TOP VIEW 5 VEE Bottom Center Pad may be left open or tied to VEE. Pin 5 is the VEE return. June 2009 * REV - 13 www.azmicrotek.com 9 AZV99 LOGIC DIAGRAM AND PINOUTS FOR AZV99T, AZV99N 4mA Q D 470 VEE QHG QHG VBB/D EN CMOS/TTL THRESHOLD AZV99T AZV99N EN follows CMOS/TTL functionality. See the Timing Diagram. Q1 D2 VBB / D 3 EN 4 8 VCC 7 QHG 6 QHG 5 VEE AZV99T TSSOP 8 MLP 8, 2x2mm Q D VBB/D EN 1 2 3 4 AZV99N 8 7 6 VCC QHG QHG TOP VIEW 5 VEE Bottom Center Pad may be left open or tied to VEE. Pin 5 is the VEE return. June 2009 * REV - 13 www.azmicrotek.com 10 AZV99 DIE PAD COORDINATES AZV99 DIE: AZV99 A B C D M L K J I H G DIE SIZE: 950u X 940u DIE THICKNESS: 180u BOND PAD: 85u X 85u E F Note: Other die thicknesses available. Contact factory for further information. PAD COORDINATES1 NAME A B C D E F G H I J K L M 0, 0 is center of die. PAD DESIGNATION D D ¯ VBB EN/EN ¯¯¯ VEE NC EN-SEL QHG ¯ QHG CS-SEL VCC Q Q ¯ PAD CENTERS X(Microns) Y(Microns) -342.5 312.5 -342.5 144.5 -342.5 -87.0 -342.5 -255.0 -33.5 -312.5 126.5 -312.5 312.5 -248.5 312.5 -98.5 312.5 51.5 312.5 201.5 302.5 342.5 142.5 342.5 -140.5 342.5 1. June 2009 * REV - 13 www.azmicrotek.com 11 AZV99 DIE ON TAPE ORIENTATION DIE ID Direction of Feed Package X (Die) Suffix R Reel Diameter 7” Quantity 3000 Carrier Tape Width 8mm Carrier Tape Pitch 4mm June 2009 * REV - 13 www.azmicrotek.com 12 AZV99 PACKAGE DIAGRAM MLP 16 D 2. INDEX AREA (D/2 x E/2) A D 2 E 2 E 3x e e B D2 D2/2 E2/2 E2 2 1 5. 2x 2x aaa C aaa C TOP VIEW bbb M C A B 16 x b 3. 3x e BOTTOM VIEW L ccc C A 4. 0.08 C SIDE VIEW A3 C SEATING PLANE A1 NOTES: 1. DIMENSIONING AND TOLERANCING CONFORM TO ASME T14-1994. 2. THE TERMINAL #1 AND PAD NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. 3. DIMENSION b APPLIES TO METALLIZED PAD AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM PAD TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. 5. INSIDE CORNERS OF METALLIZED PAD MAY BE SQUARE OR ROUNDED MILLIMETERS DIM A A1 A3 b D D2 E E2 e L aaa bbb ccc MIN MAX 0.80 1.00 0.05 0.00 0.25 REF 0.18 0.30 2.90 3.10 0.25 1.95 2.90 3.10 0.25 1.95 0.50 BSC 0.30 0.50 0.25 0.10 0.10 June 2009 * REV - 13 www.azmicrotek.com 13 AZV99 PACKAGE DIAGRAM MLP 8 2x2mm Pin 1 Dot By Marking 2.000±0.050 2.000±0.050 MLP 8 (2x2mm) TOP VIEW 0.350±0.050 0.250±0.050 8 7 0.500 bsc 6 5 1 Pin 1 Identification R0.100 TYP 2 1.200±0.050 exp. pad 3 4 0.600±0.050 exp. pad BOTTOM VIEW 1.750 Ref. 0.900±0.050 0.000-0.050 1 2 34 0.203±0.025 SIDE VIEW Note: All dimensions are in mm June 2009 * REV - 13 www.azmicrotek.com 14 AZV99 PACKAGE DIAGRAM TSSOP 8 NOTES: 1. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 2. MAXIMUM MOLD PROTRUSION FOR D IS 0.15mm. 3. MAXIMUM MOLD PROTRUSION FOR E IS 0.25mm. DIM A A1 A2 A3 bp c D E e HE L Lp v w y Z θ MILLIMETERS MIN MAX 1.10 0.05 0.15 0.80 0.95 0.25 0.25 0.45 0.15 0.28 2.90 3.10 2.90 3.10 0.65 4.70 5.10 0.94 0.40 0.70 0.10 0.10 0.10 0.35 0.70 6O 0O June 2009 * REV - 13 www.azmicrotek.com 15 AZV99 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. June 2009 * REV - 13 www.azmicrotek.com 16