74AUP1G00SE-7

74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single two-input positive NAND gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Y = A • B or Y = A + B Applications Features • • • • • • Advanced Ultra Low Power (AUP) CMOS • Low Dynamic Power Consumption CPD = 6pF (Typical at 3.6V) • Schmitt Trigger Action at all inputs makes the circuit tolerant for Supply Voltage Range from 0.8V to 3.6V ±4 mA Output Drive at 3.0V Low Static Power Consumption ICC < 0.9µA Suited for Battery and Low Power Needs Wide array of products such as:
Tablets, E-readers
Cell Phones, Personal Navigation / GPS
MP3 Players ,Cameras, Video Recorders
PCs, Ultrabooks, Notebooks, Netbooks
Computer Peripherals, Hard Drives, SSDs, CD/DVD ROMs
TVs, DVDs, DVRs, Set-Top Boxes slower input rise and fall time. The hysteresis is typically 250mV at VCC = 3.0V. • IOFF Supports Partial-Power-Down Mode Operation • ESD Protection Exceeds JESD 22 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101) • • • • Latch-Up Exceeds 100mA per JESD 78, Class I Leadless Packages Named per JESD30E Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) Halogen and Antimony Free. “Green” Device (Note 3) Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain