A Product Line of
Diodes Incorporated
AA4003
2W STEREO AUDIO POWER AMPLIFIER WITH SHUTDOWN
Description
Pin Assignments
The AA4003 is a Class AB stereo Audio Power Amplifier which can
deliver 2.0W into 4Ω speakers with limitation of THD+N less than 1%.
The chip is designed specially for Portable DVD player, Portable
Media Player, LCD monitor and Digital Photo Frame applications.
(Top View)
SHUTDOWN
1
20
HP-SENSE
GND
2
19
GND
OUTL+
3
18
OUTR+
VDD
4
17
VDD
OUTL-
5
16
OUTR-
LIN-
6
15
RIN-
GND
7
14
BYPASS
LIN+
8
13
RIN+
PGND
9
12
PGND
PGND
10
11
PGND
AA4003 is available in packages of SOIC-16 and TSSOP-20(EDP).
Features
Output Power
BTL: 2.0W/CH (4Ω, THD+N≤1%)
SE: 160mW/CH (16Ω, THD+N≤1%)
Supply Voltage Range: 2.7V to 5.5V
External Feedback Loop for Flexible Gain Set-up
Low Power Consumption at Shutdown Mode 0.7µA Typical
SE, BTL Mode Switchable
Optimized Click/POP Noise Suppression
Thermal Shutdown Protection
TSSOP-20(EDP) (G Package)
Applications
(Top View)
Portable DVD Player
Portable Media Player
LCD Monitor
Digital Photo Frame
SHUTDOWN
1
16
HP-SENSE
GND
2
15
GND
OUTL+
3
14
OUTR+
VDD
4
13
VDD
OUTL-
5
12
OUTR-
LIN-
6
11
RIN-
GND
7
10
BYPASS
LIN+
8
9
RIN+
SOIC-16 (M Package)
AA4003
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AA4003
Typical Applications Circuit
RF
20k
VDD
CS
10F
+
4,13
CI
1uF
+
Left IN
RI
20k
6
LIN-
8
LIN+
COUT RPD
220F 1.5k
+
_
OUTL-
5
OUTL+
3
+
20k
VDD
16
100k
HP-SENSE
20k
AMP1L
100k
_
To control pin
CI
1F
+
Right IN
+
RI
20k
Cb
1.0F
To HP-Sense circuit
AMP2L
10
BYPASS
11
RIN-
9
RIN+
COUT
220F
+
_
OUTR-
+
12
20k
+
20k
AMP1R
SLEEVE
RPD
1.5k
HEADPHONE
JACK
_
+
1
SHUTDOWN
OUTR+
14
AMP2R
2,7,15
RF
20k
Typical Application Circuit of AA4003 (M Package)
AA4003
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AA4003
Pin Descriptions
Pin Number
Pin Name
Function
G Package
M Package
1
1
2,7,19
2,7,15
GND
3
3
OUTL+
4,17
4,13
VDD
5
5
OUTL-
6
6
LIN-
Left channel negative input
8
8
LIN+
Left channel positive input
9,10,11,12
–
PGND
Power ground, used for thermal release
13
9
RIN+
Right channel positive input
14
10
BYPASS
15
11
RIN-
16
12
OUTR-
Right channel negative output
18
14
OUTR+
Right channel positive output
20
16
HP-SENSE
SHUTDOWN
Shutdown mode enable pin, active High
Signal ground
Left channel positive output
Power supply pin
Left channel negative output
Internal reference voltage pin, connect a 1.0µF capacitor to GND
Right channel negative input
SE, BTL Mode switch pin,
L – BTL Mode
H – SE Mode
Absolute Maximum Ratings (Note 1)
Symbol
Notes:
Parameter
VDD
Supply Voltage
VIN
Input Voltage
PD
Power Dissipation
θJA
Package Thermal Resistance
TJ
Operating Junction Temperature
Rating
Unit
6
V
-0.3 to VDD+0.3
V
Internally limited
–
M Package
90
G Package
50 (Note 2)
ºC/W
+150
ºC
TSTG
Storage Temperature Range
-65 to +150
ºC
TLEAD
Lead Temperature 1.6mm from Case for 10 Seconds
+260
ºC
–
ESD (Human Body Model)
2000
V
–
ESD (Machine Model)
300
V
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied.
Exposure to “Absolute Maximum Ratings” for extended periods may affect device reliability.
2. Chip is soldered to 200mm2 copper (top side solder mask) of 1oz. on PCB with 8x0.5mm vias.
Recommended Operating Conditions
Symbol
VDD
TA
Parameter
Min
Max
Unit
Supply Voltage
2.7
5.5
V
Operating Ambient Temperature
-40
+85
C
AA4003
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AA4003
Electrical Characteristics
(VDD=5V, TA=+25oC, CI=1µF, COUT=220µF and RI=RF=20kΩ unless otherwise specified. For SE Mode,
HP_SENSE=5V, for BTL Mode, HP_SENSE=0V)
Symbol
Parameter
IDD
Quiescent Current
ISD
Shutdown Current
VIH
HP_SENSE LOGIC
VIL
Min
Typ
Max
SE Mode, VIN=0, IO=0
Conditions
–
3
10
BTL Mode, VIN=0, IO=0
–
6
20
VSHUTDOWN=5V
–
0.7
2.0
µA
–
4
–
–
V
–
–
–
0.8
V
V
–
3
–
–
VIL
–
–
–
0.8
–
Thermal Shutdown Temperature
–
Hysteresis Temperature Window
–
–
THD+N=1%, RL=32Ω
THD+N=10%, RL=32Ω
THD+N=1%, RL=16Ω
VIH
–
SHUTDOWN LOGIC
Unit
mA
V
–
o
+25
–
o
–
80
–
–
110
–
–
160
–
–
+170
C
C
SE Mode
PO
THD+N
SNR
Output Power
mW
THD+N=10%, RL=16Ω
–
220
–
Total Harmonic Distortion + Noise
PO=75mW, RL=32Ω
–
0.2
–
%
Signal to Noise Ratio
PO=75mW, RL=32Ω
–
90
–
dB
PO=75mW, RL=32Ω,
f=1kHz
Cb=1µF, f=1kHz,
VRIPPLE=0.2VRMS,
RL=16Ω
–
-80
–
dB
–
60
–
dB
VIN=0V, No load
–
±5
±50
mV
THD+N=1%, RL=4Ω
–
2
–
THD+N=10% RL=4Ω
–
2.5
–
THD+N=1% RL=8Ω
–
1.1
–
THD+N=10% RL=8Ω
–
1.5
–
Total Harmonic Distortion + Noise
PO=1W, RL=4Ω
–
0.1
–
%
XTALK
Crosstalk
PSRR
Power Supply Rejection Ratio
BTL Mode
VOS
PO
THD+N
Output Offset Voltage
Output Power
W
SNR
Signal to Noise Ratio
PO=1W, RL=8Ω
–
95
–
dB
XTALK
Crosstalk
PO=1W, RL=8Ω, f=1kHz
–
-80
–
dB
PSRR
Power Supply Rejection Ratio
Cb=1µF,f=1kHz,
VRIPPLE=0.2VRMS,
RL=8Ω
–
67
–
dB
AA4003
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Performance Characteristics
Quiescent Current vs. Supply Voltage
Quiescent Current vs. Ambient Temperature
10
THD+N (%)
1
VDD=5.0V, SE Mode
VDD=5.0V, BTL Mode
f=1kHz, LPF=30kHz
RL=16
f=1kHz
LPF=30kHz
RL=4
RL=32
1
THD+N (%)
10
0.1
RL=8
0.1
0.01
1E-3
10m
300m
100m
0.01
10m
100m
THD+N vs. Output Power @ SE Mode
THD+N vs. Output Power @ BTL Mode
10
10
VDD=5.0V, SE Mode
VDD=5.0V, BTL Mode
COUT=1000F, PO=150mW
PO=1.5W, RL=4
RL=16, LPF=80kHz
LPF=80kHz
1
1
THD+N (%)
THD+N (%)
3
1
Output Power (W)
Output Power (W)
0.1
0.1
0.01
20
100
1k
10k
20k
0.01
20
Frequency (Hz)
Document number: DS36881 Rev. 2 - 2
1k
10k
20k
Frequency (Hz)
THD+N vs. Frequency @ SE Mode
AA4003
100
THD+N vs. Frequency @ BTL Mode
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Performance Characteristics (Cont.)
10
10
SE Mode, VDD=5.0V
BTL Mode, VDD=5.0V
PO=75mW, RL=32
PO=1W, RL=8
LPF=80kHz, COUT=1000F
LPF=80kHz
1
THD+N (%)
THD+N (%)
1
0.1
0.1
0.01
20
100
1k
10k
0.01
20
20k
100
1k
Frequency (Hz)
10k
20k
Frequency (Hz)
THD+N vs. Frequency @ SE Mode
THD+N vs. Frequency @ BTL Mode
800
2.5
VDD=5.0V, SE Mode
f=1kHz, LPF=30kHz
THD+N=10%
THD+N=1%
f=1kHz, LPF=30kHz
THD+N=10%
THD+N=1%
2.0
Output Power (W)
Output Power (mW)
600
VDD=5.0V, BTL Mode
400
1.5
1.0
200
0.5
0
10
20
30
40
50
60
0.0
0.0
70
5.0
10.0
Output Power vs. Resistor Load @ SE Mode
25.0
30.0
35.0
3.0
BTL Mode, RL=4
SE Mode, RL=16
2.5
Output Power (mW)
f=1kHz, LPF=30kHz
THD+N=10%
THD+N=1%
200
Output Power (mW)
20.0
Output Power vs. Resistor Load @ BTL Mode
250
150
100
50
0
2.5
15.0
Resistor Load ()
Resistor Load ()
f=1kHz, LPF=30kHz
THD+N=10%
THD+N=1%
2.0
1.5
1.0
0.5
3.0
3.5
4.0
4.5
5.0
Output Power vs. Supply Voltage @ SE Mode
Document number: DS36881 Rev. 2 - 2
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
Supply Voltage (V)
AA4003
0.0
2.5
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Output Power vs. Supply Voltage @ BTL Mode
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AA4003
Performance Characteristics (Cont.)
70
75
70
60
65
PSRR (dB)
PSRR (dB)
50
40
30
55
50
VDD=5.0V, SE Mode
RL=32,Cb=1.0F
45
VRIPPLE=0.2Vrms
20
60
VDD=5.0V, BTL Mode
RL=8, Cb=1.0F
VRIPPLE=0.2Vrms
40
10
10
100
1k
10k
10
20k
100
1k
10k
20k
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency @ SE Mode
PSRR vs. Frequency @ BTL Mode
4
1000
-80
VDD=5.0V
800
0
-120
400
-160
-8
Phase
-200
Phase (deg)
600
Gain (dB)
Start-up Time (ms)
Gain
-4
-12
-240
200
-16
SE Mode, VDD=5.0V
RF=RI=20k, COUT=1000F
0
0.2
0.4
0.6
0.8
1.0
Bypass Capacitor (F)
Document number: DS36881 Rev. 2 - 2
100
1k
10k
-280
100k
1M
10M
Frequency (Hz)
Start-up Time vs. Bypass Capacitor
AA4003
-20
10
Closed Loop Frequency Response
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AA4003
Application Information
SE/BTL Mode, HP_SENSE Pin
The AA4003 can operate under 2 types of output configuration, BTL (Bridged-Tied-Load) mode and SE (Single-Ended) mode, determined by
HP_SENSE pin's logic level. (Here is the discussion about left channel only, it equally applies to right channel.)
COUT
220F
+
_
Left Out-
+
20k
20k
AMP1L
COUT
220F
+
_
RPD
1.5k
Left Out-
+
20k
20k
AMP1L
Main
Speak
_
+
+
Headphone
Speak
Main
Speak
_
Left Out+
AMP2L
RPD
1.5k
Left Out+
AMP2L
VDD
R1
100k
R2
100k
VDD
R1
R2
100k 100k
SLEEVE
HP_SENSE= Low Level
HEADPHONE
JACK
Figure 1. Output Configuration for Left Channel in BTL Mode
HP_SENSE= High Level
Figure 2. Output Configuration for Left Channel in SE Mode
When HP_SENSE pin is held low which sets the chip in BTL mode, the AMP2L unit is turned on. AMP2L has fixed unity gain internally, AC signal
at OUT+ is 180 degree phase shifted from OUT-. Because the DC component (Output Bias voltage, approx 1/2 V DD) between OUT+ and OUT- is
canceled, there is no necessity to use DC block capacitors for main speak. In BTL mode, output voltage swing across main speaker is about 2
times that in SE mode, so there is 4 times output power compared to SE mode with same load and input. (see Figure 1)
If applying high level to HP_SENSE pin which sets the chip in SE mode, the AMP2L unit is in high impedance state. There is no current loop
between OUT+ and OUT-, the main speak is naturally disabled without any hardware change. The output audio signal rides on bias voltage at
OUT- (Output Bias voltage, approx 1/2 VDD), so it has to use a capacitor COUT to block DC bias and couple AC signal to headphone speak. (See
Figure 2)
It is recommended to connect HP_SENSE to the headphone jack switch pin illustrated in Figure 1.
When headphone plug is not inserted, the voltage of HP_SENSE pin is determined by voltage divider formed by R1 and RPD. For given resistor's
value in Figure 1, R1=100kΩ, RPD=1.5kΩ, DC voltage at HP_SENSE is about 74mV. AC signal equals output amplitude of OUT- through COUT, so
signal at HP_SENSE node is 74mV DC plus AC signal. The maximum peak-to-peak voltage at OUT- is no greater than VDD (supply voltage 5.0V),
so the positive maximum voltage of HP_SENSE node will be no greater than 2.5V+75mV≈2.575V, which is less than HP_SENSE input high level
minimum value (4.0V). That means the chip is in BTL mode and there is no risk of operation mode switch between SE and BTL. When
headphone plug is inserted, as the RPD is disconnected from R1, the voltage of HP_SENSE pin is pulled up by R1 to V DD and sets the chip in SE
mode.
HP_SENSE pin can also be connected to MCU I/O port to control the mode switch through MCU.
It is necessary to note that AA4003 still can drive headphone even in BTL mode because OUT- is always active whatever the chip is in SE or BTL
mode.
CIN, COUT, Cb and CS (Power Supply) Selection
For input stages of AA4003, input capacitors CI is used to accommodate different DC level between input source and AA4003 bias voltage (about
2.31V). Input capacitors CI and input resistors RI form a first order High Pass Filter, which determines the lower corner frequency according to the
classic equation below,
f CIL
1
………………………..(1)
2R I C I
Similarly, for output stage in SE mode, output capacitor (COUT), and headphone load also form a first order High Pass Filters, and its cut-off
frequency is determined by equation 2.
AA4003
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Application Information (Cont.)
f COL
1
2R HP C OUT
………………….(2)
The purpose of bypass capacitor (Cb) is to filter internal noise, reduce harmonic distortion, and improve power supply rejection ratio performance.
Tantalum or ceramic capacitor with low ESR is recommended, and it should be placed as close as possible to the chip in PCB layout. The chip will
not work until internal DC bias is set up completely. So the size of Cb will also affect the chip start up time, which is approx linearly proportional to
the value of bypass capacitor. For AA4003, here are various start-up times for several typical capacitor values. (see Figure “Start-up Time vs
Bypass Capacitor” in page 7)
Cb (µF)
Start up Time (ms)
0.33
340
0.47
420
1.0
970
For AA4003 power supply, it is better to use an individual power source generated from voltage regulator split from video, digital circuit units in
system. The power supply bypass capacitors, CS, is recommended to use one low ESR electrolytic capacitor between 4.7µF to 10µF with a
parallel 0.1µF ceramic capacitor which is located close to the chip.
Setup Proper Gain, Design Example
The closed loop gain of AA4003 is determined by the ratio of feedback resistor (RF) to input resistor (RI).
AV
RF
…………………………….(3)
RI
Example:
VDD=5V, RL=8Ω, BTL configuration, Desired output power PO=1.0W (each channel), THD+N≤1%.Input signal, VIN=1.0VRMS from D-A converter.
Step 1,
To check if the chip can deliver 1W to 8Ω load with the limitation of THD+N≤1%, VDD=5V. From Figure “THD+N vs. Output Power @BTL Mode”
in Page 5, Figure “Output Power vs. Resistor Load @ BTL Mode” in Page 6, AA4003 can deliver 1W to 8Ω load each channel.
Step 2,
If yes, to calculate output voltage,
VOUT PO R L 1* 8 2.83VRMS
So pass-band gain, AV=VOUT/VIN=2.83x.
Step 3,
Assuming input resistor is 20kΩ, the feedback resistor=20kΩ*1.415=28.3kΩ. Select the closest standard value 28kΩ.
Shutdown
AA4003 has a shutdown feature to reduce power consumption. If apply high level to shutdown pin, output amplifiers will be turned off, bias circuit
is also disabled, the maximum current drawn from VDD is less than 2.0µA. A logic low level will enable the device.
Optimizing CLICK/POP Noise
The AA4003 includes optimized circuits to suppress CLICK/POP noise during power up/power down transition.
In BTL mode the AA4003 can effectively reduce most common mode signal including CLICK/POP noise.
In SE mode, optimized ramp for rise/fall edge of BIAS can significantly reduce click/pop noise due to charge and/or discharge output capacitor
(COUT). Furthermore, increasing bypass capacitor value (Cb) can slower ramp of charging bypass capacitor, prolong start-up time, mask most of
transient noises before bias voltage is set up completely. It is recommended to use 1.0µF capacitor with lower ESR.
AA4003
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Application Information (Cont.)
Power Dissipation, Efficiency and Thermal Design Consideration
For Class AB amplifiers, Formula 4 is the basic equation of efficiency worked in BTL configuration,
VP
…………………………… (4)
4VDD
here VP is output peak voltage across the load.
Thermal dissipation becomes major concern when delivering more output power especially in BTL mode. The maximum power dissipation can be
calculated by following equation.
PDMAX
TJMAX TA
………………….(5)
JA
Here TJMAX is maximum operating junction temperature, 150oC, TA is ambient temperature, θJA is thermal resistance from junction to ambient,
which is 50oC/W for TSSOP-20(EDP), given in datasheet.
Assuming TA is 25oC, the maximum power dissipation PDMAX is about 2.5W according to formula 6.
There is another formula about power dissipation which is determined by supply voltage and load resistance.
2
PDBTLMAX
2VDD
…………………….(6)
2 R L
If power dissipation calculated in an application is larger than that package permitted, there will be a need to assemble an additional heat sink, or
keep ambient temperature around the chip low, or increase load resistance, or decrease power supply voltage.
Here is an example. Assuming VDD=5.0V, RL=4Ω, stereo in BTL mode,
2VDD
2 52
PDBTLMAX 2
1.266 W
R L 3.14 2 4
2
Per channel, total power dissipation PDTOTAL=2* PDBTLMAX=2.53W. According to formula 6, maximum ambient temperature is,
TA TJMAX JA PDBTLMAX 150 50 * 2.53 23.5o C
That is to say, if user wants AA4003 to delivery 2W power per channel to 4Ω load at VDD=5.0V, BTL mode, ambient temperature has to hold lower
than +23.5oC. When junction temperature exceeds about +170oC, OTSD feature will be enabled, and shut down the device to limit total power
dissipation.
There is an exposed thermal pad on bottom of the chip to provide the direct thermal path from die to heat sink. It is recommended to use copper
on the surface of Printed Circuit Board as heat sink. To dig some matrix regular holes under chip, remove mask of this area copper, and make
sure to keep them contact well when soldering on PCB are also recommended. (See Figure 3)
Recommended PCB Layout for AA4003
Using wide traces for power supply to reduce power losses caused by parasitic resistance in all outputs is useful to help releasing heat away from
the chip. It is recommended to place bypass capacitor, power supply bypass capacitors as close as possible to the chip. Figure 3 and Figure 4
show the recommended layout for double layer PCB.
AA4003
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AA4003
Application Information (Cont.)
Figure 3. Copper and Holes under Part
Figure 4. Top Route and Silk Screens
AA4003
Document number: DS36881 Rev. 2 - 2
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AA4003
Ordering Information
AA4003 X XX - XX
Product Name
Package
Packing
E1/G1
G : TSSOP-20(EDP)
M : SOIC-16
TR : Tape & Reel
Blank : Tube
E1 : Lead Free
G1 : Green
Diodes IC's Pb-free products, as designated with "E1" suffix in the part number, are RoHS compliant.
Products with "G1" suffix are available in green packages.
Package
TSSOP-20(EDP)
SOIC-16
Temperature
Range
Part Number
Marking ID
Packing
Lead Free
Green
Lead Free
Green
AA4003G-E1
AA4003G-G1
AA4003G
AA4003GG
Tube
AA4003GTR-E1
AA4003GTR-G1
AA4003G
AA4003GG
Tape & Reel
AA4003M-E1
AA4003M-G1
AA4003M-E1
AA4003M-G1
Tube
AA4003MTR-E1
AA4003MTR-G1
AA4003M-E1
AA4003M-G1
Tape & Reel
-40 to +85°C
-40 to +85°C
AA4003
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Package Outline Dimensions (All dimensions in mm(inch).)
(1)
Package Type: TSSOP-20(EDP)
6.400(0.252)
6.600(0.260)
4.100(0.161)
4.300(0.169)
2.900(0.114)
3.100(0.122)
6.200(0.244)
6.600(0.260)
EXPOSED PAD
4.300(0.169)
4.500(0.177)
#1 PIN
0.000(0.000)
0.750(0.030)
INDEXФ 0.850(0.033) Dp 0.100(0.004)
0.100(0.004)
0.190(0.007)
0.650(0.026)TYP
0.800(0.031)
1.050(0.041)
0.340(0.013)
0.540(0.021)
4-10°
14°
TOP & BOTTOM
0.200(0.008)MIN
R0.090(0.004)MIN
1.200(0.047)
MAX
0.050(0.002) R0.090(0.004)MIN
0.150(0.006)
0.250(0.010)TYP
0°
8°
0.200(0.008)
0.280(0.011)
0.450(0.018)
0.750(0.030)
1.000(0.039)
REF
Note: Eject hole, oriented hole and mold mark is optional.
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Document number: DS36881 Rev. 2 - 2
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Package Outline Dimensions (Cont. All dimensions in mm(inch).)
(2)
Package Type: SOIC-16
D
D1
7°
0.310(0. 012)
0.510(0. 020)
7°
B
A
20:1
0.250(0.010)
0.400(0. 016)
1.270(0.050)
BSC
9.800(0.386)
10.200(0.402)
1.270(0. 050)
0°
8°
R 0.070(0. 003)
0.200(0. 008)
R 0.070(0. 003)
0.200(0. 008)
B
20:1
8°
C
3°
7°
0.200(0. 008)
Sφ1.000(0. 039)
Depth 0.200(0.008)
8°
A
0.150(0.006)
×45 °
0.400(0.016)
8°
C-C
50:1
1.000(0.039)
0.170(0.007)
0.250(0.010)
3.800(0. 150)
4.040(0. 159)
9.5
°
0.200(0.008)
0.250(0.010)
0.050(0.002)
0.250(0.010)
5.800(0. 228)
6.240(0. 246)
C
Note: Eject hole, oriented hole and mold mark is optional.
D
Symbol
D1
min(mm) max(mm) min(inch) max(inch) min(mm) max(mm) min(inch) max(inch)
Option1
1.350
1.750
0.053
0.069
1.250
Option2
-
1.260
-
0.050
1.020
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.
1.650
0.049
0.065
-
0.040
-
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AA4003
Suggested Pad Layout
(1)
Package Type: TSSOP-20(EDP)
X1
G
Y1
Z
Y
E
X
Dimensions
Z
(mm)/(inch)
G
(mm)/(inch)
X
(mm)/(inch)
Y
(mm)/(inch)
E
(mm)/(inch)
X1
(mm)/(inch)
Y1
(mm)/(inch)
Value
7.720/0.304
4.160/0.164
0.420/0.017
1.780/0.070
0.650/0.026
4.500/0.177
3.300/0.130
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Suggested Pad Layout (Cont.)
(2)
Package Type: SOIC-16
Z
G
Y
X
E
Dimensions
Z
(mm)/(inch)
G
(mm)/(inch)
X
(mm)/(inch)
Y
(mm)/(inch)
E
(mm)/(inch)
Value
6.900/0.272
3.900/0.154
0.650/0.026
1.500/0.059
1.270/0.050
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IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
(AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes
without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the
application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or
trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume
all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated
website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and
hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings
noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the
final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express
written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the
labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any
use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related
information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its
representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2012, Diodes Incorporated
www.diodes.com
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