AP2302

Preliminary Datasheet 3A DDR TERMINATION REGULATOR General Description The AP2302 linear regulator is designed to meet the JEDEC specification SSTL-2 and SSTL-18 for termination of DDR-SDRAM. The regulator can sink or source up to 3A current continuously, offers enough current for most DDR applications. Output voltage is designed to track the reference voltage within a 2% (DDR I) and 3% (DDR II) tolerance for load regulation while preventing shooting through on the output stage. On-chip thermal limiting provides protection against a combination of high current and ambient temperature which would create an excessive junction temperature. The AP2302, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The AP2302 is available in SOIC-8, TO-252-5L and TO-263-5L packages. AP2302 Features · · · · · Support Both DDR I (1.25VTT) and DDR II (0.9VTT) Requirements Source and Sink Current up to 3A High Accuracy Output Voltage at Full-load Adjustable VOUT by External Resistors Shutdown for Standby or Suspend Operation with High-impedance Output Mode Applications · · · DDR-SDRAM Termination DDR-II Termination SSTL-2 Termination SOIC-8 TO-252-5L TO-263-5L Figure 1. Package Types of AP2302 Jul. 2006 Rev. 1. 2 1 BCD Semiconductor Manufacturing Limited Preliminary Datasheet 3A DDR TERMINATION REGULATOR Pin Configuration M Package (SOIC-8) VIN GND REFEN VOUT 1 2 3 4 8 7 6 5 VCNTL VCNTL VCNTL VCNTL AP2302 D Package (TO-252-5L) 5 4 3 2 1 VOUT REFEN VCNTL (TAB) GND VIN S5 Package (TO-263-5L) 5 4 3 2 1 VOUT REFEN VCNTL (TAB) GND VIN Figure 2. Pin Configuration of AP2302 (Top View) Pin Description Pin Number SOIC-8 1 2 3 4 5, 6, 7, 8 TO-252-5L 1 2 4 5 3 TO-263-5L 1 2 4 5 3 Pin Name VIN GND REFEN VOUT VCNTL Power Input Ground Reference Voltage Input and Chip Enable Output Voltage Supply Voltage for Internal Circuit (Internally Connected for SOIC8), (TAB for TO-252-5L and TO-263-5L) Function Jul. 2006 Rev. 1. 2 2 BCD Semiconductor Manufacturing Limited Preliminary Datasheet 3A DDR TERMINATION REGULATOR Functional Block Diagram VCNTL 3 (5, 6, 7, 8) AP2302 VIN 1 CURRENT LIMIT BANDGAP A(B) A for 5-pin B for 8-pin OUTPUT CONTROL REFEN 4 (3) 5 (4) VOUT START UP THERMAL PROTECT 2 GND Figure 3. Functional Block Diagram of AP2302 Ordering Information AP2302 Circuit Type Package M: SOIC-8 D: TO-252-5L S5: TO-263-5L Temperature Range Part Number Tin Lead AP2302M SOIC-8 0 to 125oC AP2302MTR TO-2525L TO-2635L AP2302D 0 to 125oC AP2302DTR AP2302S5 0 to 125oC AP2302S5TR AP2302S5TR-E1 AP2302S5 AP2302S5-E1 AP2302DTR-E1 AP2302S5-E1 AP2302D AP2302S5 AP2302D-E1 AP2302S5-E1 AP2302MTR-E1 AP2302D-E1 2302M AP2302D 2302M-E1 AP2302D-E1 Lead Free AP2302M-E1 E1: Lead Free Blank: Tin Lead TR: Tape and Reel Blank: Tube Marking ID Packing Type Tin Lead 2302M Lead Free 2302M-E1 Tube Tape ＆ Reel Tube Tape ＆ Reel Tube Tape ＆ Reel Package BCD Semiconductor's Pb-free products, as designated with "E1" suffix in the part number, are RoHS compliant. Jul. 2006 Rev. 1. 2 3 BCD Semiconductor Manufacturing Limited Preliminary Datasheet 3A DDR TERMINATION REGULATOR Absolute Maximum Ratings (Note 1) Parameter Supply Voltage for Internal Circuit Power Dissipation ESD (Human Body Model) Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10sec) Symbol VCNTL PD ESD TJ TSTG TLEAD SOIC-8 Package Thermal Resistance (Free Air) θJA TO-252-5L TO-263-5L Value 7 Internally Limited 2 150 -65 to 150 260 160 130 90 oC/W AP2302 Unit V W KV oC oC oC Note 1: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to "Absolute Maximum Ratings" for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply Voltage for Internal Circuit DDR I Power Input DDR II Junction Temperature TJ 0 VIN 1.6 1.8 125 oC Symbol VCNTL (Note 2, 3)　 Min Typ 3.3 2.5 Max 6 VCNTL Unit V V Note 2: Keep VCNTL ≥ VIN in power on and power off sequences. Note 3: For safe operation, VCNTL MUST be tied to 3.3V rather than 5V. Jul. 2006 Rev. 1. 2 4 BCD Semiconductor Manufacturing Limited Preliminary Datasheet 3A DDR TERMINATION REGULATOR Electrical Characteristics (TJ=25oC, VIN=2.5V, VCNTL=3.3V, VREFEN=1.25V, COUT=10µF (Ceramic), unless otherwise specified.) Parameter Output Offset Voltage DDR I Load Regulation DDR II Quiescent Current of VCNTL Leakage Current in Shutdown Mode Protection Current Limit Thermal Shutdown Temperature Thermal Shutdown Hysteresis Shutdown Function Shutdown Threshold Trigger Output=High Output=Low Note 4: VOS is the voltage measurement defined as VOUT subtracted from VREFEN. 0.8 0.2 V ILIMIT TSHDN 3.3V≤VCNTL≤5V 3 150 50 A oC oC AP2302 Symbol VOS Conditions IL=0A (Note 4) IL=0 to 1.5A IL=0 to -1.5A IL=0 to 1.5A IL=0 to -1.5A No Load VREFEN