TPS7A84
SBVS233B – JANUARY 2016 – REVISED JUNE 2021
TPS7A84 High-Current (3 A), High-Accuracy (1%),
Low-Noise (4.4 µVRMS), LDO Voltage Regulator
1 Features
3 Description
•
•
The TPS7A84 is a low-noise (4.4 µVRMS), low-dropout
linear regulator (LDO) capable of sourcing 3 A with
only 180 mV of maximum dropout. The device output
voltage is pin-programmable from 0.8 V to 3.95 V
and adjustable from 0.8 V to 5.0 V using an external
resistor divider.
•
•
•
•
•
•
•
•
•
•
Low dropout: 180 mV (max) at 3 A
1% (max) accuracy over line, load, and
temperature
Output voltage noise:
– 4.4 µVRMS at 0.8-V output
– 7.7 µVRMS at 5.0-V output
Input voltage range:
– Without BIAS: 1.4 V to 6.5 V
– With BIAS: 1.1 V to 6.5 V
ANY-OUT™ operation:
– Output voltage range: 0.8 V to 3.95 V
Adjustable operation:
– Output voltage range: 0.8 V to 5.0 V
Power-supply ripple rejection:
– 40 dB at 500 kHz
Excellent load transient response
Adjustable soft-start in-rush control
Open-drain power-good (PG) output
Stable with a 47-µF or larger ceramic output
capacitor
3.5-mm × 3.5-mm, 20-pin VQFN
2 Applications
•
•
•
•
•
•
Macro remote radio units (RRU)
Outdoor backhaul units
Active antenna system mMIMO (AAS)
Ultrasound scanners
Lab and field instrumentation
Sensor, imaging, and radar
The combination of low-noise (4.4 µVRMS), high
PSRR, and high output current capability makes the
TPS7A84 ideal to power noise-sensitive components
such as those found in high-speed communications,
video, medical, or test and measurement applications.
The high performance of the TPS7A84 limits
power-supply-generated phase noise and clock
jitter, making this device ideal for powering highperformance serializer and deserializer (SerDes),
analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), and RF components. Specifically,
RF amplifiers benefit from the high-performance and
5.0-V output capability of the device.
For digital loads [such as application-specific
integrated circuits (ASICs), field-programmable gate
arrays (FPGAs), and digital signal processors (DSPs)]
requiring low-input voltage, low-output (LILO) voltage
operation, the exceptional accuracy (0.75% over
load and temperature), remote sensing, excellent
transient performance, and soft-start capabilities of
the TPS7A84 ensure optimal system performance.
The versatility of the TPS7A84 makes the device
a component of choice for many demanding
applications.
Bias Supply
Device Information(1)
PART NUMBER
BIAS
Input Supply
TPS7A84
PACKAGE
VQFN (20)
BODY SIZE (nom)
3.50 mm × 3.50 mm
IN
TPS7A84
EN Signal
EN
OUT
(1)
PG
For all available packages, see the orderable addendum at
the end of the data sheet.
TPS7A84
VDD
GPIO
DSP,
ASIC,
FPGA
C6000
Powering Digital Loads
Input Supply
OUT
IN
PG
VCC
VCC
IQ Modulators
IQ Demodulators
TRF372017
TRF3722
TRF371125
TRF371135
EN
Powering RF Components
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A84
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SBVS233B – JANUARY 2016 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configurations and Functions.................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................ 8
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 16
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................18
8 Application and Implementation.................................. 19
8.1 Application Information............................................. 19
8.2 Typical Applications.................................................. 34
9 Power Supply Recommendations................................37
10 Layout...........................................................................38
10.1 Layout Guidelines................................................... 38
10.2 Layout Example...................................................... 38
11 Device and Documentation Support..........................39
11.1 Device Support........................................................39
11.2 Documentation Support.......................................... 39
11.3 Receiving Notification of Documentation Updates.. 39
11.4 Support Resources................................................. 39
11.5 Trademarks............................................................. 39
11.6 Electrostatic Discharge Caution.............................. 40
11.7 Glossary.................................................................. 40
12 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (January 2016) to Revision B (June 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document .................1
• Added links to Applications section.................................................................................................................... 1
• Changed title of Figure 8.................................................................................................................................... 8
• Added RMS noise BW condition to Figure 9 through Figure 12......................................................................... 8
• Changed conditions of Figure 13 and Figure 14.................................................................................................8
• Changed the Bias Rail section for clarification ................................................................................................ 17
• Changed Programmable Soft-Start section for clarification..............................................................................17
• Added last paragraph to Internal Current Limit section.................................................................................... 17
• Moved Soft-Start and In-Rush Current section.................................................................................................20
• Added Charge Pump Noise section..................................................................................................................21
• Changed equation 4: changed VREF to VNR/SS ................................................................................................ 22
• Added Current Sharing section.........................................................................................................................25
• Changed Table 5 ..............................................................................................................................................25
• Changed Figure 47 .......................................................................................................................................... 26
• Added RPJ to Figure 48.................................................................................................................................... 27
• Changed Undervoltage Lockout (UVLO) Operation section.............................................................................28
• Changed Behavior when Transitioning from Dropout into Regulation section..................................................29
• Changed Load Transient Response section.....................................................................................................29
• Changed title ofNegatively-Biased Output section........................................................................................... 30
• Added Reverse Current Protection section...................................................................................................... 30
• Changed equation 9 from PD = (VOUT – VIN) × IOUT to PD = (VIN – VOUT) × IOUT .............................................31
• Added equation 11............................................................................................................................................31
• Added Recommended Area for Continuous Operation section........................................................................32
• Changed Table 8 ..............................................................................................................................................39
Changes from Revision * (January 2016) to Revision A (January 2016)
Page
• Released to production ......................................................................................................................................1
2
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OUT
OUT
GND
IN
IN
20
19
18
17
16
5 Pin Configurations and Functions
OUT
1
15
IN
SNS
2
14
EN
FB
3
13
NR/SS
PG
4
12
BIAS
50mV
5
11
1.6V
6
7
8
9
10
100mV
200mV
GND
400mV
800mV
Thermal Pad
Figure 5-1. RGR Package, 3.5-mm × 3.5-mm, 20-Pin VQFN, Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
50mV
5
100mV
6
200mV
7
400mV
9
800mV
10
1.6V
11
I/O
DESCRIPTION
I
ANY-OUT voltage setting pins. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground
increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network
but decreases the range of the network; multiple pins can be simultaneously connected to GND or SNS to select the
desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output
Voltage section for additional details.
BIAS
12
I
BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2
V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance
for VIN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be
left floating or tied to ground.
EN
14
I
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable
functionality is not required, this pin must be connected to IN. If enable functionality is required, VEN must always be high
after VIN is established when a BIAS supply is used. See the Sequencing Requirements section for more details.
FB
3
I
Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT
(as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor
can disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation
sections for more details.
GND
8, 18
—
IN
15-17
I
13
—
Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference
voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended
to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. See the NoiseReduction and Soft-Start Capacitor (CNR/SS) section for more details.
1, 19, 20
O
Regulated output pin. A 47-μF or larger ceramic capacitor (25 μF or greater of capacitance) from OUT to ground is
required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to
the load. See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
PG
4
O
Active-high, power-good pin. An open-drain output indicates when the output voltage reaches 89.3% of the target. The
use of a feed-forward capacitor can disrupt PG (power good) functionality. See the Power-Good Function section for
more details.
SNS
2
I
Output voltage sense input pin. This pin connects the internal R1 resistor to the output. Connect this pin to the load side
of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See
the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details.
NR/SS
OUT
Thermal pad
—
Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection.
Input supply voltage pin. A 47-μF or larger ceramic capacitor (25 μF or greater of capacitance) from IN to ground is
recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible.
See the Input and Output Capacitor Requirements (CIN and COUT) section for more details.
Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over junction temperature range (unless otherwise noted)(1)
Voltage
7.0
IN, BIAS, PG, EN (5% duty cycle, pulse duration = 200 µs)
–0.3
7.5
SNS, OUT
–0.3
VIN + 0.3(2)
NR/SS, FB
–0.3
3.6
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V
–0.3
VOUT + 0.3
UNIT
Internally limited
PG (sink current into device)
Temperature
(2)
MAX
–0.3
OUT
Current
(1)
MIN
IN, BIAS, PG, EN
A
5
Operating junction, TJ
–55
150
Storage, Tstg
–55
150
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The absolute maximum rating is VIN + 0.3 V or 7.0 V, whichever is smaller.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±2000
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over junction temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input supply voltage range
1.1
6.5
V
VBIAS
Bias supply voltage range(1)
3.0
6.5
V
0.8
5
V
0
VIN
V
range(2)
VOUT
Output voltage
VEN
Enable voltage range
IOUT
Output current
0
CIN
Input capacitor
10
47
COUT
Output capacitor
47
47 || 10 || 10(3)
RPG
Power-good pullup resistance
10
CNR/SS
NR/SS capacitor
10
nF
CFF
Feed-forward capacitor
10
nF
R1
Top resistor value in feedback network for
adjustable operation
12.1(4)
kΩ
R2
Bottom resistor value in feedback network for
adjustable operation
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
3
A
µF
µF
100
kΩ
160(5)
kΩ
125
°C
–40
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
This output voltage range does not include device accuracy or accuracy of the feedback resistors.
The recommended output capacitors are selected to optimize PSRR for the frequency range of 400 kHz to 700 kHz. This frequency
range is a typical value for dc-dc supplies.
The 12.1-kΩ resistor is selected to optimize PSRR and noise by matching the internal R1 value.
The upper limit for the R2 resistor is to ensure accuracy by making the current through the feedback network much larger than the
leakage current into the feedback node.
6.4 Thermal Information
TPS7A84
THERMAL METRIC(1)
RGR (VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
35.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
47.6
°C/W
RθJB
Junction-to-board thermal resistance
12.3
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
12.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.0
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V(2), OUT connected to 50 Ω to GND(3), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF,
CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
Input supply voltage range(1)
VIN
range(1)
MIN
TYP
1.1
VBIAS
Bias supply voltage
VFB
Feedback voltage
0.8
VNR/SS
NR/SS pin voltage
0.8
VUVLO1(IN)
Input supply UVLO with BIAS
VIN rising with VBIAS = 3.0 V
1.02
VHYS1(IN)
VUVLO1(IN) hysteresis
VBIAS = 3.0 V
320
VUVLO2(IN)
Input supply UVLO without BIAS
VIN rising
1.31
VHYS2(IN)
VUVLO2(IN) hysteresis
VUVLO(BIAS)
Bias supply UVLO
VBIAS rising, VIN = 1.1 V
2.83
VHYS(BIAS)
VUVLO(BIAS) hysteresis
VIN = 1.1 V
290
Output voltage
ΔVOUT/
ΔVIN
ΔVOUT/
ΔIOUT
VDO
3.0
Using the ANY-OUT pins
Using external
resistors(4)
Accuracy(4) (5)
0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 3 A, over VIN
Accuracy with
BIAS
VIN = 1.1 V, 5 mA ≤ IOUT ≤ 3 A,
3.0 V ≤ VBIAS ≤ 6.5 V
Line regulation
6.5
V
V
V
1.085
1.39
Load regulation
Dropout voltage
2.9
–1.0%
1.0%
–0.75%
0.75%
0.0035
5 mA ≤ IOUT ≤ 3 A
0.08
mV/A
0.4
VIN = 1.4 V, IOUT = 3 A, VFB = 0.8 V – 3%
156
250
VIN = 5.4 V, IOUT = 3 A, VFB = 0.8 V – 3%
220
340
VIN = 1.1 V, VBIAS = 5.0 V,
IOUT = 3 A, VFB = 0.8 V – 3%
110
180
4.2
4.7
ILIM
Output current limit
VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V
ISC
Short-circuit current limit
RLOAD = 20 mΩ
1.0
VIN = 6.5 V, IOUT = 5 mA
2.8
4
VIN = 1.4 V, IOUT = 3 A
4.2
5.5
IGND
GND pin current
IEN
EN pin current
VIN = 6.5 V, VEN = 0 V and 6.5 V
IBIAS
BIAS pin current
VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 3 A
VIL(EN)
EN pin low-level input voltage
(disable device)
VIH(EN)
EN pin high-level input voltage
(enable device)
VIT(PG)
PG pin threshold
For falling VOUT
VHYS(PG)
PG pin hysteresis
For rising VOUT
VOL(PG)
PG pin low-level output voltage
VOUT < VIT(PG), IPG = –1 mA
(current into device)
Ilkg(PG)
PG pin leakage current
VOUT > VIT(PG), VPG = 6.5 V
INR/SS
NR/SS pin charging current
VNR/SS = GND, VIN = 6.5 V
IFB
FB pin leakage current
VIN = 6.5 V
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V
mV/V
5 mA ≤ IOUT ≤ 3 A, VOUT = 5.0 V
3.7
V
mV
5.0 + 1.0%
0.07
V
mV
0.8 – 1.0%
5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V,
VIN = 1.1 V
V
mV
3.95 + 1.0%
Shutdown, PG = open, VIN = 6.5 V, VEN = 0.5 V
6
V
0.8 – 1.0%
IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V
UNIT
6.5
253
Range
VOUT
VIN = 1.1 V
MAX
mV
A
A
mA
25
µA
0.1
µA
3.5
mA
0
0.5
V
1.1
6.5
V
82% × VOUT
88.3% ×
93% × VOUT
VOUT
V
–0.1
2.3
1% × VOUT
4.0
–100
6.2
V
0.4
V
1
µA
9.0
µA
100
nA
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6.5 Electrical Characteristics (continued)
over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.4 V (whichever is
greater), VBIAS = open, VOUT(nom) = 0.8 V(2), OUT connected to 50 Ω to GND(3), VEN = 1.1 V, CIN = 10 μF, COUT = 47 μF,
CNR/SS without CFF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER
PSRR
Vn
Power-supply ripple rejection
Output noise voltage
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
(1)
(2)
(3)
(4)
(5)
TEST CONDITIONS
VIN – VO UT = 0.4 V,
IOUT = 3 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT =
47 μF || 10 μF || 10 μF
MIN
TYP
f = 10 kHz,
VOUT = 0.8 V,
VBIAS = 5.0 V
42
f = 500 kHz, VOUT
= 0.8 V, VBIAS =
5.0 V
39
f = 10 kHz,
VOUT = 5.0 V
40
f = 500 kHz, VOUT
= 5.0 V
25
BW = 10 Hz to 100 kHz, VIN = 1.1 V,
VOUT = 0.8 V, VBIAS = 5.0 V, IOUT = 3 A,
CNR/SS = 100 nF, CFF = 10 nF,
COUT = 47 μF || 10 μF || 10 μF
4.4
BW = 10 Hz to 100 kHz,
VOUT = 5.0 V, IOUT = 3 A, CNR/SS = 100 nF,
CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF
7.7
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
MAX
UNIT
dB
μVRMS
–40
°C
125
°C
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is required when the VIN supply is higher than
or equal to 1.4 V. A BIAS supply helps improve dc and ac performance for VIN ≤ 2.2 V.
VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the
expected VOUT value set by the external feedback resistors.
This 50-Ω load is disconnected when the test conditions specify an IOUT value.
When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
The device is not tested under conditions where VIN > VOUT + 1.7 V and IOUT = 3 A, because the power dissipation is higher than the
maximum rating of the package.
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6.6 Typical Characteristics
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
100
IOUT = 0.1 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 2.5 A
IOUT = 3.0 A
80
60
40
20
0
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
Power Supply-Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
60
40
20
1x106
1x107
80
60
40
20
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
Power-Supply Rejection Ratio (dB)
100
VBIAS = 0 V
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
0
1x101
80
60
40
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
1x107
IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF
Figure 6-3. PSRR vs Frequency and VBIAS
Figure 6-4. PSRR vs Frequency and VIN
100
60
40
20
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
1x107
VIN = VOUT + 0.3 V, VBIAS = 5.0 V, IOUT = 3 A, COUT = 47 μF ||
10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 6-5. PSRR vs Frequency and VOUT With Bias
Power-Supply Rejection Ratio (dB)
100
VOUT = 0.8 V
VOUT = 0.9 V
VOUT = 1.1 V
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 2.5 V
80
0
1x101
VIN = 1.1 V, VBIAS = 5 V
VIN = 1.2 V, VBIAS = 5 V
VIN = 1.4 V, VBIAS = 0 V
VIN = 2.5 V, VBIAS = 0 V
VIN = 5.0 V, VBIAS = 0 V
20
0
1x101
1x107
VIN = 1.4 V, IOUT = 1 A, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, CFF = 10 nF
Power-Supply Rejection Ratio (dB)
1x103
1x104
1x105
Frequency (Hz)
Figure 6-2. PSRR vs Frequency and VIN With Bias
100
8
1x102
IOUT = 3 A, VBIAS = 5 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, CFF = 10 nF
Figure 6-1. PSRR vs Frequency and IOUT
Power-Supply Rejection Ratio (dB)
80
0
1x101
1x107
VIN = 1.1 V, VBIAS = 5 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, CFF = 10 nF
VIN = 1.10 V
VIN = 1.15 V
VIN = 1.20 V
VIN = 1.25 V
VIN = 1.30 V
VIN = 1.35 V
VIN = 1.40 V
VIN = 3.60 V
VIN = 3.65 V
VIN = 3.70 V
VIN = 3.75 V
VIN = 3.80 V
VIN = 3.85 V
VIN = 3.90 V
80
60
40
20
0
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
1x107
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF
Figure 6-6. PSRR vs Frequency and VIN for VOUT = 3.3 V
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
100
COUT = 47||10||10 PF
COUT = 47 PF
COUT = 100 PF
COUT = 200 PF
COUT = 500 PF
80
60
40
20
0
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
60
40
20
0.5
Noise (PV/—Hz)
Output Voltage Noise (PVRMS)
1x107
VOUT = 5.0 V, 11.7 PVRMS
VOUT = 3.3 V, 8.3 PVRMS
VOUT = 1.5 V, 5.4 PVRMS
VOUT = 0.8 V, 4.5 PVRMS
1
9
8
7
6
0.2
0.1
0.05
0.02
0.01
0.005
5
0.002
1.2
1.8
2.4
3
3.6
Output Voltage (V)
4.2
4.8
0.001
1x101
5.4
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 6-9. Output Voltage Noise vs Output Voltage
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106 5x106
VIN = VOUT + 0.3 V and VBIAS = 5 V for VOUT ≤ 2.2 V,
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF
= 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 6-10. Output Noise vs Frequency and Output Voltage
2
2
0.5
0.2
0.1
0.05
0.02
0.01
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.005
0.002
0.002
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106 4x106
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF,
CFF = 10 nF, RMS noise BW = 10 Hz to 100 kHz
Figure 6-11. Output Noise vs Frequency and Input Voltage
CNR/SS = 0 nF, 6.2 PVRMS
CNR/SS = 1 nF, 4.9 PVRMS
CNR/SS = 10 nF, 4.4 PVRMS
CNR/SS = 100 nF, 4.35 PVRMS
1
Noise (PV/—Hz)
VIN = 1.4 V, VBIAS = 5.0 V, 4.5 PVRMS
VIN = 1.4 V, 6.0 PVRMS
VIN = 1.5 V, 4.5 PVRMS
VIN = 1.8 V, 4.5 PVRMS
VIN = 2.5 V, 4.6 PVRMS
VIN = 5.0 V, 5.15 PVRMS
1
0.001
1x101
1x106
2
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 3.0 A
10
4
0.6
1x103
1x104
1x105
Frequency (Hz)
Figure 6-8. VBIAS PSRR vs Frequency
12
Noise (PV/—Hz)
1x102
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 3 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = 10 nF, CFF = 10 nF
Figure 6-7. PSRR vs Frequency and COUT
11
VBIAS = 3.0 V
VBIAS = 5.0 V
VBIAS = 6.5 V
0
1x101
1x107
VIN = VOUT + 0.3 V, VOUT = 1 V, IOUT = 3 A, CNR/SS = 10 nF,
CFF = 10 nF
80
0.001
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
1x106 4x106
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 3 A, COUT = 47 μF ||
10 μF || 10 μF, CFF = 10 nF, RMS noise BW = 10 Hz to
100 kHz
Figure 6-12. Output Noise vs Frequency and CNR/SS
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
2
2
CFF = 0 nF, 6.2 PVRMS
CFF = 0.1 nF, 5.8 PVRMS
CFF = 1 nF, 4.9 PVRMS
CFF = 10 nF, 4.4 PVRMS
CFF = 100 nF, 4.35 PVRMS
Noise (PV/—Hz)
0.2
0.5
0.1
0.2
0.05
0.02
0.01
0.1
0.05
0.02
0.01
0.005
0.005
0.002
0.002
0.001
1x101
1x102
1x103
1x104
Frequency (Hz)
1x105
0.001
1x101
1x106 4x106
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT = 3 A, sequencing with
a dc/dc converter and PG, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = 10 nF, RMS noise BW = 10 Hz to 100 kHz
50
Output Current
VOUT = 0.9 V
VOUT = 1.1 V
VOUT = 1.2 V
VOUT = 1.8 V
9
8
0.6
0.4
VEN
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
0.2
0
7
Output Current (A)
Voltage (V)
0.8
-0.2
0
5
10
15
20
25
30
Time (ms)
35
40
45
50
30
7
20
6
10
5
0
4
-10
3
-20
2
-30
1
-40
0
-50
1.4
1.6
1.8
2
IOUT, DC = 100 mA, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
Figure 6-17. Load Transient vs Time and VOUT Without Bias
AC-Coupled Output Voltage (mV)
Output Current (A)
40
0.8
1
1.2
Time (ms)
10
5
0
4
-10
3
-20
2
-30
1
-40
0
-50
1.75
0.25
0.5
0.75
1
Time (ms)
1.25
1.5
50
50
Output Current
VOUT = 0.9 V
VOUT = 1.1 V
0.6
20
Figure 6-16. Load Transient vs Time and VOUT With Bias
AC-Coupled Output Voltage (mV)
10
0.4
30
VIN = VOUT + 0.3 V, VBIAS = 5 V, IOUT, DC = 100 mA, slew rate =
1 A/μs, CNR/SS = CFF = 10 nF, COUT = 47 μF || 10 μF || 10 μF
Figure 6-15. Start-Up Waveform vs Time and CNR/SS
0.2
40
6
0
VIN = 1.2 V, VOUT = 0.9 V, VBIAS = 5.0 V, IOUT = 3 A,
COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF
10
1x106 4x106
10
1
0
1x105
Figure 6-14. Output Noise at 5.0-V Output
1.2
8
1x103
1x104
Frequency (Hz)
IOUT = 3 A, COUT = 47 μF || 10 μF || 10 μF, CFF = 10 nF,
RMS noise BW = 10 Hz to 100 kHz
Figure 6-13. Output Noise vs Frequency and CFF
9
1x102
AC-Coupled Output Voltage (mV)
0.5
CNR/SS = 10 nF, 11.7 PVRMS
CNR/SS = 100 nF, 7.7 PVRMS
CFF = CNR/SS = 100 nF, 6.0 PVRMS
1
Noise (PV/—Hz)
1
VOUT, 0.5 A/Ps
VOUT, 1 A/Ps
VOUT, 2 A/Ps
25
0
-25
-50
0
0.4
0.8
1.2
Time (ms)
1.6
2
VOUT = 5 V, IOUT, DC = 100 mA, IOUT = 100 mA to 3 A,
COUT = 47 μF || 10 μF || 10 μF, CNR/SS = CFF = 10 nF
Figure 6-18. Load Transient vs Time and Slew Rate
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
350
-40°C
0°C
25°C
85°C
125°C
VOUT, 100 mA to 3 A
VOUT, 500 mA to 3 A
300
40
Dropout Voltage (mV)
AC-Coupled Output Voltage (mV)
60
20
0
250
200
150
-20
100
-40
0
25
50
75
Time (Ps)
100
125
1
150
2
5
6
IOUT = 3 A, VBIAS = 0 V
VIN = 1.2 V, VBIAS = 5.0 V, COUT = 47 μF || 10 μF || 10 μF,
CNR/SS = CFF = 10 nF, slew rate = 1 A/μs
Figure 6-19. Load Transient vs Time and DC Load (VOUT = 0.9 V)
Figure 6-20. Dropout Voltage vs Input Voltage Without Bias
350
220
-40°C
0°C
25°C
85°C
125°C
-40°C
0°C
25°C
85°C
125°C
200
180
Dropout Voltage (mV)
300
Dropout Voltage (mV)
3
4
Input Voltage (V)
250
200
150
160
140
120
100
80
60
40
20
100
0
1
2
3
4
Input Voltage (V)
5
6
0
0.3
IOUT = 3 A, VBIAS = 6.5 V
0.9
1.2 1.5 1.8 2.1
Output Current (A)
2.4
2.7
3
VIN = 1.4 V, VBIAS = 0 V
Figure 6-21. Dropout Voltage vs Input Voltage With Bias
Figure 6-22. Dropout Voltage vs Output Current Without Bias
160
250
-40°C
0°C
25°C
85°C
125°C
120
-40°C
0°C
25°C
85°C
125°C
225
200
Dropout Voltage (mV)
140
Dropout Voltage (mV)
0.6
100
80
60
40
175
150
125
100
75
50
20
25
0
0
0
0.3
0.6
0.9
1.2 1.5 1.8 2.1
Output Current (A)
2.4
2.7
3
0
VIN = 1.1 V, VBIAS = 3 V
0.3
0.6
0.9
1.2 1.5 1.8 2.1
Output Current (A)
2.4
2.7
3
VIN = 5.5 V
Figure 6-23. Dropout Voltage vs Output Current With Bias
Figure 6-24. Dropout Voltage vs Output Current (High VIN)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
0.2
0.15
-40°C
0°C
25°C
85°C
125°C
0.1
-40°C
0°C
25°C
85°C
125°C
0.1
Change in VOUT (%)
Change in VOUT (%)
0.15
0.05
0
0.05
0
-0.05
-0.05
-0.1
0.5
-0.1
1
1.5
2
2.5
3
3.5
Output Voltage (V)
4
4.5
5
0
0.6
IOUT = 100 mA to 3 A
0
0.02
Change in VOUT (%)
Change in VOUT (%)
0.04
-0.015
-0.03
-40°C
0°C
25°C
85°C
125°C
0
-0.02
-40°C
0°C
25°C
85°C
125°C
-0.04
-0.06
0.6
1.2
1.8
Output Current (A)
2.4
-0.06
3
0
0.6
VIN = 3.8 V
-0.025
0
Change in VOUT (ppm)
Change in VOUT (%)
25
-0.05
-0.075
-40°C
0°C
25°C
85°C
125°C
2
2.5
3 3.5 4 4.5
Input Voltage (V)
5
5.5
VOUT = 0.8 V, VBIAS = 0 V, IOUT = 5 mA
-50
-40°C
0°C
25°C
85°C
125°C
6
6.5
-100
3
3.5
4
4.5
5
Bias Voltage (V)
5.5
6
6.5
VOUT = 0.8 V, VIN = 1.1 V, IOUT = 5 mA
Figure 6-29. Line Regulation Without Bias
12
3
-25
-75
-0.125
1.5
2.4
Figure 6-28. Load Regulation (5-V Output)
0
1
1.2
1.8
Output Current (A)
VIN = 5.5 V
Figure 6-27. Load Regulation (3.3-V Output)
-0.1
3
Figure 6-26. Load Regulation With Bias
0.015
0
2.4
VIN = 1.4 V, VBIAS = 0 V
Figure 6-25. Load Regulation vs Output Voltage
-0.045
1.2
1.8
Output Current (A)
Figure 6-30. Line Regulation Without Bias
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
3.3
0
Ground Pin Current (mA)
Change in VOUT (ppm)
3
-20
-40
-40°C
0°C
25°C
85°C
125°C
-60
5.25
2.7
2.4
2.1
-40°C
0°C
25°C
85°C
125°C
1.8
1.5
5.5
5.75
6
Input Voltage (V)
6.25
6.5
1
2
IOUT = 5 mA
6
7
Figure 6-32. Quiescent Current vs Input Voltage
5
2.4
-40°C
0°C
25°C
85°C
125°C
2
1.6
-40°C
0°C
25°C
85°C
125°C
1.2
Shutdown Current (PA)
4
Bias Pin Current (mA)
4
5
Input Voltage (V)
VBIAS = 0 V, IOUT = 5 mA
Figure 6-31. Line Regulation (5-V Output)
3
2
1
0.8
0
3
3.5
4
4.5
5
Bias Voltage (V)
5.5
6
6.5
1
1.5
2
VIN = 1.1 V, IOUT = 5 mA
2.5
3
3.5 4 4.5
Input Voltage (V)
5
5.5
6
6.5
VBIAS = 0 V
Figure 6-33. Quiescent Current vs Bias Voltage
Figure 6-34. Shutdown Current vs Input Voltage
6
7.5
4
NR/SS Charging Current (PA)
-40°C
0°C
25°C
85°C
125°C
5
Shutdown Current (PA)
3
3
2
1
0
7
6.5
6
5.5
-40°C
0°C
25°C
85°C
125°C
5
4.5
3
3.5
4
4.5
5
Bias Voltage (V)
5.5
6
6.5
1
1.5
VIN = 1.1 V
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
6
6.5
VBIAS = 0 V
Figure 6-35. Shutdown Current vs Bias Voltage
Figure 6-36. INR/SS Current vs Input Voltage
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6.6 Typical Characteristics (continued)
at TA = 25°C, VIN = 1.4 V or VIN = VOUT(NOM) + 0.4 V (whichever is greater), VBIAS = open, VOUT(NOM) = 0.8 V, VEN = 1.1 V,
COUT = 47 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted)
1.4
3
VUVLO(BIAS), Rising
VUVLO(BIAS), Falling
2.9
1
Bias Voltage (V)
Input Voltage (V)
1.2
0.8
0.6
VUVLO2(IN), Rising
VUVLO2(IN), Falling
VUVLO1(IN), Rising
VUVLO1(IN), Falling
0.4
0.2
-40
-20
0
20
40
60
80
Temperature (°C)
2.8
2.7
2.6
100
120
2.5
-60
140
-30
0
30
60
Temperature (°C)
90
120
150
VIN = 1.1 V
Figure 6-37. VIN UVLO vs Temperature
Figure 6-38. VBIAS UVLO vs Temperature
0.85
0.75
0.6
0.75
PG Voltage (V)
Enable Voltage (V)
0.8
-40°C
0°C
25°C
85°C
125°C
0.7
0.65
VIH(EN), VIN = 1.4 V
VIH(EN), VIN = 6.5 V
VIL(EN), VIN = 1.4 V
VIL(EN), VIN = 6.5 V
0.6
0.55
-40
0.45
0.3
0.15
0
-20
0
20
40
60
80
Temperature (°C)
100
120
140
0
0.5
1
1.5
2
PG Current Sink (mA)
2.5
3
VIN = 1.4 V, 6.5 V
Figure 6-39. Enable Threshold vs Temperature
Figure 6-40. PG Voltage vs PG Current Sink
0.4
90.25
-40°C
0°C
25°C
85°C
125°C
PG Threshold (% VOUT(NOM))
PG Voltage (V)
0.32
VIT(PG) Rising, VIN = 1.4 V
VIT(PG) Rising, VIN = 6.5 V
VIT(PG) Falling, VIN = 1.4V
VIT(PG) Falling, VIN = 6.5 V
90
0.24
0.16
0.08
89.75
89.5
89.25
89
88.75
88.5
88.25
88
0
0
0.5
1
1.5
2
PG Current Sink (mA)
2.5
3
87.75
-50
-25
0
25
50
Temperature (°C)
75
100
125
VIN = 6.5 V
Figure 6-41. PG Voltage vs PG Current Sink
14
Figure 6-42. PG Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The TPS7A84 is a high-current (3 A), low-noise (4.4 µVRMS), high accuracy (1%) low-dropout linear voltage
regulator (LDO). These features make the device a robust solution to solve many challenging problems in
generating a clean, accurate power supply.
The TPS7A84 has several features that make the device useful in a variety of applications. As detailed in the
Functional Block Diagram section, these features include:
•
•
•
•
•
•
•
•
•
Low-noise, high-PSRR output
ANY-OUT resistor network
Optional bias rail
Power-good output
Programmable soft-start
Foldback current limit
Enable circuitry
Active discharge
Thermal protection
Overall, these features make the TPS7A84 the component of choice because of its versatility and ability to
generate a supply for most applications.
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7.2 Functional Block Diagram
PSRR
Boost
IN
Current
Limit
OUT
Charge
Pump
BIAS
0.8-V
VREF
Active
Discharge
RNR/SS = 250 k:
+
Error
Amp
±
INR/SS
SNS
NR/SS
200 pF
R1 = 2×R = 12.1 k:
FB
1×R = 6.05 k:
UVLO
Circuits
2×R = 12.1 k:
Internal
Controller
1.6V
800mV
4×R = 24.2 k:
400mV
8×R = 48.4 k:
200mV
16×R = 96.8 k:
100mV
32×R = 193.6 k:
50mV
ANY-OUT Network
Thermal
Shutdown
±
0.893 x VREF
EN
PG
+
GND
For the ANY-OUT network, the ratios between the values are highly accurate as a result of matching, but the actual resistance can vary
significantly from the numbers listed.
7.3 Feature Description
7.3.1 Low-Noise, High-PSRR Output
The TPS7A84 includes a low-noise reference and error amplifier ensuring minimal noise during operation. The
NR/SS capacitor (CNR/SS) and feed-forward capacitor (CFF) are the easiest way to reduce device noise. CNR/SS
filters the noise from the reference and CFF filters the noise from the error amplifier. The noise contribution from
the charge pump is minimal. The overall noise of the system at low output voltages can be reduced by using a
bias rail because this rail provides more headroom for internal circuitry.
The high power-supply rejection ratio (PSRR) of the TPS7A84 ensures minimal coupling of input supply noise to
the output. The PSRR performance is primarily results from a high-bandwidth, high-gain error amplifier and an
innovative circuit to boost the PSRR between 200 kHz and 1 MHz.
The combination of a low noise-floor and high PSRR ensure that the device provides a clean supply to the
application; see the Optimizing Noise and PSRR section for more information on optimizing the noise and PSRR
performance.
7.3.2 Integrated Resistance Network (ANY-OUT)
An internal feedback resistance network is provided, allowing the TPS7A84 output voltage to be programmed
easily between 0.8 V to 3.95 V with a 50-mV step by tying the ANY-OUT pins to ground. Tying the ANY-OUT
pins to SNS increases the resolution but limits the range of the output voltage because the effective value of R1
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is decreased. Use the ANY-OUT network for excellent accuracy across output voltage and temperature; see the
Application and Implementation section for more details.
7.3.3 Bias Rail
The device features a bias rail to enable low-input voltage, low-output (LILO) voltage operation by providing
power to the internal circuitry of the device. The bias rail is required for operation with VIN < 1.4 V.
An internal power MUX supplies the greater of either the input voltage or the bias voltage to an internal charge
pump to power the internal circuitry. Unlike other LDOs that have a bias supply, the TPS7A84 does not have a
minimum bias voltage with respect to the input supply because an internal charge pump is used instead.
The internal charge pump multiples the output voltage of the power MUX by a factor of 4 to a maximum of
typically 8 V; therefore, using a bias supply with VIN ≤ 2.2 V is recommended for optimal dc and ac performance.
Sequencing requirements exist for when the bias rail is used; see the Sequencing Requirements section for
more details.
7.3.4 Power-Good Function
The power-good circuit monitors the voltage at the feedback pin to indicate the status of the output voltage.
When the feedback pin voltage falls below the PG threshold voltage (VIT(PG) + VHYS(PG), typically 89.3%), the
PG pin open-drain output engages and pulls the PG pin close to GND. When the feedback voltage exceeds the
VIT(PG) threshold by an amount greater than VHYS(PG) (typically 91.3%), the PG pin becomes high impedance.
By connecting a pullup resistor to an external supply, any downstream device can receive power-good as a logic
signal that can be used for sequencing. Make sure that the external pullup supply voltage results in a valid logic
signal for the receiving device or devices. Using a pullup resistor from 10 kΩ to 100 kΩ is recommended. Using
an external voltage detector device such as the TPS3702 is also recommended in applications where more
accurate voltage monitoring or overvoltage monitoring is required.
The use of a feed-forward capacitor (CFF) can cause glitches on start-up, and the power-good circuit may
not function normally below the minimum input supply range. For more details on the use of the power-good
circuitry, see the Power-Good Operation section.
7.3.5 Programmable Soft-Start
Soft-start refers to the ramp-up time of the output voltage during LDO turn-on after EN and UVLO exceed the
respective threshold voltages. The noise-reduction capacitor (CNR/SS) serves a dual purpose of both governing
output noise reduction and programming the soft-start ramp time during turn-on. The start-up ramp is monotonic.
The majority of the ramp is linear; however, there is an offset voltage in the error amplifier that can cause a small
initial jump in output voltage; see the Application and Implementation section on implementing a soft-start.
7.3.6 Internal Current Limit (ILIM)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events.
During a current-limit event, the LDO sources constant current; therefore, the output voltage falls with decreased
load impedance. Thermal shutdown can activate during a current limit event because of the high power
dissipation typically found in these conditions. To ensure proper operation of the current limit, minimize the
inductances to the input and load. Continuous operation in current limit is not recommended.
The foldback current limit crosses 0 A when VOUT < 0 V and prevents the device from turning on into a
negatively-biased output. See the Negatively-Biased Output section on additional ways to ensure start-up when
the TPS7A84 output is pulled below ground.
If VOUT > VIN + 0.3 V, then reverse current can flow from the output to the input. The reverse current can cause
damage to the device; therefore, limit this reverse current to 10% of the rated output current of the device. See
the Reverse Current Protection section for more details.
7.3.7 Enable
The enable pin for the TPS7A84 is active high. The output of the TPS7A84 is turned on when the enable pin
voltage is greater than its rising voltage threshold (1.1 V, max), and the output of the TPS7A84 is turned off when
the enable pin voltage is less than its falling voltage threshold (0.5 V, min). A voltage less than 0.5 V on the
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enable pin disables all internal circuits. At the next turn-on this voltage ensures a normal start-up waveform with
in-rush control, provided there is enough time to discharge the output capacitance.
When the enable functionality is not desired, EN must be tied to VIN. However, when the enable functionality
is desired, the enable voltage must come after VIN is above VUVLO1(IN) when a BIAS rail is used. See the
Application and Implementation section for further details.
7.3.8 Active Discharge Circuit
The TPS7A84 has an internal pulldown MOSFET that connects a resistance of several hundred ohms to ground
when the device is disabled to actively discharge the output voltage when the device is disabled.
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.9 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit monitors the input and bias voltage (VIN and VBIAS, respectively) to
prevent the device from turning on before VIN and VBIAS rise above the lockout voltage. The UVLO circuit also
disables the output of the device when VIN or VBIAS fall below the lockout voltage. The UVLO circuit responds
quickly to glitches on VIN or VBIAS and attempts to disable the output of the device if either of these rails collapse.
As a result of the fast response time of the input supply UVLO circuit, fast and short line transients well below the
input supply UVLO falling threshold can cause momentary glitches when asserted or when recovered from the
transient. See the Application and Implementation section for more details.
7.3.10 Thermal Protection
The TPS7A84 contains a thermal shutdown protection circuit to disable the device when thermal junction
temperature (TJ) of the main pass-FET exceeds 160°C (typical). Thermal shutdown hysteresis assures that the
LDO resets again (turns on) when the temperature falls to 140°C (typical). The thermal time-constant of the
semiconductor die is fairly short, and thus the device cycles on and off when thermal shutdown is reached until
the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C can cause
the device to exceed its operational specifications. Although the internal protection circuitry of the TPS7A84
is designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat
sinking. Continuously running the TPS7A84 into thermal shutdown or above a junction temperature of 125°C
reduces long-term reliability.
7.4 Device Functional Modes
7.4.1 Operation with 1.1 V ≤ VIN < 1.4 V
The TPS7A84 requires a bias voltage on the BIAS pin greater than or equal to 3.0 V if the high-current input
supply voltage is between 1.1 V to 1.4 V. The bias voltage pin consumes 2.3 mA, nominally.
7.4.2 Operation with 1.4 V ≤ VIN ≤ 6.5 V
If the input voltage is equal to or exceeds 1.4 V, no BIAS voltage is required. The TPS7A84 is powered
from either the input supply or the BIAS supply, whichever is greater. For higher performance, a BIAS rail is
recommended for VIN ≤ 2.2 V.
7.4.3 Shutdown
Shutting down the device reduces the ground current of the device to a maximum of 25 µA.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS7A84 is a linear voltage regulator with an input range of 1.1 V to 6.5 V and an output voltage range of
0.8 V to 5.0 V with a 1% accuracy and a 3-A maximum output current. The TPS7A84 has an integrated charge
pump for ease of use and an external bias rail to allow for the lowest dropout across the entire output voltage
range.
8.1.1 Recommended Capacitor Types
The TPS7A84 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the
input, output, and noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the industry
standard for these types of applications and are recommended, but must be used with good judgment. Ceramic
capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive
stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations
in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors
recommended herein account for a capacitance derating of approximately 50%, but at high VIN and VOUT
conditions (that is, VIN = 5.5 V to VOUT = 5.0 V) the derating can be greater than 50% and must be taken into
consideration.
8.1.2 Input and Output Capacitor Requirements (CIN and COUT)
The TPS7A84 is designed and characterized for operation with ceramic capacitors of 47 µF or greater (22 μF or
greater of capacitance) at the output and 10 µF or greater (5 μF or greater of capacitance) at the input. Using
at least a 47-µF capacitor is highly recommended at the input to minimize input impedance. Place the input
and output capacitors as near as practical to the respective input and output pins to minimize trace parasitics.
If the trace inductance from the input supply to the TPS7A84 is high, a fast current transient can cause VIN
to ring above the absolute maximum voltage rating and damage the device. This situation can be mitigated by
additional input capacitors to dampen the ringing and to keep it below the device absolute maximum ratings.
A combination of multiple output capacitors boosts the high-frequency PSRR, as illustrated in several of the
PSRR curves. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized,
10-µF ceramic capacitors with a sufficient voltage rating in conjunction with the PSRR boost circuit optimizes
PSRR for the frequency range of 400 kHz to 700 kHz, a typical range for dc-dc supply switching frequency.
This 47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage
configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a
voltage derating of approximately 60% to 80% at 5.0 V, so the addition of the two 10-µF capacitors ensures that
the capacitance is at or above 22 µF.
8.1.3 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
The TPS7A84 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CNR/SS).The use of an external CNR/SS is highly recommended, especially to minimize in-rush
current into the output capacitors. This soft-start eliminates power-up initialization problems when powering
field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled
voltage ramp of the output also reduces peak in-rush current during start-up, minimizing start-up transients to the
input power bus.
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To achieve a monotonic start-up, the TPS7A84 error amplifier tracks the voltage ramp of the external soft-start
capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start
charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS). Soft-start ramp
time can be calculated with Equation 1:
tSS = (VNR/SS × CNR/SS) / INR/SS
(1)
Note that INR/SS is provided in the Electrical Characteristics table and has a typical value of 6.2 µA.
The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that
filters out the noise from the reference before being gained up with the error amplifier, thereby reducing the
device noise floor. The LPF is a single-pole filter and the cutoff frequency can be calculated with Equation 2. The
typical value of RNR is 250 kΩ. Increasing the CNR/SS capacitor has a greater affect because the output voltage
increases when the noise from the reference is gained up even more at higher output voltages. For low-noise
applications, a 10-nF to 1-µF CNR/SS is recommended.
fcutoff = 1/ (2 × π × RNR × CNR/SS)
(2)
8.1.4 Feed-Forward Capacitor (CFF)
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a
10-nF external feed-forward capacitor optimizes the transient, noise, and PSRR performance. A higher
capacitance CFF can be used; however, the start-up time is longer and the power-good signal can incorrectly
indicate that the output voltage is settled. For a detailed description, see the Pros and Cons of Using a
Feed-Forward Capacitor with a Low Dropout Regulator application report.
8.1.5 Soft-Start and In-Rush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO
achieve threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turn-on.
In-rush current is defined as the current into the LDO at the IN pin during start-up. In-rush current then consists
primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult
to measure because the input capacitor must be removed, which is not recommended. However, this soft-start
current can be estimated by Equation 3:
IOUT(t) =
COUT ´ dVOUT(t)
dt
+
VOUT(t)
RLOAD
(3)
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turn-on ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
8.1.6 Optimizing Noise and PSRR
The ultra-low noise floor and PSRR of the device can be improved by careful selection of:
•
•
•
•
•
CNR/SS for the low-frequency range
CFF in the mid-band frequency range
COUT for the high-frequency range
VIN – VOUT for all frequencies, and
VBIAS at lower input voltages
A larger noise-reduction capacitor improves low-frequency PSRR by filtering any noise coupling from the input
into the reference. The feed-forward capacitor can be optimized to place a pole-zero pair near the edge of the
loop bandwidth and push out the loop bandwidth, thus improving mid-band PSRR. Larger output capacitors and
various output capacitors can be used to improve high-frequency PSRR.
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A higher input voltage improves the PSRR by giving the device more headroom to respond to noise on the input;
see the PSRR vs Frequency and VIN With Bias curve. A bias rail also improves the PSRR at lower input voltages
because greater headroom is provided for the internal circuits.
The noise-reduction capacitor filters out low-frequency noise from the reference and the feed-forward capacitor
reduces output voltage noise by filtering out the mid-band frequency noise. However, a large feed-forward
capacitor can create some new issues that are discussed in the Pros and Cons of Using a Feed-Forward
Capacitor with a Low Dropout Regulator application report.
A large output capacitor reduces high-frequency output voltage noise. Additionally, a bias rail or higher input
voltage improves the noise because greater headroom is provided for the internal circuits.
Table 8-1 lists the output voltage noise for the 10-Hz to 100-kHz band at a 5.0-V output for a variety of conditions
with an input voltage of 5.4 V, an R1 of 12.1 kΩ, and a load current of 3 A. The 5.0-V output is chosen because
this output is the worst-case condition for output voltage noise.
Table 8-1. Output Noise Voltage at a 5.0-V Output
OUTPUT VOLTAGE NOISE
(µVRMS)
CNR/SS (nF)
CFF (nF)
COUT (µF)
11.7
10
10
47 || 10 || 10
7.7
100
10
47 || 10 || 10
6
100
100
47 || 10 || 10
7.4
100
10
1000
5.8
100
100
1000
8.1.7 Charge Pump Noise
The device internal charge pump generates a minimal amount of noise, as shown in Figure 8-1.
Using a bias rail minimizes the internal charge pump noise when the internal voltage is clamped, thereby
reducing the overall output noise floor.
The high-frequency components of the output voltage noise density curve are filtered out in most applications by
using 10-nF to 100-nF bypass capacitors close to the load. Using a ferrite bead between the LDO output and the
load input capacitors forms a pi-filter, further reducing the high-frequency noise contribution.
0.5
VIN = 1.5 V, 4.5 PV RMS
VIN = 1.4 V, VBIAS = 5.0 V, 4.5 PV RMS
0.3
0.2
Noise (PV/—Hz)
0.1
0.07
0.05
0.03
0.02
0.01
0.007
0.005
0.003
0.002
0.001
1000000
2000000
3000000
4000000
5000000
6000000
Frequency (Hz)
7000000
8000000
9000000
1E+7
Figure 8-1. Charge Pump Noise
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8.1.8 ANY-OUT Programmable Output Voltage
The TPS7A84 can use either external resistors or the internally-matched ANY-OUT feedback resistor network to
set output voltage. The ANY-OUT resistors are accessible via pin 2 and pins 5 to 11 and are used to program the
regulated output voltage. Each pin is can be connected to ground (active) or left open (floating), or connected to
SNS. ANY-OUT programming is set by Equation 4 as the sum of the internal reference voltage (VNR/SS = 0.8 V)
plus the accumulated sum of the respective voltages assigned to each active pin; that is, 50mV (pin 5), 100mV
(pin 6), 200mV (pin 7), 400mV (pin 9), 800mV (pin 10), or 1.6V (pin 11). Table 8-2 summarizes these voltage
values associated with each active pin setting for reference. By leaving all program pins open or floating, the
output is thereby programmed to the minimum possible output voltage equal to VFB.
VOUT = VNR/SS + (Σ ANY-OUT Pins to Ground)
(4)
Table 8-2. ANY-OUT Programmable Output Voltage
ANY-OUT PROGRAM PINS (Active Low)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)
50 mV
Pin 6 (100mV)
100 mV
Pin 7 (200mV)
200 mV
Pin 9 (400mV)
400 mV
Pin 10 (800mV)
800 mV
Pin 11 (1.6V)
1.6 V
Table 8-3 provides a full list of target output voltages and corresponding pin settings when the ANY-OUT pins
are only tied to ground or left floating. The voltage setting pins have a binary weight; therefore, the output
voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV steps when tying these pins to ground.
There are several alternative ways to set the output voltage. The program pins can be driven using external
general-purpose input/output pins (GPIOs), manually connected using 0-Ω resistors (or left open), or hardwired
by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage. As with the adjustable
operation, the output voltage is set according to Equation 5 except that R1 and R2 are internally integrated and
matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the resolution of the internal
feedback network by lowering the value of R1. See the Increasing ANY-OUT Resolution for LILO Conditions
section for additional information.
VOUT = VNR/SS × (1 + R1 / R2)
(5)
Note
For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the Adjustable
Operation section).
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Table 8-3. User-Configurable Output Voltage Settings
VOUT(NOM)
(V)
50mV
100mV
200mV
400mV
800mV
1.6V
VOUT(NOM)
(V)
50mV
100mV
200mV
400mV
800mV
1.6V
0.80
Open
Open
Open
Open
Open
Open
2.40
Open
Open
Open
Open
Open
GND
0.85
GND
Open
Open
Open
Open
Open
2.45
GND
Open
Open
Open
Open
GND
0.90
Open
GND
Open
Open
Open
Open
2.50
Open
GND
Open
Open
Open
GND
0.95
GND
GND
Open
Open
Open
Open
2.55
GND
GND
Open
Open
Open
GND
1.00
Open
Open
GND
Open
Open
Open
2.60
Open
Open
GND
Open
Open
GND
1.05
GND
Open
GND
Open
Open
Open
2.65
GND
Open
GND
Open
Open
GND
1.10
Open
GND
GND
Open
Open
Open
2.70
Open
GND
GND
Open
Open
GND
1.15
GND
GND
GND
Open
Open
Open
2.75
GND
GND
GND
Open
Open
GND
1.20
Open
Open
Open
GND
Open
Open
2.80
Open
Open
Open
GND
Open
GND
1.25
GND
Open
Open
GND
Open
Open
2.85
GND
Open
Open
GND
Open
GND
1.30
Open
GND
Open
GND
Open
Open
2.90
Open
GND
Open
GND
Open
GND
1.35
GND
GND
Open
GND
Open
Open
2.95
GND
GND
Open
GND
Open
GND
1.40
Open
Open
GND
GND
Open
Open
3.00
Open
Open
GND
GND
Open
GND
1.45
GND
Open
GND
GND
Open
Open
3.05
GND
Open
GND
GND
Open
GND
1.50
Open
GND
GND
GND
Open
Open
3.10
Open
GND
GND
GND
Open
GND
1.55
GND
GND
GND
GND
Open
Open
3.15
GND
GND
GND
GND
Open
GND
1.60
Open
Open
Open
Open
GND
Open
3.20
Open
Open
Open
Open
GND
GND
1.65
GND
Open
Open
Open
GND
Open
3.25
GND
Open
Open
Open
GND
GND
1.70
Open
GND
Open
Open
GND
Open
3.30
Open
GND
Open
Open
GND
GND
1.75
GND
GND
Open
Open
GND
Open
3.35
GND
GND
Open
Open
GND
GND
1.80
Open
Open
GND
Open
GND
Open
3.40
Open
Open
GND
Open
GND
GND
1.85
GND
Open
GND
Open
GND
Open
3.45
GND
Open
GND
Open
GND
GND
1.90
Open
GND
GND
Open
GND
Open
3.50
Open
GND
GND
Open
GND
GND
1.95
GND
GND
GND
Open
GND
Open
3.55
GND
GND
GND
Open
GND
GND
2.00
Open
Open
Open
GND
GND
Open
3.60
Open
Open
Open
GND
GND
GND
2.05
GND
Open
Open
GND
GND
Open
3.65
GND
Open
Open
GND
GND
GND
2.10
Open
GND
Open
GND
GND
Open
3.70
Open
GND
Open
GND
GND
GND
2.15
GND
GND
Open
GND
GND
Open
3.75
GND
GND
Open
GND
GND
GND
2.20
Open
Open
GND
GND
GND
Open
3.80
Open
Open
GND
GND
GND
GND
2.25
GND
Open
GND
GND
GND
Open
3.85
GND
Open
GND
GND
GND
GND
2.30
Open
GND
GND
GND
GND
Open
3.90
Open
GND
GND
GND
GND
GND
2.35
GND
GND
GND
GND
GND
Open
3.95
GND
GND
GND
GND
GND
GND
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8.1.9 ANY-OUT Operation
Considering the use of the ANY-OUT internal network (where the unit resistance of 1R is equal to 6.05 kΩ)
the output voltage is set by grounding the appropriate control pins, as shown in Figure 8-2. When grounded,
all control pins add a specific voltage on top of the internal reference voltage (VNR/SS = 0.8 V). The output
voltage can be calculated by Equation 6 and Equation 7. Figure 8-2 and Figure 8-3 show a 0.9-V output voltage,
respectively, that provide an example of the circuit usage with and without bias voltage.
BIAS
EN
PG
RPG
Input
Supply
IN
OUT
To Load
COUT
CIN
Device
SNS
CFF
NR/SS
FB
CNR/SS
GND
50mV 100mV 200mV 400mV 800mV
1.6V
Figure 8-2. ANY-OUT Configuration Circuit (3.3-V Output, No External Bias)
VOUT(nom) = VNR/SS + 1.6 V + 0.8 V + 0.1 V = 0.8 V + 1.6 V + 0.8 V + 0.1 V = 3.3 V
(6)
CBIAS
Bias
Supply
BIAS
EN
PG
RPG
Input
Supply
IN
OUT
To Load
COUT
CIN
Device
SNS
CFF
NR/SS
FB
CNR/SS
GND
50mV 100mV 200mV 400mV 800mV
1.6V
Figure 8-3. ANY-OUT Configuration Circuit (0.9-V Output with Bias)
VOUT(nom) = VNR/SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V
(7)
8.1.10 Increasing ANY-OUT Resolution for LILO Conditions
As with the adjustable operation, the output voltage is set according to Equation 5, except that R1 and R2 are
internally integrated and matched for higher accuracy. Tying any of the ANY-OUT pins to SNS can increase the
resolution of the internal feedback network by lowering the value of R1. One of the more useful pin combinations
is to tie the 800mV pin to SNS, which reduces the resolution by 50% to 25 mV but limits the range. The new
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ANY-OUT ranges are 0.8 V to 1.175 V and 1.6 V to 1.975 V. The new additive output voltage levels are listed in
Table 8-4.
Table 8-4. ANY-OUT Programmable Output Voltage with 800mV Tied to SNS
ANY-OUT PROGRAM PINS (Active Low)
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50mV)
25 mV
Pin 6 (100mV)
50 mV
Pin 7 (200mV)
100 mV
Pin 9 (400mV)
200 mV
Pin 11 (1.6V)
800 V
8.1.11 Current Sharing
Current sharing is possible through the use of external operational amplifiers. For more details, see the 6A
Current-Sharing Dual LDO design guide.
8.1.12 Adjustable Operation
The TPS7A84 can be used either with the internal ANY-OUT network or by using external resistors. Using the
ANY-OUT network allows the TPS7A84 to be programmed from 0.8 V to 3.95 V. To extend this output voltage
range to 5.0 V, external resistors must be used. This configuration is referred to as the adjustable configuration
of the TPS7A84 throughout this document. Regardless whether the internal resistor network or whether external
resistors are used, the output voltage is set by two resistors, as shown in Figure 8-4. Using the internal resistor
ensures a 1% accuracy and minimizes the number of external components.
Optional Bias
Supply
CBIAS
BIAS
EN
PG
RPG
Input
Supply
IN
OUT
To Load
COUT
CIN
Device
SNS
CFF
NR/SS
R1
FB
CNR/SS
R2
GND
50mV 100mV 200mV 400mV 800mV
1.6V
Figure 8-4. Adjustable Operation
R1 and R2 can be calculated for any output voltage range using Equation 8. This resistive network must provide
a current equal to or greater than 5 μA for dc accuracy. Using an R1 of 12.1 kΩ is recommended to optimize the
noise and PSRR.
VOUT = VNR/SS × (1 + R1 / R2)
(8)
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Table 8-5 shows the resistor combinations required to achieve several common rails using standard 1%tolerance resistors.
Table 8-5. Recommended Feedback-Resistor Values(1)
FEEDBACK RESISTOR VALUES
TARGETED OUTPUT VOLTAGE
(V)
R1 (kΩ)
(1)
R2 (kΩ)
CALCULATED OUTPUT
VOLTAGE
(V)
0.9
12.4
100
0.899
0.95
12.4
66.5
0.949
1.00
12.4
49.9
0.999
1.10
12.4
33.2
1.099
1.20
12.4
24.9
1.198
1.50
12.4
14.3
1.494
1.80
12.4
10
1.798
1.90
12.1
8.87
1.89
2.50
12.4
5.9
2.48
2.85
12.1
4.75
2.838
3.00
12.1
4.42
2.990
3.30
11.8
3.74
3.324
3.60
12.1
3.48
3.582
4.5
11.8
2.55
4.502
5.00
12.4
2.37
4.985
R1 is connected from OUT to FB; R2 is connected from FB to GND.
8.1.13 Sequencing Requirements
Supply and enable sequencing is only required when the bias rail is present. The start-up is always monotonic,
independent of the sequencing requirements. Under these conditions the following requirements apply:
•
VBIAS and VIN can be sequenced in any order, as long as VEN is tied to VIN or established after VIN, as shown
in Figure 8-5.
tt0 • 0t
VIN
VEN
VUVLO1(IN)
VIH(EN)
Figure 8-5. Sequencing Diagram
Two typical application circuits for implementing the sequencing requirements are detailed in the Sequencing
with a Power-Good DC-DC Converter Pin and Sequencing with a Microcontroller (MCU) sections.
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8.1.13.1 Sequencing with a Power-Good DC-DC Converter Pin
When a dc-dc converter is used to power the device and the PG of the dc-dc converter is used to enable the
device, pull PGup to VIN, as shown in Figure 8-6.
From Input Supply
OUT
IN
DC-DC
IN
RPU
BIAS
Device
PG
EN
Figure 8-6. Sequencing with a DC-DC Converter and PG
8.1.13.2 Sequencing with a Microcontroller (MCU)
If a push-pull output stage is used to provide the enable signal to the device and the enable signal can possibly
come before VIN when a bias is present (such as with an MCU), convert the enable signal to an open-drain
signal as shown in Figure 8-7. Using an open-drain signal ensures that if the signal arrives before VIN, then the
enable voltage does not violate the sequencing requirement.
Bias Supply
Input Supply
IN
RPU
BIAS
Device
EN
Enable Signal
MCU
Figure 8-7. Push-Pull Enable to Open-Drain Enable
8.1.14 Power-Good Operation
To ensure proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and
100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor,
and the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup
resistor is outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFF with a small CNR/SS causes the power-good signal to incorrectly indicate that the output
voltage has settled during turn-on. The CFF time constant must be greater than the soft-start time constant to
ensure proper operation of the PG during start-up. For a detailed description, see the Pros and Cons of Using a
Feed-Forward Capacitor with a Low Dropout Regulator application report.
The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO
events and at light loads, power-good does not assert because the output voltage is sustained by the output
capacitance.
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8.1.15 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input or bias supplies reach the minimum
operational voltage range, and ensures that the device shuts down when the input supply or bias supply
collapse.
The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a
downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the
UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device.
When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.
The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall
time of the input supply when operating near the minimum VIN, or by using a bias rail.
Figure 8-8 shows the UVLO circuit response to various input voltage events. The diagram can be separated into
the following parts:
•
•
•
•
•
•
•
Region A: The device does not turn on until the input reaches the UVLO rising threshold.
Region B: Normal operation with a regulated output
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device is still enabled.
Region D: Normal operation with a regulated output
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up then follows.
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 8-8. Typical UVLO Operation
8.1.16 Dropout Voltage (VDO)
Generally speaking, the dropout voltage often refers to the minimum voltage difference between the input and
output voltage (VDO = VIN – VOUT) that is required for regulation. When VIN drops below the required VDO for
the given load current, the device functions as a resistive switch and does not regulate output voltage. Dropout
voltage is proportional to the output current because the device is operating as a resistive switch; see the
Dropout Voltage vs Output Current Without Bias, Dropout Voltage vs Output Current With Bias, and Dropout
Voltage vs Output Current (High VIN) curves.
Dropout voltage is affected by the drive strength for the gate of the pass element, which is nonlinear with respect
to VIN on this device because of the internal charge pump. The charge pump causes a higher dropout voltage at
lower input voltages when a bias rail is not used, as illustrated in the Dropout Voltage vs Input Voltage Without
Bias curve.
For this device, dropout voltage increases exponentially when the input voltage nears its maximum operating
voltage because the charge pump is internally clamped to 8.0 V; see the Dropout Voltage vs Input Voltage
Without Bias and Dropout Voltage vs Input Voltage With Bias curves.
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8.1.17 Behavior when Transitioning from Dropout into Regulation
Some applications may have transients that place the device into dropout, especially because this device is a
high-current linear regulator. A typical application with these conditions requires setting VIN ≤ VDO in order to
keep the device junction temperature within its specified operating range. A load transient or line transient in
these conditions can place the device into dropout, such as a load transient from 1 A to 4 A at 1A/µs when
operating with a VIN of 5.4- V and a VOUT of 5.0 V.
The load transient saturates the error amplifier output stage when the pass element is fully driven on, thus
making the pass element function like a resistor from VIN to VOUT. The error amplifier response time to this load
transient (IOUT = 4 A to 1 A at 1 A/µs) is limited because the error amplifier must first recover from saturation
and then place the pass element back into active mode. During the recovery from the load transient, VOUT
overshoots because the pass element is functioning as a resistor from VIN to VOUT. If operating under these
conditions, apply a higher dc load or increase the output capacitance to reduce the overshoot because these
solutions provide a path to dissipate the excess charge.
8.1.18 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained; see the Load Transient vs Time and VOUT With Bias curve. There are
two key transitions during a load transient response: the transition from a light to a heavy load and the transition
from a heavy to a light load. The regions shown in Figure 8-9 are broken down in this section. Regions A, E, and
H are where the output voltage is in steady-state.
During transitions from a light load to a heavy load, the:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B).
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C).
During transitions from a heavy load to a light load, the:
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F).
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G).
Transitions between current levels changes the internal power dissipation because the TPS7A84 is a highcurrent device (region D). The change in power dissipation changes the die temperature during these transitions,
and leads to a slightly different voltage level. This different output voltage level shows up in the various load
transient responses; see the Load Transient vs Time and VOUT With Bias curve.
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor; see the Load Transient vs Time and Slew Rate curve.
tAt
tCt
B
tDt
tEt
tGt
tHt
F
Figure 8-9. Load Transient Waveform
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8.1.19 Negatively-Biased Output
The device does not start or operate as expected if the output voltage is pulled below ground. This issue
commonly occurs when powering a split-rail system where the negative rail is established before the device is
enabled. Several application solutions are:
•
•
•
Enable the device before the negative regulator and disable the device after the negative regulator.
Delaying the EN voltage with respect to the IN voltage allows the internal pulldown resistor to discharge any
voltage at OUT. If the discharge circuit is not strong enough to keep the output voltage at ground, then use an
external pulldown resistor.
Place a zener diode from IN to OUT to provide a small positive dc bias on the output when the input is
supplied to the device, as shown in Figure 8-10.
IN
VIN
OUT
To Load
COUT
GND
•
Figure 8-10. Zener Diode Placed from IN to OUT
Use a PFET to isolate the output of the device from the load causing the negative bias when the device is off,
as shown in Figure 8-11.
To All Other Loads
IN
VIN
OUT
COUT
To Loads with
Negative Bias
GND
Figure 8-11. PFET to Isolate the Output from the Load
8.1.20 Reverse Current Protection
As with most LDOs, this device can be damaged by excessive reverse current.
Conditions where excessive reverse current can occur are outlined in this section, all of which can exceed the
absolute maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT, then the input supply collapses quickly and the load current becomes very
small
• The output is biased when the input supply is not established
• The output is biased above the input supply
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If an excessive reverse current flow is expected in the application, then external protection must be used to
protect the device. Figure 8-12 shows one approach of protecting the device.
Schottky Diode
IN
CIN
Internal Body Diode
OUT
Device
COUT
GND
Figure 8-12. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.21 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. PD can be calculated using Equation 9:
PD = (VIN – VOUT) × IOUT
(9)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the TPS7A84 allows for maximum efficiency across a wide range of output
voltages.
The primary heat conduction path for the package is through the thermal pad to the PCB. Solder the thermal pad
to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any
inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 10. The equation is rearranged for output current in Equation 11.
TJ = TA + (RθJA × PD)
(10)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
(11)
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of
the planes. The R θJA recorded in the Electrical Characteristics table is determined by the JEDEC standard, PCB,
and copper-spreading area, and is only used as a relative measure of package thermal performance. For a
well-designed thermal layout, RθJA is actually the sum of the VQFN package junction-to-case (bottom) thermal
resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.
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8.1.22 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are given in the Electrical Characteristics table and are used in accordance with Equation 12.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
(12)
where:
•
•
•
PD is the power dissipated as explained in Equation 9
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.23 Recommended Area for Continuous Operation (RACO)
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and
input voltage. The recommended area for continuous operation for a linear regulator can be separated into the
following parts, and is shown in Figure 8-13:
•
•
•
Output Current (A)
•
Limited by dropout: Dropout voltage limits the minimum differential voltage between the input and the output
(VIN – VOUT) at a given output current level.
Limited by rated output current: The rated output current limits the maximum recommended output current
level. Exceeding this rating causes the device to fall out of specification.
Limited by thermals: The shape of the slope is given by Equation 11. The slope is nonlinear because the
junction temperature of the LDO is controlled by the power dissipation across the LDO; therefore, when VIN
– VOUT increases, the output current must decrease in order to ensure that the rated junction temperature
of the device is not exceeded. Exceeding this rating can cause the device to fall out of specifications and
reduces long-term reliability.
Limited by VIN range: The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Maximum VIN
Limited by
Minimum VIN
VIN ± VOUT (V)
Figure 8-13. Continuous Operation Slope Region Description
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Figure 8-14 to Figure 8-19 show the recommended area of operation curves for this device on a JEDECstandard high-K board with a RθJA = 35.4°C/W, as given in the Electrical Characteristics table.
5
5
4.5
Output Current (A)
4
3.5
3
2.5
2
1.5
4
3
2.5
2
1.5
1
0.5
0.5
0
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
Figure 8-14. Recommended Area for Continuous
Operation for VOUT = 0.9 V With Bias
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
Figure 8-15. Recommended Area for Continuous
Operation for VOUT = 1.2 V With Bias
5
5
4
3.5
3
2.5
2
1.5
TA = 40qC
TA = 55qC
TA = 70qC
TA = 85qC
RACO at TA = 85qC
4.5
4
Output Current (A)
TA = 40qC
TA = 55qC
TA = 70qC
TA = 85qC
RACO at TA = 85qC
4.5
Output Current (A)
3.5
1
0
3.5
3
2.5
2
1.5
1
1
0.5
0.5
0
0
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
Figure 8-16. Recommended Area for Continuous
Operation for VOUT = 1.8 V
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
Figure 8-17. Recommended Area for Continuous
Operation for VOUT = 2.5 V
5
5
4
3.5
3
2.5
2
1.5
4
3.5
3
2.5
2
1.5
1
1
0.5
0.5
0
TA = 40qC
TA = 55qC
TA = 70qC
TA = 85qC
RACO at TA = 85qC
4.5
Output Current (A)
TA = 40qC
TA = 55qC
TA = 70qC
TA = 85qC
RACO at TA = 85qC
4.5
Output Current (A)
TA = 40qC
TA = 55qC
TA = 70qC
TA = 85qC
RACO at TA = 85qC
4.5
Output Current (A)
TA = 40qC
TA = 55qC
TA = 70qC
TA = 85qC
RACO at TA = 85qC
0
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
Figure 8-18. Recommended Area for Continuous
Operation for VOUT = 3.3 V
0
0.25
0.5
0.75
VIN - VOUT (V)
1
1.25
1.5
Figure 8-19. Recommended Area for Continuous
Operation for VOUT = 5.0 V
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8.2 Typical Applications
8.2.1 Low-Input, Low-Output (LILO) Voltage Conditions
This section discusses the implementation of the TPS7A84 using the ANY-OUT configuration to regulate a 3.0-A
load requiring good PSRR at high frequency with low-noise at 0.9 V using a 1.3-V input voltage and a 5.0-V bias
supply. The schematic for this typical application circuit is provided in Figure 8-20.
CBIAS
Bias
Supply
BIAS
EN
PG
RPG
Input
Supply
IN
OUT
To Load
COUT
CIN
Device
SNS
CFF
NR/SS
FB
CNR/SS
GND
50mV 100mV 200mV 400mV 800mV
1.6V
Figure 8-20. Typical Application
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 8-6 as the input parameters.
Table 8-6. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
1.3 V, ±3%, provided by the dc-dc converter switching at 500 kHz
Bias voltage
5.0 V, ±5%
Output voltage
0.9 V, ±1%
Output current
3.0 A (maximum), 100 mA (minimum)
RMS noise, 10 Hz to 100 kHz
< 10 µVRMS
PSRR at 500 kHz
> 40 dB
Start-up time
< 25 ms
8.2.1.2 Detailed Design Procedure
At 3.0 A, the dropout of the TPS7A84 has 180-mV maximum dropout over temperature, thus a 400-mV
headroom is sufficient for operation over both input and output voltage accuracy. The bias rail is provided for
better performance for the LILO conditions. The PSRR is greater than 40 dB in these conditions, as per the
PSRR vs Frequency and IOUT curve. Noise is less than 10 µVRMS, as per the VBIAS PSRR vs Frequency curve.
The ANY-OUT internal resistor network is also used for maximum accuracy.
To achieve 0.9 V on the output, the 100mV pin is grounded. The voltage value of 100 mV is added to the 0.8-V
internal reference voltage for VOUT(nom) equal to 0.9 V, as described in Equation 13.
VOUT(nom) = VNR/SS + 0.1 V = 0.8 V + 0.1 V = 0.9 V
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Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.
Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors
for the output are selected.
To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. This
value is calculated with Equation 14.
tSS = (VNR/SS × CNR/SS) / INR/SS
(14)
At the 3.0-A maximum load, the internal power dissipation is 1.2 W and corresponds to a 42.48°C junction
temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient
temperature, the junction temperature is at 97.5°C. To further minimize noise, a feed-forward capacitance (CFF)
of 10 nF is selected.
8.2.1.3 Application Curves
8
50
7
25
6
0
5
-25
4
-50
3
-75
2
-100
1
-125
0
-150
100
0
10
20
30
40
50
60
Time (Ps)
70
80
90
AC Coupled Output Voltage (mV)
9
Output Current (A)
1.2
100
IOUT
VOUT, AC 75
1
0.8
Voltage (V)
10
0.6
0.4
VEN
VOUT, CNR/SS = 0 nF
VOUT, CNR/SS = 10 nF
VOUT, CNR/SS = 47 nF
VOUT, CNR/SS = 100 nF
0.2
0
-0.2
0
Figure 8-21. Output Load Transient Response
5
10
15
20
25
30
Time (ms)
35
40
45
50
Figure 8-22. Output Start-Up Response
8.2.2 Typical Application for a 5.0-V Rail
This section discusses the implementation of the TPS7A84 using an adjustable feedback network to regulate a
3-A load requiring good PSRR at high frequency with low-noise at an output voltage of 5.0 V. The schematic for
this typical application circuit is provided in Figure 8-23.
Optional Bias
Supply
CBIAS
BIAS
EN
PG
RPG
Input
Supply
IN
OUT
To Load
COUT
CIN
Device
SNS
CFF
NR/SS
R1
FB
CNR/SS
R2
GND
50mV 100mV 200mV 400mV 800mV
1.6V
Figure 8-23. Typical Application
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8.2.2.1 Design Requirements
For this design example, use the parameters listed in Table 8-6 as the input parameters.
Table 8-7. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
5.50 V, ±1%, provided by the dc-dc converter switching at 500 kHz
Bias voltage
Not used because VOUT ≥ 2.20 V
Output voltage
5.0 V, ±1%
Output current
3.0 A (maximum), 10 mA (minimum)
RMS noise, 10 Hz to 100 kHz
< 10 µVRMS
PSRR at 500 kHz
> 40 dB
Start-up time
< 25 ms
8.2.2.2 Detailed Design Procedure
At 3.0 A and 5.0 VOUT, the dropout of the TPS7A84 has a 340-mV maximum dropout over temperature, thus a
500-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high
temperature on some devices, the TPS7A84 can enter dropout if both the input and output supply are beyond
the edges of their accuracy specification.
For a 5.0-V output. use external adjustable resistors. See the resistor values in listed Table 8-5 for choosing
resistors for a 5.0-V output.
Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.
Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors
for the output are selected.
To satisfy the required start-up time and still maintain low noise performance, a 100-nF CNR/SS is selected. This
value is calculated with Equation 14.
tSS = (VNR/SS × CNR/SS) / INR/SS
(15)
At the 3.0-A maximum load, the internal power dissipation is 1.5 W and corresponds to a 53.1°C junction
temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient
temperature, the junction temperature is at 108.1°C. To further minimize noise, a feed-forward capacitance
(CFF) of 10 nF is selected.
8.2.2.3 Application Curves
100
IOUT = 0.1 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT = 2.5 A
IOUT = 3.0 A
80
60
40
20
0
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
1x107
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
100
VIN = 5.30 V
VIN = 5.35 V
VIN = 5.40 V
VIN = 5.45 V
VIN = 5.50 V
VIN = 5.55 V
VIN = 5.60 V
80
60
40
20
0
1x101
1x102
1x103
1x104
1x105
Frequency (Hz)
1x106
1x107
Figure 8-24. PSRR vs Frequency and IOUT for VOUT Figure 8-25. PSRR vs Frequency and VIN for VOUT =
= 5.0 V
5.0 V at IOUT = 3.0 A
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9 Power Supply Recommendations
The TPS7A84 is designed to operate from an input voltage supply range between 1.1 V and 6.5 V. If the input
supply is less than 1.4 V, then a bias rail of at least 3.0 V must be used. The input voltage range provides
adequate headroom in order for the device to have a regulated output. This input supply must be well regulated.
If the input supply is noisy, additional input capacitors with low ESR can help improve output noise performance.
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout
For best overall performance, place all circuit components on the same side of the circuit board and as near
as practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to the input and output capacitors is strongly discouraged and
negatively affects system performance. The grounding and layout scheme illustrated in Figure 10-1 minimizes
inductive parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability.
A ground reference plane is also recommended and is either embedded in the PCB itself or located on the
bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output
voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device
when connected to the thermal pad. In most applications, this ground plane is necessary to meet thermal
requirements.
10.2 Layout Example
CBIAS
To Bias Supply
1.6V
800mV
400mV
GND
200mV
100mv
Ground Plane for Thermal Relief and Signal
Ground
10
9
8
7
6
11
5
RPG
BIAS
12
4
PG Output
PG
R2
Thermal Pad
To Signal Ground
To PG Pullup Supply
50mV
NR/SS
13
3
FB
EN
14
2
SNS
To Signal Ground
CNR/SS
Enable Signal
To Load
CFF R1
1
17
18
19
20
IN
GND
OUT
OUT
Input Power Plane
16
IN
15
IN
CIN
OUT
Output Power Plane
COUT
Power Ground Plane
Vias used for application purposes.
Figure 10-1. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS7A84. The summary information for this fixture is shown in Table 11-1.
Table 11-1. Design Kits and Evaluation Modules
NAME
LITERATURE NUMBER
TPS7A8400EVM-753 evaluation module
SBVU028
The EVM can be requested at the Texas Instruments web site through the TPS7A84 product folder.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS7A84 is available through the TPS7A84 product folder
under simulation models.
11.1.2 Device Nomenclature
Table 11-2. Ordering Information(1)
PRODUCT
TPS7A84YYYZ
(1)
DESCRIPTION
YYY is the package designator.
Z is the package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
Texas Instruments, TPS3702 High-Accuracy, Overvoltage and Undervoltage Monitor data sheet
Texas Instruments, TPS7A8400EVM-753 Evaluation Module user's guide
Texas Instruments, Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator
application report
Texas Instruments, 6A Current-Sharing Dual LDO design guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
ANY-OUT™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
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11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPS7A8400RGRR
ACTIVE
VQFN
RGR
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11CI
TPS7A8400RGRT
ACTIVE
VQFN
RGR
20
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
11CI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
