PI2EQX3202B-SATA-EVB1

PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial ReDriver™ with Equalization, De-emphasis, and Squelch Features Description • Supports data rates up to 3.2Gbps on each lane Pericom Semiconductor’s PI2EQX3202B is a low power, signal ReDriver™. The device provides programmable equalization, amplification, and de-emphasis by using 7 select bits, SEL[0:6], to optimize performance over a variety of physical mediums by reducing Inter-symbol Interference. PI2EQX3202B supports four 100-Ohm Differential CML data I/O’s between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the ReDriver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independently. When a channel is enabled (EN_x=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericom’s PI2EQX3202B also provides power management Stand-by mode operated by an Enable pin. • Optimized for SATA i/m operation • Adjustable Transmiter De-Emphasis & Amplitude • Adjustable Receiver Equalization • Two Spread Spectrum Reference Clock Buffer Outputs • Optimized for SATA applications • Input signal level detection & output squelch on all channels • 100-Ohm Differential CML I/O’s • Low Power (100mW per Channel) • Standby Mode – Power Down State • VDD Operating Range: 1.5V to 1.8V • Industrial temperture range • Packaging (Pb-free & Green): 84-ball LFBGA (NB84) Block Diagram Pin Description LVCMOS Signal Detection SD_x CML CML 1 2 3 4 5 6 7 8 9 10 A SD_C SD_D SEL0_A SEL0_B SEL4_A SEL4_B SEL6_A SEL6_B EN_A EN_B B VDD SD_B VDD SEL1_A SEL2_A SEL3_A SEL5_A VDD EN_C VDD C BO+ SD_A AI+ SEL1_B SEL2_B SEL3_B SEL5_B BI+ EN_D AO+ D BO– VDD AI– BI– GND AO– E GND VDD GND GND GND GND xO+ xI+ Equalizer Limiting Amp xO- xISEL [0:2] EN_x 84-Ball LFBGA Power Management SEL [2]_ x SEL [3]_ x F VDD GND VDD VDD GND VDD G DO+ SEL0_C CI+ DI+ SEL6_C CO+ H DO– SEL0_D CI– VDD CKIN+ CKIN– GND DI– SEL6_D CO– J GND SEL1_C GND SEL2_C SEL2_D SEL3_D IREF GND SEL4_D GND K EN_CLK SEL1_D SEL3_C SEL4_C OUT0+ OUT0– OUT1+ OUT1– SEL5_C SEL5_D -- Repeated 2 times -- CKINCKIN+ Buffer EN_ CLK OUTOUT+ IREF 09-0019 1 PS8885G 07/31/09 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial ReDriver™ with Equalization, De-emphasis, and Squelch Pin Description Pin # B1, F1, D2, E2, B3, F3, H4, B8, F8, B10, F10 C3 D3 E1, J1, F2, E3, J3, H7, E8, J8, D9, E9, F9, E10, J10 C8 D8 G3 H3 G8 H8 A3, B4, B5 A4, C4, C5 G2, J2, J4 H2, K2, J5 B6, A5 C6, A6 K3, K4 J6, J9 B7, A7 C7, A8 K9, G9 K10, H9 C10 D10 BI+ BICI+ CIDI+ DISEL[0:2]_A SEL[0:2]_B SEL[0:2]_C SEL[0:2]_D SEL[3:4]_A SEL[3:4]_B SEL[3:4]_C SEL[3:4]_D SEL[5:6]_A SEL[5:6]_B SEL[5:6]_C SEL[5:6]_D AO+ AO- C1 D1 BO+ BO- O G10 H10 CO+ CO- O G1 H1 DO+ DO- O A9, A10, B9, C9 EN_ [A,B,C,D] I 09-0019 Pin Name I/O VDD PWR AI+ AI- I GND PWR Description Supply Voltage, 1.5V to 1.8V ± 0.1V CML Input Channel A with internal 50Ω pull down Supply Ground I CML Input Channel B with internal 50Ω pull down I CML Input Channel C with internal 50Ω pull down I CML Input Channel D with internal 50Ω pull down I I I I I I I I I I I I O Selection pins for equalizer (see Amplifier Configuration Table) w/ 50kΩ internal pull up Selection pins for amplifier (see Amplifier Configuration Table) w/ 50kΩ internal pull up Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50kΩ internal pull up CML Output Channel A internal 50Ω pull up to VDD during normal operation and 2kΩ when EN_A=0. Drives to output common mode voltage when input is