A product Line of
Diodes Incorporated
PI3DPX1207B
DP-Alt DP1.4/USB3.1 10Gbps Linear Redriver with Non-Blocking, Latency-Free and built-in Aux Switch
Description
Applications
PI3DPX1207B is the DP-Alt 1.4 (Max 10Gbps) Linear Redriver.
DP1.4 standard can support 4K2K@120Hz / 25.82 Gbps with
4-channels.
ÎÎ Notebook, Desktop and AIO personal computers
Each of the DP1.4 and USB3.1 Gen2 differential signals can be easily
adjustable with equalization, output swing and gain adjustment
by either pin or I2C control settings. It can optimize the DP/USB
10Gbps signal performance over a variety of physical mediums by
reducing Inter-symbol interference jitters.
ÎÎ DP-Alt Monitors and Displays
ÎÎ Active DP-Alt Cables/Adapters
USB3.1 Gen2
DPALT
PI3DPX1207
DPAlt
ReDriver
DP1.3
Non-blocking linear Redriver can provides 2x better additive
jitter performance than the conventional CMOS-based Redriver.
Since Linear Redriver does not block the Receiver DFE’s adaptive
channel controls, it can natively support DisplayPort Transparent
LT(Link Training) without any dependency of the DP-Aux channels listener.
USB3.1 Gen2
DPALT
PI3DPX1207
DPAlt
ReDriver
DP1.4
NB PC System
DPALT
DPALT
Type-C PD
Controller
I2C
Figure 1-1 Type-C Connector inside PCs
Named as “Trace Loss Canceling” technology, and supports the
cascading high speed link connections between Host and Device.
It means multiple linear Redriver can be placed in the link to work
seamlessly to compensate high insertion loss.
Type-C to Type-C Board
DP/USB
Aux
Type-C Connector
The Cascading, Low Jitter and Simplicity of Gain adjustment capabilities to extend signal transmission features are ideal choice for
the 8-10Gbps high speed DP Alt signal integrity solutions.
Cable
PI3DPX1207B
Linear Redriver
DP/USB
SBU1/2
Captive connector
PD Control Circults
Figure 1-2 DP-Alt to DP Active Cables
Features
Ordering Information
ÎÎ DP-Alt 4-channel Redriver and DeMux (DP 2-ch and USB
2-ch)
ÎÎ Latency-free USB Read/Write Transfer rate and DisplayPort
Redriver Link Training for variable video frame rate
control
ÎÎ DP1.4 (8.1 Gbps) and USB3.1 Gen 2 (10 Gbps) standard
compliant
Ordering Number
PI3DPX1207BZHEX
Package
Code
Package Description
ZH
42-pin, Very Thin Quad Flat NoLead (TQFN) (3.5x9mm)
Notes:
ÎÎ Type-C DP/USB mode selection: DP only, USB only, DP/
USB split modes
1. EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU
(RoHS 3) compliant. All applicable RoHS exemptions applied.
ÎÎ Natively support Transparent DisplayPort Link training
with Non-blocking No-latency Linear ReDriver
ÎÎ Independently controlled EQ/Gain/Swing signal outputs for
DisplayPort and USB modes
2. See http://www.diodes.com/quality/lead-free/ for more information about
Diodes Incorporated’s definitions of Halogen- and Antimony-free, “Green” and
Lead-free. Thermal characteristics can be found on the company web site at
www.diodes.com/design/support/packaging/
3. E = Pb-free and Green
4. X suffix = Tape/Reel
ÎÎ Type-C Plug and Aux Flipping controls through I2C slave
pins
ÎÎ Slave I2C support only. I2C speed up to 1MHz
ÎÎ Auto power saving circuit
ÎÎ Single Power Supply: 3.3V
PI3DPX1207B
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2. General Information
2.1 Revision History
Revision
Description of Changes
Jul 2016
Preliminary Datasheet release.
Aug 2016
Low-power mode, ePad Via, Default register values added.
Oct 2016
Ch 4. Vin-Diff 400mV to Typ changed. Add more clarification in Pin Description and Block Diagram.
Nov 2016
Ch 4. AC/DC electrical parameters and output eye added. Removed Generic mode. Pls contact Diodes for Generic
mode application usage.
Dec 2016
Ch 4. Power consumption max added.
Ch 5. PCB routing information, CTS report added.
Add Sample Errata and disclaimer
Jan 2017
Ch5. DP1.4 CTS test report added.
May 2017
Ch3. 4-bit EQ and FG setting change for high speed Eye signal optimization. Related register spec updated
Ch5. USB compliance report added.
Aug 2017
Application reference schematic changed for Aux & SBU1/2 connection. SiGe BiCmos Redriver Jitter performance
Benchmark data added in Application session. Power down current max IPD increase 100uA from 66uA. Aux
listener features and DP low power D3 mode removed.
Nov 2017
USB3.2, PCIeG3, TMDS modes added for special usage. EC / PD / TCPC programming guide(p51). Due to the Intel’s new requirement on the TX impedance when Power-on and Receiver detect phase. All TX 4kOhm impedance
changed from 4kOhm to 4.5kOhm (p9, p11,p17)
Mar 2018
AUXSBU2, 18 pin; AUXSBU1, 19 pin
Page 46, EN and IN_HPD are reversed.
Apr 2018
Updated 2.3 Diagram
May 2018
Remove Industrial Temp Ordering Information, Remove PI3DPX1207D from Section 2.2; Remove PI3HDX711B
and PI3HDX2711B from Section 2.4
2.2 Family Products Comparison
PI3DPX1207B
PI3DPX1205A
Type-C DisplayPort Alt Redriver
Type-C DisplayPort Alt Active Mux
USB / DP Latency-Free
USB / DP Latency-Free
Max Data Rate
10Gbps
10Gbps
Package
42-pin TQFN (3.5x9mm)
40-pin TQFN(4x6mm)
NEXT Crosstalk
Very good, -45dB at 5GHz
Very good, -45dB at 5GHz
Package Pin-out
Place 2 pins space between 10Gbps Data channels
TX0/1, RX0/1 to reduce Crosstalk
Place 2 pins space between 10Gbps Data channels
TX0/1, RX0/1 to reduce Crosstalk
Control modes
I2C or Pin-mode
I2C mode control
Power supply
3.3V
3.3V
General Features
PI3DPX1207B
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2.3 PI3DPX1207 Redriver Switching Preset modes
Preset mode supporting with I2C control
Preset mode with pin-strap (or I2C control)
CONF = 0010
CONF bit controlled by I2C. Default CONF = 0
CONF = 1000
CONF = 0011
CONF = 1001
AP_RX2
AP_RX2
CON_TX2 (DP1)
CON_TX2 (DP2)
AP_RX2
AP_TX2
AP_TX2
CON_RX2(DP0)
AP_TX2
CON_RX2(DP3)
CON_TX1(DP2)
AP_RX1
CON_TX1(DP1)
CON_RX1(DP3)
AP_TX1
CON_RX1(DP0)
AP_RX1
AP_RX1
AP_TX1
AP_TX1
AUXP
AUXP
SBU1
SBU1
AUXP
AUXN
AUXN
SBU2
SBU2
AUXN
DP
CON_TX2 (USB3.1) AP_RX2
CON_TX2 (DP1)
CON_RX2(USB3.1) AP_TX2
CON_RX2(DP0)
CON_TX1(DP1)
AP_RX1
CON_TX1(USB3.1)
CON_RX1(DP0)
AP_TX1
CON_RX1(USB3.1)
SBU1
AUXP
SBU2
AUXN
DP/USB3
DP Flip
AP_RX2
AP_TX2
AP_RX1
AP_TX1
AUXP
AUXN
USB3.1
CONF = 0101
CON_TX2
AP_RX2
CON_TX2
CON_RX2
AP_TX2
CON_RX2
CON_TX1
AP_RX1
CON_TX1
CON_RX1
AP_TX1
CON_RX1
SBU1
AUXP
SBU1
SBU2
AUXN
SBU2
USB3.1 Flip
SBU2
DP/USB3 Flip
CONF = 1010
CONF = 0100
SBU1
CONF = 1011
AP_RX2
CON_TX2 (TMDS1) AP_RX2
CON_TX2 (TMDS2)
AP_TX2
CON_RX2(TMDS0)
AP_TX2
CON_RX2(TMDS3)
AP_RX1
CON_TX1(TMDS2)
AP_RX1
CON_TX1(TMDS1)
AP_TX1
CON_RX1(TMDS3)
AP_TX1
CON_RX1(TMDS0)
AUXP
SBU1
AUXP
SBU1
AUXN
SBU2
AUXN
SBU2
AC-TMDS Flow
AC-TMDS Flip
Note: DP_PIN_EN# =1 when IN_HPD pin not controlled the channels
CONF = 0110
AP_RX2
CONF = 0111
CON_TX2 (DP1)
AP_RX2
CON_TX2 (USB3.1)
CON_RX2(DP0)
AP_TX2
CON_RX2(USB3.1)
AP_RX2
AP_TX2
AP_TX2
AP_RX1
AP_RX1
CON_TX1(USB3.1)
AP_RX1
CON_TX1(DP1)
AP_TX1
AP_TX1
CON_RX1(USB3.1)
AUXP
AUXN
AP_TX1
SBU1
AUXP
SBU2
AUXN
DP/USB3
CONF = 1101
CONF = 1100
CON_RX1(DP0)
CON_TX2
AP_RX2
CON_TX2
CON_RX2
AP_TX2
CON_RX2
CON_TX1
AP_RX1
CON_RX1
AP_TX1
CON_RX1
SBU1
SBU2
USB3.2
DP/USB3 Flip
PCIe3
CONF = 1110
AP_RX2
AP_TX2
AP_RX1
AP_TX1
PCIe3/USB3
DP Alt Type-C Redriver
PI3DPX1207B
Document number DS39965 Rev 4-2
CON_TX1
CONF = 1111
CON_TX2 (PCIe3)
AP_RX2
CON_TX2 (USB3)
CON_RX2(PCIe3)
AP_TX2
CON_RX2(USB3)
CON_TX1(USB3)
AP_RX1
CON_TX1(PCIe3)
CON_RX1(USB3)
AP_TX1
CON_RX1(PCIe3)
PCIe3/USB3
Flip
USB3.2 and PCIe3 , AC-TMDS Redriver Modes
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2.4 Other Related Products
Part Numbers
Products Description
Redrivers
PI3DPX1203B
DisplayPort 1.4 Redriver for Source/Sink/Cable Application, Linear-type
PI3HDX1204B1
HDMI 2.0 Redriver (DP++ Level Shifter), High EQ, place near to the source-side, Limiting type
PI3HDX1204E
HDMI 2.0 Linear Redriver (DP++ Level Shifter) , Link transparent, place near to the sink-side
PI3DPX1207B
DisplayPort 1.4 Alt Type-C Redriver, 8.1 Gbps and USB3.1 10 Gbps, Link Transparent
PI3DPX1202A
Low Power DisplayPort 1.2 Redriver with built-in AUX Listener, Limiting-type
PI3HDX511F
High EQ HDMI 1.4b Redriver and DP++ Level Shifter for Sink/Source Application, Limiting-type
Active Switches & Splitters
PI3DPX1205A
DisplayPort 1.4 Alt Type-C Mux Redriver, 8.1 Gbps and USB3.1 10 Gbps, Link Transparent
PI3HDX231
HDMI 2.0 3:1 ports Mux Redriver, Linear-type
PI3HDX414
HDMI 1.4b 1:4 Demux Redriver & Splitter for 3.4 Gbps Application, Limiting-type
PI3HDX412BD
HDMI 1.4b 1:2 Demux Redriver & Splitter for 3.4 Gbps Application, Limiting-type
PI3HDX621
HDMI 1.4 Redriver 2:1 Active Switch with built-in ARC and Fast Switching support, Limiting-type
PI3DPX1207B
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Contents
1. Product Summary........................................................................................................................................................ 1
2. General Information................................................................................................................................................... 2
2.1 Revision History......................................................................................................................................................... 2
2.2 Family Products Comparison .................................................................................................................................. 2
2.3 PI3DPX1207 Redriver Switching Preset modes................................................................................................... 3
2.4 Other Related Products............................................................................................................................................ 4
3. Pin Configuration........................................................................................................................................................ 6
3.1 Package Pin-out......................................................................................................................................................... 6
3.2 Pin Description........................................................................................................................................................... 7
4. Functional Description.............................................................................................................................................. 9
4.1 Product Feature Details ........................................................................................................................................... 9
4.2 Functional Block Diagram....................................................................................................................................... 10
4.3 The Operating mode control.................................................................................................................................. 11
4.4 EQ/FG/SW controls ................................................................................................................................................ 13
4.5 USB mode................................................................................................................................................................. 15
4.6 DisplayPort mode..................................................................................................................................................... 16
4.7 I2C Programming .................................................................................................................................................... 19
4.8 Detail Programming Registers............................................................................................................................... 21
5. Electrical Specification
..................................................................................................................................... 27
5.1 Absolute Maximum Ratings.................................................................................................................................... 27
5.2 Recommended Operating Conditions.................................................................................................................. 27
5.3 Thermal Information................................................................................................................................................ 27
5.5 Power Consumption................................................................................................................................................ 28
5.6 AC/DC Characteristics............................................................................................................................................ 28
6. Applications................................................................................................................................................................. 38
6.1 Channel connection diagram................................................................................................................................. 38
6.2 Type-C AC-cap connection diagram..................................................................................................................... 38
6.3 SiGe BiCMOS vs. CMOS Redrivers Jitter performance.................................................................................... 39
6.4 Redriver Placement Consideration....................................................................................................................... 40
6.5 Channel Output Eye Signal vs. EQ/FG/SW Setting (For ES samples Information Only)............................. 42
6.6 Reference Application Schematics ...................................................................................................................... 46
6.7 Type-C System Block diagram.............................................................................................................................. 47
6.8 Programming Guide................................................................................................................................................ 49
6.9 PCB Layout Guideline............................................................................................................................................. 55
6.10 DP/USB Compliance Test.................................................................................................................................... 61
7. Mechanical/Packaging Information ................................................................................................................... 63
7.1 Mechanical Outline.................................................................................................................................................. 63
7.2 Part Marking Information........................................................................................................................................ 64
7.3 Tape & Reel Materials and Design........................................................................................................................ 65
8. Important Notice........................................................................................................................................................ 68
PI3DPX1207B
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3. Pin Configuration
A0/DP_EQ
AP_RX2P
AP_RX2N
VDD33
VDD33
AP_TX2P
AP_TX2N
VDD33
RXDET_EN
AP_RX1N
AP_RX1P
VDD33
VDD33
AP_TX1N
AP_TX1P
AUXP
AUXN
1
2
3
4
5
6
7
A2/SSAP_EQ
FG
SW
EN
3.1 Package Pin-out
(Top View)
42 41 40 39
38
37
36
PI3DPX1207
35
42-TQFN
34
3.5x9mm
33
8
9
10
32
31
30
29
ePAD
11
12
13
14
15
28
16
17
IN_HPD
CON_TX2P
CON_TX2N
VDD33
VDD33
CON_RX2P
CON_RX2N
VDD33
I2C_EN
CON_TX1N
CON_TX1P
27
26
25
VDD33
VDD33
24
CON_RX1P
23
A1/SSCON_EQ
22
CONF0
CON_RX1N
CONF1/SCL
AUXSBU1
CONF2/SDA
AUXSBU2
18 19 20 21
Figure 3-1 42-TQFN package pin-out (PI3DPX1207B)
PI3DPX1207B
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3.2 Pin Description
Pin Name
CON_RX1N/P
Pin #
25,24
Type
Description
I/O
Type-C receptacle RX/TX Channel CML input/output
With selectable input termination between 50Ω to VDD, 67kΩ to VbiasRx or 67kΩ
to GND.
With selectable output termination between 50Ω to VbiasTx, 4.5k to VbiasTx or
Hi-Z
Type-C receptacle RX/TX Channel CML input/output
With selectable input termination between 50Ω to VDD, 67kΩ to VbiasRx or 67kΩ
to GND.
With selectable output termination between 50Ω to VbiasTx, 4.5k to VbiasTx or
Hi-Z
CON_RX2P/N
33,32
I/O
CON_TX2P/N
37,36
O
CML output terminals. With selectable output termination between 50Ω to VbiasTx, 4.5kΩ to VbiasTx or Hi-Z
CON_TX1N/P
29,28
O
CML output terminals. With selectable output termination between 50Ω to VbiasTx, 4.5kΩ to VbiasTx or Hi-Z
AP_RX2P/N
2,3
I
CML input terminals. With selectable input termination between 50Ω to VDD,
67kΩ to VbiasRx or 67kΩ to GND.
AP_RX1N/P
10,11
I
CML input terminals. With selectable input termination between 50Ω to VDD,
67kΩ to VbiasRx or 67kΩ to GND.
AP_TX2P/N
AP_TX1N/P
A0/DP_EQ
6,7
14,15
1
I/O
Type-C receptacle RX/TX Channel CML input/output terminals.
With selectable input termination between 50Ω to VDD, 67kΩ to VbiasRx or 67kΩ
to GND.
With selectable output termination between 50Ω to VbiasTx, 4.5k to VbiasTx or
Hi-Z
I/O
Type-C receptacle RX/TX Channel CML input/output terminals.
With selectable input termination between 50Ω to VDD, 67kΩ to VbiasRx or 67kΩ
to GND.
With selectable output termination between 50Ω to VbiasTx, 4.5k to VbiasTx or
Hi-Z
I
For pin control mode (I2C_EN=Low)
DP Application processor side: The equalization selection. 4-level input pins.
With internal 100kΩ pull-up resistor and 200kΩ pull-down resistor.
For I2C control mode (I2C_EN=High).
I2C address select. 2-level input pins. Internal 200kΩ pull-down resistor.
I
Receiver detect enable mode. With internal 300kΩ pull-up resistor.
“Low”: Disabled
“High”: Enabled (Default)
16, 17
I/O
Host AP/UFP-side DisplayPort Aux Channel, connected to Source
18, 19
I/O
Connector/DFP Low Speed Signal Port. Side band use
RXDET_EN
9
AUXP/N
AUXSBU2
AUXSBU1
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Pin Name
CONF2/SDA
Pin #
20
Type
I/O
CONF1/SCL
21
I
CONF0
22
I
A1/SSCON_EQ
23
I
Description
For Pin control mode with internal 300kΩ pull-down resistor (I2C_EN=Low).
CONF2 is the selection pin for the channel mode assignment and flip control
For I2C control mode (I2C_EN=High).
SDA is I2C control bus data. Open drain structure.
For Pin control mode with internal 300kΩ pull-down resistor (I2C_EN=Low).
CONF1 is the selection pin for the channel mode assignment and flip control
For I2C control mode (I2C_EN=High)
SCL is I2C control clock. Open drain structure.
For Pin control mode (I2C_EN=Low)
CONF0 is the selection pin for the channel mode assignment and flip control.
300kΩ pull-down resistor.
For pin control mode (I2C_EN=Low)
USB Type-C connector side. The equalization selection. 4-level input pins. With
internal 100kΩ pull-up resistor and 200kΩ pull-down resistor.
For I2C control mode (I2C_EN=High)
The I2C address select. 2-level input pins. With internal 200kΩ pull-down resistor.
I2C_EN
30
I
I2C enable control. With internal 300kΩ pull-up resistor.
“Low”: Pin control is selected
“High”: I2C control is selected (Default)
IN_HPD
38
I
Hot plug detection from Sink. With internal 300kΩ pull-down resistor.
SW
39
I
For pin control mode (I2C_EN=Low)
DP Type-C Connector side: The -1dB linear swing selection. 2-level input pins.
With internal 300kΩ pull-up resistor.
FG
40
I
For pin control mode (I2C_EN=Low)
The flat selection. 4-level input pins. With internal 100kΩ pull-up resistor and
200kΩ pull-down resistor.
A2/SSAP_EQ
41
I
For pin control mode (I2C_EN=Low)
USB Application Process side: The equalization selection. 4-level input pins. With
internal 100kΩ pull-up resistor and 200kΩ pull-down resistor.
For I2C control mode (I2C_EN=High)
The I2C address select. 2-level input pins. With internal 200kΩ pull-down resistor.
EN
42
I
Chip Enable. With internal 300kΩ pull-up resistor.
“Low”: Chip Power Down
“High”: Normal Operation (Default)
VDD33
4,5
8, 12
13, 26
27,31
34,35
P
3.3V Power Supply
ePAD
ePAD
G
ePAD for the Ground
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4. Functional Description
4.1 Product Feature Details
General Features
ÎÎ DP-Alt HBR3 8.1Gbps mode and USB3.1 10Gbps Type-C application
ÎÎ Flexible DP-Alt mode switching between USB3.1 Gen2 and DP 8.1Gbps
ÎÎ Ultra Low standby power with auto power saving for the DisplayPort and USB mode
ÎÎ Selectable adjustment of receiver Equalization, Flat gain, -1dB compression linear output swing
ÎÎ Built-in control logic for Type-C plug/unplug normal and flipping orientations
ÎÎ Active Linear ReDriving for signal integrity
ÎÎ Except the EN pin, I2C_EN, I2C address pins, IN_HPD and I2C I/O pins, all other pin setting will be ignored in the I2C
mode.
ÎÎ Slave I2C only. I2C speed up to 1MHz
ÎÎ The I2C I/O buffer supports the 1.8V/3.3V signal condition
ÎÎ IN_HPD could be selected as active high or active low by I2C mode ( byte4 [1])
ÎÎ Single power supply 3.3±0.3V
DisplayPort 1.4
ÎÎ DP LT-transparent through linear Redriver design
ÎÎ Hot Plug Detect
USB 3.1 Gen 2
ÎÎ Selectable input termination between 50Ω to VDD, 67kΩ to VbiasRx or 67kΩ to GND.
ÎÎ Selectable output termination between 50Ω to VbiasTx, 4.5kΩ to VbiasTx or Hi-Z with receiver termination detection.
ÎÎ Possible operation modes: PD, Unplug, deep slumber mode, slumber mode and active mode.
ÎÎ Receives and transmits the signal in unplug, deep slumber mode and active mode.
ÎÎ Active mode: The channel is always ready to transmit. No Ton/Toff due to the signal detector in this mode.
ÎÎ Slumber mode, Deep slumber mode and Unplug mode: The channel is partially/fully off due to the power saving. Signal detector
is monitoring the input signal actively. If the input signal is detected, the channel will switch to the active mode. ON-time is
operation mode selection dependent.
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4.2 Functional Block Diagram
AP_RX2P/N
EQ
Tx
Tx
AP_TX2P/N
AP_RX1N/P
EQ
EQ
Tx
CON_RX2P/N
EQ
Tx
CON_TX1N/P
Tx
AP_TX1N/P
EQ
EQ
AUXP
AUXN
CONF2/SDA
CONF1/SCL
CON_TX2P/N
Tx
CON_RX1N/P
AUXSBU1
AUXSBU2
Mux
I2C Slave
IN_HPD
EN
I2C_EN
Conf. Register
USB state controller
DP state controller
Bandgap, Biasing
FG
SW
A0/DP_EQ
A1/SSCON_EQ
A2/SSAP_EQ
RXDET_EN
CONF0
Figure 4-1 PI3DPX1207B DP-Alt ReDriver block diagram
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4.3 The Operating mode control
4.3.1 Preset DP-Alt Channel mapping control
CONF
Modes
AP_RX2
AP_TX2
AP_RX1
AP_TX1 AUXP
AUXN
IN HPD/ AUX
CMD
with CONF0/1/2 pins or CONF[3:0] I2C register bits control
0000
Safe State
X
X
X
X
X
X
X
0001
Safe State
X
X
X
X
X
X
X
0010
4 lane DP1.4 + AUX
CON_
TX2
(DP1)
CON_
RX2
(DP0)
CON_
TX1
(DP2)
CON_
RX1
(DP3)
SBU1
SBU2
All CON response
0011
Flip mode:
4 lane DP1.4 + AUX
CON_
TX2
(DP2)
CON_
RX2
(DP3)
CON_
TX1
(DP1)
CON_
RX1
(DP0)
SBU2
SBU1
All CON response
0100
1 lane USB3.x (AP_CH1)
X
X
CON_
TX1
CON_
RX1
X
X
X
0101
Flip mode:
1 lane USB3.x (AP_CH2)
CON_
TX2
CON_
RX2
X
X
X
X
X
0110
USB3 (AP_CH1) + 2 lane
DP1.4(AP_CH2) + AUX
CON_
TX2
(DP1)
CON_
RX2
(DP0)
CON_
TX1
(USB3)
CON_
RX1
(USB3)
SBU1
SBU2
CON2 response
only
0111
CON_
Flip mode:
USB3 (AP_CH1) + 2 lane DP1.4 TX2
(AP_CH2) + AUX
( USB3)
CON_
RX2 (
USB3)
CON_
TX1
(DP1)
CON_
RX1
(DP0)
SBU2
SBU1
CON1 response
only
CON_
CON_
RX1/
TX1/DP1
DP0
SBU1
SBU2
CON1 response
only
with CONF[3:0] i2C register bits control
1000
USB3 (AP_CH2) +
2 lane DP1.4 (AP_CH1) + AUX
CON_
CON_TXRX2(USB3)
2(USB3)
1001
USB3 (AP_CH1) +
2 lane DP1.4 (AP_CH2) +AUX
(flipped)
CON_
TX2/ DP1
CON_
CON_
TXRX2/ DP0
1(USB3)
CON_
RX1(USB3)
SBU2
SBU1
CON2 response
only
1010
4 lane TMDS mode with AUX
channel for HDMI DDC
CON_
TX2
CON_
RX2
CON_
TX1
CON_
RX1
SBU1
SBU2
IN_HPD Only3)
1011
4 lane TMDS mode flipped with CON_
AUX channel for HDMI DDC
TX2
CON_
RX2
CON_
TX1
CON_
RX1
SBU2
SBU1
IN_HPD Only3)
1100
2 lane USB3.x
CON_
TX2
CON_
RX2
CON_
TX1
CON_
RX1
X
X
1101
2 lane PCIe3
CON_
TX2
CON_
RX2
CON_
TX1
CON_
RX1
X
X
1110
USB3 (AP_CH1) + PCIe3
(AP_CH2)
CON_
CON_TXRX2(P2(PCIe3)
CIe3)
CON_
TX1(USB3)
CON_
RX1(USB3)
X
X
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CONF
Modes
AP_RX2
AP_TX2
AP_RX1
AP_TX1 AUXP
AUXN
IN HPD/ AUX
CMD
1111
USB3 (AP_CH2) + PCIe3
(AP_CH1)
CON_
TX2(
USB3 )
CON_
RX2(
USB3)
CON_
TX1(PCIe3)
CON_
RX1(PCIe3)
X
X
X
Note:
1) CONF[2:0] pins and CONF[3:0] (I2C 0x3[7:4]) with mode description. Both Pin and I2C mode can access below setting
2) The high speed channels don’t do any flip action. Only the AUX channel is flipped.
3) Set the I2C reg byte12 bit2 DP_HPD_PIN_EN#=1 if the target channel is not controlled by the IN_HPD pin.
4.3.2 IN_HPD control
Table 4-1. DP_HPD_PIN_EN# register can enable the IN_HPD control
I2C Byte 0x12[2]:
Pin IN_HPD Status
DP_HPD_PIN_EN#
(Hot plug detection input from Sink)
DP output status
1
x
Enabled
0
0
Disabled
0
1
Enabled
4.3.3 IN_HPD assert and De-assert De-bounce timer
IN_HPD transition
De-bounce timer timeout
Assert: Low -> High
~0s
De-assert: High -> Low
~ 325ms typ
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Notes
Any Low-> High transition within timeout
will reset the timer.
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4.4 EQ/FG/SW controls
Table 4-2. Equalization Setting
EQ pin
L
R
F
H
EQ3
EQ2
EQ1
EQ0
@ 2.5GHz
@ 3GHz
@ 4GHz
@ 5GHz
@ 6GHz
Note
0
0
0
0
3.2
3.8
4.9
5.7
6.1
I2C Default
0
0
0
1
3.5
4.2
5.5
6.4
6.9
0
0
1
0
3.8
4.7
6.1
7.1
7.7
0
0
1
1
4.2
5.1
6.6
7.7
8.4
0
1
0
0
4.7
5.6
7.2
8.3
9
0
1
0
1
5
6
7.7
8.9
9.6
0
1
1
0
5.4
6.4
8.2
9.4
10.1
0
1
1
1
5.7
6.8
8.6
9.9
10.6
1
0
0
0
6.2
7.3
9
10.2
11
1
0
0
1
6.5
7.6
9.4
10.7
11.4
1
0
1
0
6.8
7.9
9.8
11.1
11.8
1
0
1
1
7
8.2
10.1
11.4
12.1
1
1
0
0
7.4
8.5
10.4
11.7
12.4
1
1
0
1
7.6
8.8
10.7
12
12.7
1
1
1
0
7.8
9.1
11
12.3
13
1
1
1
1
8.1
9.3
11.3
12.6
13.3
Pin Default
4.4.1 Flat Gain Setting
Table 4-3. FG 4-level input selection pins for the DC gain
FG pin
FG[1:0]
Flat Gain Settings V/V
R (Tie Rext to GND)
00
-1.5 dB
F (Leave Open)
01
0 dB (Default)
L (Tie 0Ω to GND)
10
+1 dB
H (Tie 0Ω to VDD)
11
+2.5 dB
4.4.2 Output -1 dB Compression point output swing setting
Table 4-4. SW selection pins for the -1dB compression point output swing setting
SW pin
USB
DP
0
900mVppd
1100mVppd
1
1000mVppd
1200mVppd (Default)
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4.4.3 I2C mode: 0x5[1:0] to 0x8[1:0]
CONx_SW[1:0]
Output Linear Swing Settings
00
900mVppd
01
1000mVppd
10
1100mVppd
11
1200mVppd (Default)
4.4.4 Chip Enable Setting:
Table 4-5. Channel EN enable pin
EN
Channel Enable Setting
0
Disabled
1
Enabled (Default)
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4.5 USB mode
In the low power mode, the signal detector will still be monitoring the input channel. If a channel is in low power mode and the input
signal is detected, the corresponding channel will wake-up immediately. If a channel is in low power mode and the signal detector
is idle longer than 6ms, the receiver detection loop will be active again. If load is not detected, then the Channel will move to Device
Unplug Mode and monitor the load continuously. If load is detected, it will return to Low Power Mode and receiver detection will be
active again per 6ms.
Table 4-6. The I/O termination resistance under different conditions
Symbol
Parameter
Resistance
Units
Rin-pd
Input resistance at power down mode
67k to GND
Ω
Rin-U0
Input resistance at U0 condition
50 to VDD
Ω
Rin-U1
Input resistance inU1
50 to VDD
Ω
Rin-U2/U3
Input resistance in U2/U3
50 to VDD
Ω
Rin-RXDet
Input resistance in RXDET
67k to VbiasRx
Ω
RX terminal
(1)
(1)
(1)
TX terminal
Rout-pd
Output resistance at power down mode
HIZ
Ω
Rout-U0
Output resistance at U0 condition
50 to VbiasTx1
Ω
Rout-U1
Output resistance in U1 mode
4.5k to VbiadTx1
Ω
Rout-U2/U3
Output resistance in U2/U3 mode
4.5k to VbiasTx2
Ω
Rout-RXDet
Output resistance in RXDET mode (1)
4.5k to VbiasTx2
Ω
(1)
(1)
Notes: (1) The value of Rin-RxDet will be updated only after the receiver evaluation has been done. Thus, the value can be 50Ω or 67kΩ pull-low.
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4.6 DisplayPort mode
By default, all channels will go to active modes if IN_HPD = 1. The ON/OFF of each DP channel is controlled by the Aux lane count.
4.6.1 DisplayPort Main Link
The electrical sub-block of a DP Main-Link consists of up to four differential pairs. The DP TX drives doubly terminated, AC-coupled
differential pairs, as shown in Figure 3-34 in a manner compliant with the Main-Link Transmitter electrical specification.
Upstream device
Sink
Connector
ML_TX_x_n
50Ω
Tx
Downstream device
ML_RX_x_n
Vbias_Tx
Vbias_Rx
50Ω
ML_TX_x_p
50Ω
Rx
50Ω
ML_RX_x_p
Source
Connector
Sink
Connector
ML_TX_x_n
50Ω
Tx
100k-1MΩ
Vbias_Tx
50Ω
ML_RX_x_n
Vbias_Rx
50Ω
Rx
50Ω
ML_TX_x_p
Source
Connector
100k-1MΩ
ML_RX_x_p
Figure 4-2 DisplayPort Main Link Connection Diagram
Table 4-7. DP Low Power Mode Description
PM_State
Mode
Description
1
Active mode
Data transfer (normal operation);
The AUX monitor is actively monitoring for Link Training unless it is disabled through I2C
interface. At power-up all Main Link outputs are Enabled by default. AUX Link Training is
necessary to overwrite the DPCD registers to Enable/Disable Main Link outputs.
2
Standby mode
Low power consumption (I2C interface is active; AUX monitor is inactive); Main Link outputs
are disabled; the Sink device has de-asserted HPD
3
Power down
mode(OFF)
Lowest power consumption (EN = 0); all outputs are high-impedance; I2C interface is turned
off, all inputs are ignored, I2C register is reset and AUX DPCD is reset:
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Power-up
EN = 0
Power Down
Mode
D3 Power Saving
Mode
HPD low
for >tHPD
EN = 1
EN = 0
Enter D3
Aux Cmd
Standby Mode
Exit D3
Aux Cmd
EN = 0
HPD high
Aux link
training
started
HPD low
for >tHPD
Active Mode
Figure 4-3 DisplayPort Operation mode
4.6.2 DisplayPort Aux Channel
The AUX CH of DP is a half-duplex, bidirectional channel. The DP device with DPTX such as a Source device is the master of the
AUX CH (called AUX CH Requester), while the device with DPRX such as a Sink device is the slave (AUX CH Replier). As the master, the Source device must initiate a Request Transaction, to which the Sink device responds with a Reply Transaction.
The system design of a DFP_D on a USB Type-C connector connected to a UFP_D on a USB Type-C connector using a USB Type-C
to USB Type-C Cable. The 2MΩ pull-down resistors on SBU1 and SBU2 are representative of the leakage of ESD and EMI/RFI
components including termination to ensure no floating nodes, and are intended to show compliance with SBU Termination in USB
Type-C r1.1. The plug orientation switch may be replaced by AUX polarity inversion logic in the DisplayPort transmitter or receiver,
controlled by the plug orientation detection mechanism associated with the USB Type-C Receptacle. Note: The 3.3V levels in the
Adaptors are derived from VCONN because not all DisplayPort UFP_D devices provide DP_PWR.
DislayPort Tx
AUX_CH_P
USB Type-C DFP_D
C_AUX
50Ω
AUX_CH_P
SB1
75-200nF
100kΩ
Vbias_Tx
50Ω
75-200nF
3.3V
100kΩ
AUX_CH_N
SB2
2MΩ
2MΩ
AUX_CH_N
SB2
C_AUX
AUX_CH_N
Plug
Orientation
Switch
DislayPort Rx
USB Type-C UFP_D
2MΩ
75-200nF
1MΩ
Plug
Orientation
Switch
50Ω
Vbias_Tx
50Ω
AUX_CH_P
SB1
2MΩ
C_AUX
75-200nF
C_AUX
3.3V
USB Type-C
to USB Type-C
Cable
Figure 4-4 AUX Signaling Using USB Type-C to USB Type-C Cables
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C_AUX
50Ω
Tx
Vbias_Tx
C_AUX
AUX+
10-105kΩ
2.5~3.3V
1MΩ
Vbias_Rx
50Ω
1MΩ
50Ω
Rx
DP_PWR
50Ω
10-105kΩ
C_AUX
C_AUX
AUXSource
Connector
Sink
Connector
Rx
Tx
Figure 4-5 DisplayPort Aux Channel Connection
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4.7 I2C Programming
4.7.1 I2C Address
Table 4-8. I2C Address bits
Register Bits
Bit7
Slave address (First byte
is slave address)
Bit6
1
Bit5
0
Bit4
1
Bit3
0
Note: A0, A1, A2 are pin-strapping selectable
A2
Bit2
A1
Bit1
A0
Bit0
0/1
(W/R)
4.7.2 I2C Feature Summary
•
•
•
•
•
•
•
•
•
I2C interface operates as a slave device.
The device supports Bulk read/write
Support operating speed up to 1MHz
Supported 7-bit addressing
The data byte format is 8-bit bytes with the most significant bit (MSB) first.
Will never hold the clock line SCL LOW to force the master into a wait state.
No response when the data on common bus is matched to the device address.
When I2C_EN=0, all registers become RO byte.
If I2C master want read/write invalid register, i.e. the I2C slave just write/read from a dummy RO register with FF by default.
4.7.3 Acknowledge
Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge
clock pulse, it will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period
of this clock pulse as indicated in the I2C Data Transfer diagram. It will generate an acknowledge after each byte has been received.
4.7.4 Data Transfer
A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, it will watch the next byte of information
for a match with its address setting. When a match is found it will respond with a read or write of data on the following clocks. Each
byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. Data is transferred
with the most significant bit (MSB) first. It will never hold the clock line SCL LOW to force the master into a wait state.
4.7.5 Start & Stop Condition
A HIGH to LOW transition on the SDA line, while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the
SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below
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date transferred (n bytes + acknowledge)
S
W
Slave Address
A
DATA
...
A
A/A
DATA
P
“0” (write)
A master-transmitter addressing a slave receiver with a 7-bit address. The transfer direction is not changed
date transferred (n bytes + acknowledge)
S
R
Slave Address
A
DATA
...
A
A
DATA
P
“1” (read)
A master reads a slave immediately after the first byte.
read
or write
(n bytes
+ ack)
S
Slave
Address
R/W
A
DATA
A/A
Slave
Address
S
R/W
(n bytes
+ ack)
A
DATA
A/A
P
direction of transfer
may chnage at this time
read or write
Combined format
From master to slave
A= acknowledge
A= not acknowledge
From slave to master
S= start condition
P= stop condition
Figure 4-6 Block read/write protocol
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4.8 Detail Programming Registers
4.8.1 Register Default Summary
Table 4-9. Programming Register Map
Byte
Read after
power up
CONF[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
03h
1
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
11h
2
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
20h
3
00h
00h
10h
20h
30h
40h
50h
60h
70h
80h
90h
A0h
B0h
C0h
D0h
E0h
F0h
4
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
5
03h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
6
03h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
7
03h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
8
03h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
07h
9
60h
60h
62h
68h
67h
00h
0Eh
48h
27h
21h
4Eh
60h
63h
00h
00h
00h
00h
10
FCh
FCh
FCh
FCh
FCh
42h
42h
FCh
42h
42h
FCh
FEh
Feh
42h
7Fh
7Eh
42h
11
FCh
FCh
FCh
FCh
FCh
42h
42h
42h
FCh
FCh
42H
FEh
Feh
42h
7Fh
42h
7Eh
12
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
58h
13
00h
00h
00h
FFh
FFh
00h
00h
F0h
0Fh
0Fh
F0h
FFh
FFh
00h
00h
00h
00h
14
FFh
FFh
FFh
00h
00h
33h
CCh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
15
C8h
C8h
C8h
C8h
C8h
C8h
C8h
59h
C8h
C8h
C8h
C8h
C8h
C8h
C8h
C8h
C8h
D3h
16
DCh
DCh
DCh
5Ch
5Ch
D3h
D3h
DCh
56h
56h
59h
5Ch
5Ch
D3h
D3h
D3h
17
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
14h
18
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
04h
19
~30
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
31
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
01h
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4.8.2 BYTE 0 (Revision and Vendor ID Register)
Bit
Type
Power up condition
7
RO
0
6
RO
0
5
RO
0
4
RO
0
3
RO
0
2
RO
0
1
RO
1
0
RO
1
Control affected
Comment
Revision ID
Rev# = 0000
Vendor ID
Pericom
4.8.3 BYTE 1 (Device Type/Device ID register)
Bit
Type
Power up condition
7
RO
0
6
RO
0
5
RO
0
4
RO
1
3
RO
0
2
RO
0
1
RO
0
0
RO
1
Control affected
Comment
Device Type
Device Type
Active Mux = 0001
Device ID
Device ID
PI3DPX1207 = 0001
4.8.4 BYTE 2 (Byte count register)
Bit
Type
Power up condition
7
RO
0
6
RO
0
5
RO
1
4
RO
0
3
RO
0
2
RO
0
1
RO
0
0
RO
0
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Control affected
Comment
Register Byte count
I2C byte count = 32 bytes
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4.8.5 BYTE 3 (Mode control)
If I2C_EN=0, this byte is Read Only register. If I2C_EN=1, This byte is Read/Write register.
Bit
Type
Power up condition
Default
7
R/W
0
0
CONF
6
R/W
Latch
0
CONF
5
R/W
Latch
0
CONF
4
R/W
Latch
0
CONF
3
R/W
0
0
Reserved
PIN_RXDET_EN#
Inverted version of Pin9
RXDET_EN
2
R/W
Latch
0
1:0
R/W
0
0
Control affected
Comment
Channel Preset assignment for the Preset
Application Mode,
Far end Receiver termination detection Enable (Active Low)
0 - Detection is enabled.
1 - Detection is disabled.
Reserved
4.8.6 BYTE 4 (Override the power down control)
If I2C_EN=0, this byte is Read Only register. If I2C_EN=1, this byte is Read/Write register.
Bit
Type
Power up condition
7
R/W
Latch EN pin
0
PD_CON_RX1
6
R/W
Latch EN pin
0
PD_CON_TX1
5
R/W
Latch EN pin
0
PD_CON_TX2
4
R/W
Latch EN pin
0
PD_CON_RX2
3
R/W
1
1
Reserved
2
R/W
1
1
Reserved
1
R/W
0
0
IN_HPD_ActiveHigh_
EN#
0
R/W
1
1
Reserved
PI3DPX1207B
Document number DS39965 Rev 4-2
Default
Control affected
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Comment
CONx power down override
0 – Normal operation
1 – Force the CONx to power down state
0 - IN_HPD Active High
1 - IN_HPD Active Low
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PI3DPX1207B
4.8.7 BYTE 5 (Equalization, Flat gain and -1dB linear Swing setting of CON_RX2)
If I2C_EN=0, this byte is Read Only register. If I2C_EN=1, this byte is Read/Write register.
Bit
Type
Power up condition
Default
Control affected
7
R/W
Latch EQ
0
CON_RX2_EQ
6
R/W
Latch EQ
0
CON_RX2_EQ
5
R/W
Latch EQ
0
CON_RX2_EQ
4
R/W
Latch EQ
0
CON_RX2_EQ
3
R/W
Latch_FG
0
CON_RX2_FG
2
R/W
Latch_FG
1
CON_RX2_FG
1
R/W
Latch_SW
1
CON_RX2_SW
0
R/W
Latch_SW
1
CON_RX2_SW
Comment
CON_RX2 setting configuration
Equalizer
Flat gain
Swing
4.8.8 BYTE 6 (Equalization, Flat gain and -1dB linear Swing setting of CON_TX2)
If I2C_EN=0, this byte is Read Only register. If I2C_EN=1, this byte is Read/Write register.
Bit
Type
Power up condition
Default
Control affected
7
R/W
Latch EQ
0
CON_TX2_EQ
6
R/W
Latch EQ
0
CON_TX2_EQ
5
R/W
Latch EQ
0
CON_TX2_EQ
4
R/W
Latch EQ
0
CON_TX2_EQ
3
R/W
Latch_FG
0
CON_TX2_FG
2
R/W
Latch_FG
1
CON_TX2_FG
1
R/W
Latch_SW
1
CON_TX2_SW
0
R/W
Latch_SW
1
CON_TX2_SW
Comment
CON_TX2 setting configuration
Equalizer
Flat gain
Swing
4.8.9 BYTE 7 (Equalization, Flat gain and -1dB linear Swing setting of CON_TX1)
If I2C_EN=0, this byte is Read Only register. If I2C_EN=1, this byte is Read/Write register.
Bit
Type
Power up condition
7
R/W
Latch EQ
0
CON_TX1_EQ
6
R/W
Latch EQ
0
CON_TX1_EQ
5
R/W
Latch EQ
0
CON_TX1_EQ
4
R/W
Latch EQ
0
CON_TX1_EQ
3
R/W
Latch_FG
0
CON_TX1_FG
2
R/W
Latch_FG
1
CON_TX1_FG
1
R/W
Latch_SW
1
CON_TX1_SW
0
R/W
Latch_SW
1
CON_TX1_SW
PI3DPX1207B
Document number DS39965 Rev 4-2
Default
Control affected
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Comment
CON_TX1 setting configuration
Equalizer
Flat gain
Swing
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Diodes Incorporated
PI3DPX1207B
4.8.10 BYTE 8 (Equalization, Flat gain and -1dB linear Swing setting of CON_RX1)
If I2C_EN=0, this byte is Read Only register. If I2C_EN=1, this byte is Read/Write register.
Bit
Type
Power up condition
Default
Control affected
7
R/W
Latch EQ
0
CON_RX1_EQ
6
R/W
Latch EQ
0
CON_RX1_EQ
5
R/W
Latch EQ
0
CON_RX1_EQ
4
R/W
Latch EQ
0
CON_RX1_EQ
3
R/W
Latch_FG
0
CON_RX1_FG
2
R/W
Latch_FG
1
CON_RX1_FG
1
R/W
Latch_SW
1
CON_RX1_SW
0
R/W
Latch_SW
1
CON_RX1_SW
Comment
CON_RX1 setting configuration
Equalizer
Flat gain
Swing
4.8.11 BYTE 9 (RESERVED)
4.8.12 BYTE 10 (Feature control of the CON_RX2 and CON_TX2)
•
CON2 represents CON_RX2 and CON_TX2
Bit
Type
Power up condition
7
R/W
1
CON2 Feature 0
6
R/W
1
CON2 Feature 1
5
R/W
1
CON2 Feature 2
4
R/W
1
CON2 Feature 3
3
R/W
1
CON2 Feature 4
2
R/W
1
CON2 Feature 5
1
R/W
0
CON2 Feature 6
0
R/W
0
CON2 Feature 7
PI3DPX1207B
Document number DS39965 Rev 4-2
Control affected
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Comment
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PI3DPX1207B
4.8.13 BYTE 11 (Feature control of the CON_RX1 and CON_TX1)
CON1 represents CON_RX1 and CON_TX1
Bit
Type
Power up condition
Control affected
7
R/W
1
CON1 Feature 0
6
R/W
1
CON1 Feature 1
5
R/W
1
CON1 Feature 2
4
R/W
1
CON1 Feature 3
3
R/W
1
CON1 Feature 4
2
R/W
1
CON1 Feature 5
1
R/W
0
CON1 Feature 6
0
R/W
0
CON1 Feature 7
Comment
4.8.14 BYTE 12 (Threshold, feature Enable/Disable and timing setting)
Bit
Type
Power up condition
Control affected
Comment
7
R/W
0
IDET_VTH
6
R/W
1
IDET_VTH
High Speed channel signal detector threshold setting
00 50mVppd
01 65mVppd (Default)
10 80mVppd
11 95mVppd
5
R/W
0
Reserved
4
R/W
1
Reserved
3
R/W
1
Reserved
2
R/W
0
DP_HPD_PIN_EN#
Enable the IN_HPD Pin, so the redriver will response to
this pin.
0 – Enabled
1 – Disabled
1
R/W
0
AUX _EN#
Enable/Disable the AUX Mux
0 – Enabled
1 – Disabled
0
R/W
0
Reserved
4.8.15 BYTE 13 - 31 : Reserved
PI3DPX1207B
Document number DS39965 Rev 4-2
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PI3DPX1207B
5. Electrical Specification
5.1 Absolute Maximum Ratings
Supply Voltage to Ground Potential..............................................................................................................................–0.5 V to +3.8 V
DC SIG Voltage....................................................................................................................................................... –0.5 V to VDD + 0.5 V
CML Continuous Output Current....................................................................................................................................+30 to +30mA
Storage Temperature.....................................................................................................................................................–65 °C to +150 °C
Junction Temperature........................................................................................................................................................................125°C
ESD HBM.........................................................................................................................................................................................±2000V
ESD CDM...........................................................................................................................................................................................±500V
Note:
(1) Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to beyond the absolute maximum rating conditions for extended periods may affect inoperability and degradation of device reliability and performance.
5.2 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
Symbol
Parameter
VDD
VDD Supply Voltage
VDD_I2C
VDD I2C Supply Voltage
VNOISE
Supply Noise up to 50 MHz
TA
Min.
Typ.
Max
Units
3.0
3.3
3.6
V
3.6
V
mVpp
100
(1)
Ambient Temperature, Commercial C-temp range
Ambient Temperature, Industrial I-temp range
0
70
-40
(2)
Notes:
(1) Allowed supply noise (mVpp sign wave) under typical condition
(2) Industrial temperature -40 to +85 oC can be guaranteed by design. Commercial temperature 0 to +70 oC is supported by the production-tested.
C
o
85
5.3 Thermal Information
Symbol
Parameter
Theta JA
Junction-to-ambient resistance
35.34
o
Theta JC
Junction-to-case (top) thermal resistance
15.17
o
PI3DPX1207B
Document number DS39965 Rev 4-2
42-pin TQFN
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Unit
C/W
C/W
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PI3DPX1207B
5.5 Power Consumption
Over operating temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
IPD
Typical Pin Power Down current,
VDD=3.3V
IDDQ_PD
I2C Power Down current,
VDD=3.3V
Min.
Typ.
Max
Units
EN = 0
26
100
µA
EN=1, I2C Byte4=1111
112
340
µA
1-lane DP
33
55
mA
2-lane DP
66
110
mA
4-lane DP
132
210
mA
DP1.4 Mode
IDD_DP
Power supply current in DP mode
EN =1, VDD=3.3V
1-lane USB 3.1 Gen2 Mode
IU0
Current in USB U0 mode,
VDD=3.3V
EN=1, USB U0 mode
80
112
mA
IU1
Current in USB U1 mode,
VDD=3.3V
EN=1, USB U1 mode
16
20
mA
IU2/U3
Current in USB U2/U3 modes. VDD=3.3V
EN=1, USB U2/U3 mode
0.5
0.6
mA
IRXDET
Current in USB RXDET mode, VDD=3.3V
EN=1, USB RXDET mode
0.5
0.6
mA
5.6 AC/DC Characteristics
Over operating temperature range (unless otherwise noted)
5.6.1 LVCMOS I/O DC Specifications
Symbol
Parameter
Min.
Typ.
Max
Unit
2-level control pins
VIH
DC input logic High
VDD*0.65
V
VIL
DC input logic Low
VDD*0.35
V
IIH
Input High current
25
uA
IIL
Input Low current
-25
uA
4-level control pins
VIH
DC input logic "High"
0.92*VDD
VDD
VIF
DC input logic "Float"
0.59*VDD
0.67*VDD
0.75*VDD
V
VIR
DC input logic "With Rext to GND"
0.25*VDD
0.33*VDD
0.41*VDD
V
VIL
DC input logic "Low"
GND
0.08*VDD
V
IIH
Input High current
50
uA
IIL
Input Low current
REXT
External resistor connects to GND (±5%)
PI3DPX1207B
Document number DS39965 Rev 4-2
-50
uA
68
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V
kΩ
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PI3DPX1207B
5.6.2 USB Differential Channel
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
1.0
pF
USB differential Input
CRXPARASITIC
The parasitic capacitor for RX
RRX-DIFF-DC
DC Differential Input Impedance
RRX-CM_DC
DC common mode input impedance
DC impedance limits are need to
guarantee RxDet. Measured with
respect to GND over a voltage of
500mV max
ZRX-HIZ-DC-PD
DC input CM input impedance for
V>0 during reset or power down
(Vcm=0 to 500mV)
CAC_COUPLING
AC coupling capacitance
VRX-CM-AC-P
Common mode peak voltage
Common mode peak voltage(1)
VRX-CM-DC-ActiveIdle-Delta-P
72
120
18
30
25
75
Ω
kΩ
265
nF
AC up to 5GHz
150
mVpeak
Between U0 and U1. AC up to
5GHz
200
mVpeak
Differential Swing |VTX-D+-VTX-D-|
1.2
Vppd
120
Ω
600
mV
265
nF
USB differential Output
VTX-DIFF-PP
Output differential p-p voltage swing
RTX-DIFF-DC
DC Differential TX Impedance
VTX-RCV-DET
The amount of voltage change allowed during RxDet
Cac_coupling
AC coupling capacitance
TTX-EYE(10Gbps)
Transmitter eye, Include all jitter
At the silicon pad. 10Gbps
0.646
UI
TTX-EYE(5Gbps)
Transmitter eye, Include all jitter
At the silicon pad. 5Gbps
0.625
UI
TTX-DJ-DD(10Gbps)
Transmitter deterministic jitter
At the silicon pad. 10Gbps
0.17
UI
TTX-DJ-DD(5Gbps)
Transmitter deterministic jitter
At the silicon pad. 5Gbps
0.205
UI
CTXPARASITIC
The parasitic capacitor for TX
1.1
pF
RTX-CM_DC
Common mode DC output Impedance
18
30
Ω
VTX-DC-CM
The instantaneous allowed DC common mode voltage at the connector
side of the AC coupling capacitors
|VTX-D++VTX-D-|/2
0
2.2
V
VTX-C
Common-Mode Voltage
|VTX-D++VTX-D-|/2
VDD2V
VDD
V
VTX-CM-AC-PP-
Active mode TX AC common mode
voltage
VTX-D++VTX-D- for both time and
amplitude
100
mVpp
Between U0 to U1
200
mVpeak
Active
VTX-CM-DC-Active_Idle-Delta
Common mode delta voltage
|Avguo(|VTEX-D+ + VTX-D-|)/2-Avgu1(|VTX-D+ +
VTX-D-|)/2|
PI3DPX1207B
Document number DS39965 Rev 4-2
72
75
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PI3DPX1207B
Symbol
VTX-Idle-Diff-AC-pp
VTX-Idle-Diff-DC
Parameter
Conditions
Max.
Unit
Idle mode AC common mode delta
voltage|VTX-D+-VTX-D-|
Between Tx+ and Tx- in idle
mode. Use the HPF to remove
DC components. =1/LPF. No AC
and DC signals are applied to Rx
terminals .
10
mVppd
Idle mode DC common mode delta
voltage|VTX-D+-VTX-D-|
Between Tx+ and Tx- in idle
mode. Use the LPF to remove
DC components. =1/HPF. No
AC and DC signals are applied
to Rx terminals.
10
mV
Peaking gain (Compensation at
5GHz, relative to 100MHz, 100mVp-p
sine wave input)
Gp
EQx=0
EQx=R
EQx=F
EQx=1
Variation around typical
GF
Flat gain (100MHz, EQx=F, SWx=F)
Min.
5.7
8.9
11.1
12.6
-3
FGx=0
FGx=R
FGx=F
FGx=1
Variation around typical
Typ.
dB
+3
-1.5
0
+1
+2.5
-3
dB
dB
+3
dB
VSW_100M
-1dB compression point output
swing (at 100MHz)
SWx=0
SWx=1
900
1000
mVppd
VSW_5G
-1dB compression point output
swing (at 5GHz)
SWx=0
SWx=1
600
750
mVppd
DDNEXT(2)
Differential near-end crosstalk
100MHz to 5GHz
-45
dB
DDFEXT
Differential far-end crosstalk
100MHz to 5GHz
-45
dB
100MHz to 5GHz, FGx=1, EQx=R, SW=F
0.6
100MHz to 5GHz, FGx=1,
EQx=1, SW=F
0.5
100MHz to 5GHz, FGx=1, EQx=R, SW=F
0.8
(2)
VNOISE-INPUT
VNOISE-OUTPUT
S11
S22
Input-referred noise
Output-referred noise2
Input return loss
Output return loss
PI3DPX1207B
Document number DS39965 Rev 4-2
100MHz to 5GHz, FGx=1,
EQx=1, SW=F
mVRMS
mVRMS
1
10 MHz to 4.1 GHz differential
-13.0
1 GHz to 4.1 GHz common
mode
-5.0
10 MHz to 4.1 GHz differential
-15
1 GHz to 4.1 GHz common
mode
-6.0
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dB
dB
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PI3DPX1207B
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Signal and Frequency Detectors
VTH_UPM
Unplug mode detector threshold
Threshold of LFPS when the
input impedance of the redriver
is 67kohm to VbiasRx only. Used
in the unplug mode.
VTH_DSM
Deep slumber mode detector threshold
LFPS signal threshold in Deep
slumber mode
100
600
mVppd
VTH_AM
Active mode detector threshold
Signal threshold in Active and
slumber mode
65
175
mVppd
FTH
LFPS frequency detector
Detect the frequency of the input
CLK pattern
100
400
MHz
TON_UPM
Turn on of unplug mode
3
mS
TON-DSM
Turn on of deep slumber mode
5
µS
TON_SM
Turn on of slumber mode
20
ns
TX pin to RX pin latency
when input signal is LFPS
200
800
mVppd
Note:
(1) Measured using a vector-network analyzer (VNA) with -15dbm power level applied to the adjacent input. The VNA detects the signal at the output of the victim
channel. All other inputs and outputs are terminated with 50Ω.
(2) Subtract the Channel Gain from the Total Gain to get the Actual Crosstalk
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5.6.3 DisplayPort Differential Channel
Symbol
Parameters
Typ.
Max.
Units
VID
Peak to peak differential input voltage
400
1200
mV
VODO
Differential overshoot voltage
15%*V3P3
V3P3
VODU
Differential undershoot voltage
25%*V3P3
V3P3
Isc
Output short current
60
mA
Vtx diff-lev1
Differential pk-pk level 1
340
400
460
mV
Vtx diff-lev2
Differential pk-pk level 2
510
600
680
mV
Vtx diff-lev3
Differential pk-pk level 3
690
800
920
mV
Vtx diff-lev4
Differential pk-pk level 4
1020
1200
1380
mV
GP
Condition
Min.
EQx=0
EQx=R
EQx=F
EQx=1
Peaking gain: Compensation at
4 GHz, relative to 100 MHz, 100
mVp-p sine wave input
4.9
7.7
9.8
11.3
Variation around typical
GF
Flat gain:
100 MHz, EQ[3:0] = 1000, SW[1:0]
= 10
-3
dB
+3
FGx=0
FGx=R
FGx=F
FGx=1
+1
-1.5
0
2.5
Variation around typical
-3
dB
+3
SWx = 0
SWx = 1
dB
dB
V1dB_100M
-1 dB compression point of output
swing at 100 MHz
TR /TF
Rise and Fall Time
TSK(D)
Intra-pair differential skew
50
ps
TSK(O)
Intra-pair differential skew
50
ps
20% to 80 %
1100
1200
mVppd
30
ps
5.6.4 Hot Plug/Unplug Detect Circuitry
Parameter
Min
HPD Voltage
2.25
Hot Plug Detection Threshold
2.0
Hot Unplug Detection Threshold
Max
Unit
3.6
V
200
HPD de-assert debounce timer
200
Notes
V
0.8
HPD pin Termination
PI3DPX1207B
Document number DS39965 Rev 4-2
Typ
450
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V
kΩ
To GND
ms
Any HPD Low to High edge will reset the
debounce timer
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PI3DPX1207B
JBERT (No Pre-emphasis)
Trace Card
Char Board(DUT)
Trace Card
Oscilloscope
Ch1
Ch1
Ch2
SMA
cable
DUT
SMA
cable
TP1
Ch2
SMA
cable
TP2
TP3
TP4
1) Trace card between TP1 and TP2 is designed to emulate 6-48” of FR4. Trace width -4 mils,100Ω differnetial impedance
2) All jitter is measured at a BER of 10-9
3) Residual jitter reflects the total jitter measured at TP4 jitter minus TP1 jitter
4) VDD = 3.3V, RT = 50Ω
5) The input signal from JBERT does not have any pre-emphasis.
Figure 5-1 AC Electrical Parameter test setup
Upstream device
Sink
Connector
ML_TX_x_n
50Ω
Tx
Downstream device
ML_RX_x_n
Vbias_Tx
Vbias_Rx
50Ω
ML_TX_x_p
50Ω
Rx
50Ω
ML_RX_x_p
Source
Connector
Sink
Connector
ML_TX_x_n
50Ω
Tx
100k-1MΩ
Vbias_Tx
50Ω
ML_RX_x_n
Vbias_Rx
50Ω
Rx
50Ω
ML_TX_x_p
100k-1MΩ
Source
Connector
ML_RX_x_p
Figure 5-2 High-speed Chanel Test Circuit
Output Intra-Pair Skew
OUTxP
50%
OUTxN
Output Inter-Pair Skew
OUTyP
OUTyN
Figure 5-3 Intra and Inter-pair Differential Skew definition
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Common Mode Voltage
VCM = (|VD+ + VD-| / 2)
VCMP = (max |VD+ + VD-| / 2)
VD+
VCM
VDIFF
VD-
DIFFp-p
Symmetric Differential Swing
VDIFFp-p = (2 * max |VD+ - VD-|)
Asymmetric Differential Swing
VDIFFp-p = (max |VD+ - VD-| {VD+ > VD-}
+ max |VD+ - VD-| {VD+ < VD-})
0V
VDIFFP-P
tPLH
tPHL
80%
80%
0V
VDIFFP-P
20%
20%
tf
tr
Figure 5-4 Definition of Peak-to-peak Differential voltage
VOUT
AP_RXA
EQ=H
CON_TXA
TX channel
VIN
AP_TXB
output swing
= 1V (0dBV)
VIN
NEXT
Xtalk
CON_RXB
EQ=H
VOUT
RX channel
Host(APU/CPU)
ReDriver
Device
Figure 5-5 NEXT Crosstalk definition
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50Ω
RX1+
TX1+
50Ω
AGGRESSOR SIGNAL (-15Bm)
RX1-
4-PORT
VECTOR
NETWORK
ANALYZER
N52454
TX150Ω
TX2+
RX2+
TX2-
RX2-
50Ω
NEXT XTALK OUTPUT
Figure 5-6 Channel-isolation test configuration
50Ω
50Ω
RX_+
TX_+
RX_-
TX_-
BALUN
PSPL 5315A
(200kHz TO 17GHz)
POWER METER
GIGATRONICS 8652A
WITH 80301A HEAD (10MHz
to 18GHz)
Figure 5-7 Noise test configuration
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5.6.5 I2C Bus SCL/SDA Specification
Symbol
Parameter
VIL
DC input logic LOW
VIH
DC input logic HIGH
VOL1
DC output logic LOW voltage
IOL
LOW-level output current
Ii
Input current each I/O pin
CI
Capacitance for each I/O pin
fSCL
Bus Operation Frequency
tBUF
Bus Free Time Between Stop and Start condition
tHD:STA
Hold time after (Repeated) Start condition.
After this period, the first clock is generated.
tSU:STA
Conditions
Min.
Max
Units
-0.5
0.4
V
1.2
VDD
V
(open-drain or open-collector)
at 3 mA sink current;
0
0.4
V
VOL = 0.4V
20
mA
VOL = 0.6V
6
mA
-10
Typ.
10
uA
10
pF
1000
KHz
1.3
us
0.6
us
Repeated start condition setup time
0.26
us
tSU:STO
Stop condition setup time
0.26
us
tHD:DAT
Data hold time
0
ns
tSU:DAT
Data setup time
50
ns
tLOW
Clock Low period
0.5
us
tHIGH
Clock High period
0.26
tF
tR
At Ipull-up, Max
50
us
Clock/Data fall time
120
ns
Clock/Data rise time
120
ns
Notes:
(1) Recommended value.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Compliant to I2C physical layer specification.
(4) VIL = 0.4V and VIH = 1.2V because the silicon needs to support both SCL/SDA with 1.8V/3.3V signaling level.
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STOP
START
START
SDA
tf
tSU;DAT
tLOW
tf
tr
t HD;STA
tBUF
SCL
S
tHD;STA
tHD;DAT
HIGH
t SU;STA
Sr
t SU;STO
P
S
Figure 5-8 Definition of timing for F/S-mode on the I2C-bus
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6. Applications
Note:
Information in the following applications sections is not part of the component specification, and does not warrant its accuracy or completeness. Customers are responsible for determining suitability of components for their purposes. Customers
should validate and test their design implementation to confirm system functionality.
6.1 Channel connection diagram
Upstream
Device
AP_RX2P
PI3DPX1207
AP_RX2N
RXBP
RXBN
AP_TX2P
AP_TX2N
TXAN
TXAP
AP_RX1N
AP_RX1P
CON_TX1N
CON_TX1P
AP_TX1N
AP_TX1P
CON_RX1N
CON_RX1P
RXAN
RXAP
Connector
CON_TX2P
CON_TX2N
TXBP
TXBN
CON_RX2P
CON_RX2N
Upstream
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
Downstream
Figure 6-1 Source-side Host to USB Type-C Connector connection diagram
6.2 Type-C AC-cap connection diagram
CON_TX1
Tx
USB PHY
Rx
Tx
Flip
Switch
Flip
Switch
Rx
USB PHY
CON_TX2
CON_RX1
DP PHY
Flip
Switch
Flip
Switch
DP PHY
Passive Cable
Transmitter-IC
Type-C
ReDriver
Type-C
ReDriver
CON_RX2
Source-side system
Sink-side system
Receiver-IC
Note: AC-cap is recommanded for potential Type-C Sink Device compatibility (interoperability) issues because of the different Type-C legacy implementation, not latest Type-C Logo
compiant devices.
Figure 6-2 AC-capacitor circuits in the high speed channel for Type-C and DP-captive cable
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6.3 SiGe BiCMOS vs. CMOS Redrivers Jitter performance
Linear SiGe Redriver jitter test result was shown below. As known, SiGe Redriver can cover most of the Notebook PC routing trace
length.
Figure 6-3 SiGe BiCmos vs CMOS Redriver performance comparison
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6.4 Redriver Placement Consideration
6.4.1 USB3.1 10Gbps System Design Challenges
•
•
Jitter budget is basis for Tx and Rx compliance specs.
Loss budget is basis for compliance channels, including pad cap, package, PCB routing
Table 6-1. USB channel Jitter Budget
DJ (ps)
RJ (ps)
14.1
TJ (ps)
Term
Comments
31.1
Transmitter
Practical route length is 0)
return data[N];
return res;
}
6.8.3 I2C Multi-Byte Write compared to I2C Block Write using i2c_smbus_write_i2c_block_data()
Example:
//Write PI3DPX1207 I2C reg from BYTE0 to BYTE len-1
//return value: no of byte written
int pi3dpx1207_writen( struct i2c_client *client, u8 len, u8 *val)
{
//Write I2C Byte0 to Byte len-1
If (len >1)
return i2c_smbus_write_i2c_block_data(client, *val[0], len, val[1]);
return i2c_smbus_write_byte(client, *val[0]);
}
//Write PI3DPX1207 I2C reg Byte N
//return value: no of byte written
int pi3dpx1207_write( struct i2c_client *client, u8 N, u8 val)
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{
u8 data[N+1];
int res;
//Read I2C Byte0 to Byte N
res = pi3dpx1207_readn(client, N+1, &data);
if (res >0)
{
data[N]=val;
return pi3dpx1207_writen(client, N+1, &data);
}
return res;
}
6.8.4 Read/Write Byte 3 with OP_MODE 0x03[7:4] to set channel mapping control CONF[3:0]
• 0000 Safe State
• 0001 Safe State
• 0010 4 lane DP1.4 + AUX
• 0011 4 lane DP1.4 + AUX Flipped
• 0100 1 lane USB3.x (AP_CH1)
• 0101 1 lane USB3.x (AP_CH1) Flipped
• 0110 USB3 (AP_CH1) + 2 lane DP1.4 (AP_CH2) + AUX
• 0111 USB3 (AP_CH1) + 2 lane DP1.4 (AP_CH2) + AUX Flipped
Example:
//Write PI3DPX1207 Byte 3 to set channel mapping control
//input: confg
//return value: no of byte written
int pi3dpx1207_set_channel_mapping (struct i2c_client *client, u8 confg)
{
//Read byte 3
int reg = pi3dpx1207_read(client, 3)
if (reg < 0)
return 0;
reg &= 0x0F;
reg |= (confg >4);
}
return reg;
}
6.8.5 Write Byte 4 with PD_CONx[7:4] and Byte 12 to set HPD state
Example:
const u8 eq_fg_sw[8][6] = {“PI3DPX1207 I2C Setting Table”}
//Write PI3DPX1207 Byte 4 to set HPD state
//return value: no of byte written
int pi3dpx1207_hpd(struct i2c_client *client, u8 hpd)
{
u8 data[13];
//Read byte3
int confg = pi3dpx1207_get_channel_mapping(client);
data[0] = 0;
data[1] = 0;
data[2] = 0;
data[3] = confg;
confg = confg >>4;
data[4] = eq_fg_sw[conf][0];
if (hpd)
{
if ((confg == 2) || (confg ==3))
//If HPD is high, power on DP channels by clear bits[7:4] of byte 4.
data[4] = eq_fg_sw[conf][0] & 0x0F;
else if (confg == 6)
data[4] = eq_fg_sw[conf][0] & 0xCF;
else if (confg ==7)
data[4] = eq_fg_sw[conf][0] & 0x3F;
}
data[5] = eq_fg_sw[confg][1];
data[6] = eq_fg_sw[confg][2];
data[7] = eq_fg_sw[confg][3];
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data[8] = eq_fg_sw[confg][4];
data[9] = 0;
data[10] = 0;
data[11] = 0;
if (hpd)
//If HPD is high, enable IN_HPD pin by clear bit2 of byte12
data[12] = eq_fg_sw[confg][5] & 0xFB;
else
data[12] = eq_fg_sw[confg][5];
res = pi3dpx1207_writen(client,13, &data);
if (res
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