PI3EQX1204-CZHE

A product Line of Diodes Incorporated PI3EQX1204-C 12.5Gbps 4-channel, SAS3 ReDriver with Linear Equalization Features Description ÎÎ1-12.5Gbps serial link with linear equalizer The PI3EQX1204-C is a SAS3, 4 differential channels ReDriver. The device provides programmable linear equalization, output swing and flat gain, by either pin strapping option or I2C Control, to optimize performance over a variety of physical mediums by reducing Inter-symbol interference. ÎÎSupport SATA Gen1/Gen2/Gen3, SAS2/3, and XAUI protocol ÎÎSupporting 4 differential channels ÎÎHandle up to 34dB channel loss (42" FR4 trace or 10 meters or SAS3 cable) ÎÎIndependent channel configuration of receiver equalization, output swing and flat gain ÎÎRate and Coding Agnostic PI3EQX1204-C supports four 100-Ohm Differential CML data I/O’s and extends the signals across other distant data pathways on the user’s platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the ReDriver, whereas the integrated linear amplifier/buffer circuitry provides flexibility with signal integrity of the signal after the ReDriver. ÎÎTransparent to link training, OOB, Idle ÎÎ260mW per channel power dissipation with 700 mVpp output swing ÎÎPin strap and I 2C selectable device programming ÎÎ4-bit selectable address bit for I 2C Application ÎÎSupply Voltage: 3.3V±0.3V Rack Server, JBOD storage ÎÎIndustrial Temperature Range: -40oC to 85oC ÎÎPackaging (Pb-free & Green): àà 42-contact TQFN (9mm x3.5mm) EQ1/AD1 EQ0/AD0 EQ3/AD3 Conditional pullup, 50-Ohm or HIZ Input threshold Detection EQ2/AD2 Pin Configuration (Top-Side View) Block Diagram VCC CML Input buffer I+ Equalizer I- VCC Conditional input Load: 50-Ohm or 200K-ohm PRSNT# Linear Amp Equalization control (4-bits) Power management O+ Buffer OCML output amplifier Flat gain control SW1 SW0 VCC A0RX+ 1 2 3 4 A0RX- 5 6 7 VCC Swing control Flat gain Output Swing control (2-bits) control (2-bits) ^^ Repeats 4x ^^ 42 41 40 39 38 37 36 35 FG1/I2C_RESET# FG0 VCC A0TX+ 34 A0TXVCC A1TX+ A1TXVCC A2TX+ A1RX+ A1RXVCC A2RX+ 8 9 10 33 32 31 30 29 A2RXVCC A3RX+ A3RXVCC 11 12 13 14 15 27 26 25 24 DNC DNC 16 17 22 28 23 A2TXVCC A3TX+ A3TXVCC DNC I2C_DONE PI3EQX1204-C Document number: DS40033 Rev.1-2 1 ENI2C PRSNT# SDA SCL 18 19 20 21 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Pin Description Pin # Pin Name Type Description 4 A0RX+ I 5 A0RX- I CML inputs for Channel A0, with internal 50-Ohm pull-up and ~200K-Ohm pull-up otherwise. 35 A0TX+ O 34 A0TX- O 7 A1RX+ I 8 A1RX- I 32 A1TX+ O 31 A1TX- O 10 A2RX+ I 11 A2RX- I 29 A2TX+ O 28 A2TX- O 13 A3RX+ I 14 A3RX- I 26 A3TX+ O 25 A3TX- O 19 SCL I/O I2C SCL Clock. In Master mode (ENI2C floating), SCL is an output. Otherwise it is an input. 18 SDA I/O I2C SDA data input/output. 42, 41, 40, 39 AD[3:0] I I2C programmable address bits, with internal 100k-Ohm pull-up. Data Signals CML outputs for Channel A0, with internal 50-Ohm pull-up and high impedance otherwise. CML inputs for Channel A1, with internal 50-Ohm pull-up and ~200K-Ohm otherwise. CML outputs for Channel A1, with internal 50-Ohm pull-up and high impedance otherwise. CML inputs for Channel A2, with internal 50-Ohm pull-up and ~200K-Ohm otherwise. CML outputs for Channel A2, with internal 50-Ohm pull-up and high impedance otherwise. CML inputs for Channel A3, with internal 50-Ohm pull-up and ~200K-Ohm otherwise. CML outputs for Channel A3, with internal 50-Ohm pull-up and high impedance otherwise. Control Signals 20 PRSNT# I This pin is active in both PIN mode(ENI2C=LOW) and I2C mode (ENI2C=HIGH). Cable present detect input. This pin has internal 100K-ohm pull-up. When High, a cable is not present, and the device is put in lower power mode. When LOW, the device is enabled and in normal operation. 21 ENI2C I When LOW, each channel is programmed by the external pin voltage. When HIGH, each channel is programmed by the data stored in the I2C bus. When floating, master mode (Read External EEPROM) 42, 41, 40, 39 EQ[3:0] I Inputs with internal 100k-Ohm pull-up. This pins set the amount of Equalizer Boost in all channel when ENI2C is LOW. 1, 2 SW[1:0] I Inputs with internal 100k-Ohm pull-up. This pin sets the output Voltage Level in all channel when ENI2C is LOW. 38, 37 FG[1:0] I Inputs with internal 100KΩ pull up resistor. Sets the output flat gain level on all channels when ENI2C is low. 38 I2C_RESET# I Inputs with internal 100KΩ pull up resistor. Reset pin for I2C. When set low will reset the registers to default state. PI3EQX1204-C Document number: DS40033 Rev.1-2 2 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Pin # Pin Name Type 22 I2C_DONE O 16, 17, 23 Power Pins DNC Description Valid register load status output, use for daisy chain master LOW = External EEPROM load failed HIGH = External EEPROM load passed Do Not Connect 3, 6, 9, 12, 15, 24, 27, 30, 33, 36 VCC PWR 3.3V Supply Voltage EP GND PWR Exposed pad. Supply Ground PI3EQX1204-C Document number: DS40033 Rev.1-2 3 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Description of Operation Power Enable function: One pin control or I2C control, when PRSNT# is set to HIGH, the IC goes into power down mode, both input and output termination set to 200K and High impedance respectively. Individual Channel Enabling is done through the I2C register programming. Equalization Setting: EQ[3:0] are the selection pins for the equalization selection for each channel. Table 1. Equalization Setting Equalizer setting EQ3 EQ2 EQ1 EQ0 @ 3GHz @ 4GHz @ 5GHz @ 6GHz 0 0 0 0 3.6 4.5 5.5 6.8 0 0 0 1 4 5.1 6.2 7.6 0 0 1 0 4.4 5.6 6.9 8.4 0 0 1 1 4.7 6.1 7.5 9.1 0 1 0 0 5.1 6.6 8.1 9.8 0 1 0 1 5.5 7.1 8.7 10.4 0 1 1 0 5.9 7.6 9.2 11 0 1 1 1 6.2 8 9.7 11.5 1 0 0 0 6.6 8.5 10.2 12 1 0 0 1 6.9 8.9 10.7 12.5 1 0 1 0 7.3 9.3 11.1 12.9 1 0 1 1 7.6 9.7 11.5 13.3 1 1 0 0 8 10.1 11.9 13.7 1 1 0 1 8.2 10.5 12.3 14.1 1 1 1 0 8.6 10.8 12.7 14.4 1 1 1 1 8.9 11.1 13 14.7 PI3EQX1204-C Document number: DS40033 Rev.1-2 4 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Flat Gain Setting: FG[1:0] are the selection bits for the DC value. Table 2. Flat Gain Setting Flat Gain Setting FG1 FG0 dB 0 0 -3.5 0 1 -1.5 1 0 0.5 1 1 2.5 Swing Setting: Swing Setting: SW[1:0] are the selection bits for the output swing value. Table 3. Swing Setting SW1 SW0 mVp-p 0 0 700 0 1 800 1 0 900 1 1 1000 PI3EQX1204-C Document number: DS40033 Rev.1-2 5 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C I2C Programming Address assignment A6 A5 A4 A3 A2 A1 A0 R/W 1 1 1 AD3 AD2 AD1 AD0 1=R, 0=W BYTE 0 Reserved BYTE 1 Reserved BYTE 2 Bit Type Power up condition Control affected 7 R/W 0 A3 Power down 6 R/W 0 A2 Power down 5 R/W 0 A1 Power down 4 R/W 0 A0 Power down 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Comment 1 = Power down BYTE 3 Bit Type Power up condition Control affected 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Bit Type Power up condition Control affected 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Channel A0 configuration Comment Equalizer EQ0 FG1 Flat gain Swing BYTE 4 PI3EQX1204-C Document number: DS40033 Rev.1-2 Channel A1 configuration 6 Comment Equalizer EQ0 FG1 Flat gain Swing www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C I2C Programming cont. BYTE 5 Bit Type Power up condition Control affected 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Bit Type Power up condition Control affected 7 R/W 0 EQ3 6 R/W 0 EQ2 5 R/W 0 EQ1 4 R/W 0 3 R/W 0 2 R/W 0 FG0 1 R/W 0 SW1 0 R/W 0 SW0 Channel A2 configuration Comment Equalizer EQ0 FG1 Flat gain Swing BYTE 6 Channel A3 configuration Comment Equalizer EQ0 FG1 Flat gain Swing BYTE 7-15 with '0' power up condition Reserved PI3EQX1204-C Document number: DS40033 Rev.1-2 7 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Reset and I2CM Timing Diagram I2C Operation The integrated I2C interface operates as a master or slave device depending on the pin ENI2C being HIZ or HIGH respectively. Standard mode (100Kbps) is supported with 7-bit addressing. The data byte format is 8-bit bytes, and supports the format of indexing to be compatible with other bus devices. In the Slave mode (ENI2C = HIGH), the device supports Read/Write. The bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A3 to A0 are programmable to support multiple chips environment. The Data is loaded until a Stop sequence is issued. In the master mode (ENI2C = HIZ), PI3EQX1204-C supports up to 16 masters connected in daisy chain through connecting I2C_ DONE pin to I2C_RESET# pin of the next part. Master EEPROM data starting address for device address: I2C address: AD3, AD2, AD1, AD0 Data starting location 0000 00H 0001 10H 0010 20H 0011 30H 0100 40H 0101 50H 0110 60H 0111 70H 1000 80H 1001 90H 1010 A0H 1011 B0H 1100 C0H 1101 D0H 1110 E0H 1111 F0H PI3EQX1204-C Document number: DS40033 Rev.1-2 8 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Transferring Data Every byte put on the SDA line must be 8-bits long. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (see the I2C Data Transfer diagram). The PI3EQX1204-C will never hold the clock line SCL LOW to force the master into a wait state. Acknowledge Data transfer with acknowledge is required from the master. When the master releases the SDA line (HIGH) during the acknowledge clock pulse, the PI3EQX1204-C will pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse as indicated in the I2C Data Transfer diagram. The PI3EQX1204-C will generate an acknowledge after each byte has been received. Data Transfer A data transfer cycle begins with the master issuing a start bit. After recognizing a start bit, the PI3EQX1204-C will watch the next byte of information for a match with its address setting. When a match is found it will respond with a read or write of data on the following clocks. Each byte must be followed by an acknowledge bit, except for the last byte of a read cycle which ends with a stop bit. For a write cycle, the first data byte following the address byte is an index byte that is used by the PI3EQX1204-C. Data is transferred with the most significant bit (MSB) first. I2C Data Transfer Start & Stop Conditions A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition, as shown in the figure below PI3EQX1204-C Document number: DS40033 Rev.1-2 9 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C I2C Data Transfer PI3EQX1204-C Document number: DS40033 Rev.1-2 10 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage to Ground Potential . . . . . . . . . . . . . –0.5V to +4.6V DC SIG Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to VCC+0.5V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25mA to +25mA Power Dissipation Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1W Junction Temperature Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C ESD, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2kV to +2kV Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical characteristics: LVCMOS I/O DC Specifications (VCC = 3.3 ± 0.3V, TA = -40 to 85°C) Symbol Parameter VIH DC input logic high VCC/2 + 0.7 DC input logic low -0.3 VIL VOH VOL V hys Conditions Min. Typ. VCC + 0.2 At IOH = -200µA Max Units VCC + 0.3 V VCC/2 - 0.7 V V At IOL = -200µA 0.2 V 0.8 Hysteresis of Schmitt trigger input V SDA and SCL I/O for I2C-bus (VCC = 3.3 ± 0.3V, TA = -40 to 85°C) Symbol Parameter Conditions Min. Typ. Max. Units VIH DC input logic high VCC/2 + 0.7 VCC + 0.3 V VIL DC input logic low -0.3 VCC/2 - 0.7 V VOL DC output logic low V hys Hysteresis of Schmitt trigger input tof Output fall time from VIHmin to VILmax with bus cap. 10-400pF 250 ns f SCLK SCLK clock frequency 100 kHz 0.4 IOL = 3mA V 0.8 V High speed I/O AC/DC Specifications (VCC = 3.3 ± 0.3V, TA = -40 to 85°C) Symbol Parameter CRX RX AC coupling capacitance S11 Input return loss S22 Output return loss R IN Conditions Min. Typ. 220 10MHz to 6GHz differential 11.0 1GHz to 6GHz common mode 5.0 10MHz to 6GHz differential 11.5 1GHz to 6GHz common mode 4.8 DC single-ended input impedance 50 DC Differential Input Impedance 100 PI3EQX1204-C Document number: DS40033 Rev.1-2 11 www.diodes.com Max. Units nF dB dB Ω May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C High speed I/O AC/DC Specifications cont. Symbol Parameter Conditions Min. Typ. Max. Units DC single-ended output impedance 50 DC Differential output Impedance 100 ZRX-HIZ DC input CM input impedance during reset or power down 200 VRX-DIFF-PP Differential Input Peak-to-peak Voltage Operational 1.2 Vppd Input source common-mode noise DC – 200MHz 150 mVpp ROUT Ω kΩ Max time to electrical idle after sending an EIOS 4 8 ns DATA Max time to valid diff signal after leaving electrical idle 4 8 ns Vcc Power supply voltage 3.3 3.6 V Pmax Max Supply power 1.3 W Imax Max Supply current 360 mA Pidle Supply power PRSNT#=1 14.4 mW tpd Latency From input to output 0.5 EQ = 1111 15.4 GP Peaking gain (Compensation at 6GHz, relative to 100MHz, 100mVp-p sine wave input) EQ = 1000 12.5 EQ = 0000 7.1 TTX-IDLE-SET-TOIDLE TTX-IDLE-TO-DIFF- GF 3 PRSNT#=0 Flat gain (100MHz, EQ = 1000, SW = 10) Variation around typical V1dB_6G VCoup -1dB compression point of output swing (at 100MHz) -1dB compression point of output swing (at 6GHz) Channel isolation PI3EQX1204-C Document number: DS40033 Rev.1-2 12 dB +3 FG = 11 2 FG = 10 0 FG = 01 -2 FG = 00 -4 Variation around typical V1dB_100M -3 ns -3 dB +3 SW = 11 1370 SW = 10 1280 SW = 01 1040 SW = 00 920 SW = 11 1000 SW = 10 940 SW = 01 700 SW = 00 600 100MHz to 6GHz, Figure 1 (Note 1) 25 www.diodes.com dB dB mVppd mVppd dB May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C High speed I/O AC/DC Specifications cont. Symbol Vnoise_input Vnoise_output Parameter Conditions Input-referred noise Output-referred noise (Note 2) Min. Typ. 100MHz to 6GHz, FG = 11, EQ = 0000, Figure 2 0.5 100MHz to 6GHz, FG = 11, EQ = 1010, Figure 2 0.4 100MHz to 6GHz, FG = 11, EQ = 0000, Figure 2 0.7 100MHz to 6GHz, FG = 11, EQ = 1010, Figure 2 0.8 Max. Units mVRMS mVRMS 1.6 Note: (1) Measured using a vector-network analyzer (VNA) with -15dBm power level applied to the adjacent input. The VNA detects the signal at the output of the victim channel. All other inputs and outputs are terminated with 50Ω. (2) Guaranteed by design and characterization. PI3EQX1204-C Figure 1. Channel-isolation test configuration PI3EQX1204-C Figure 2. Noise test configuration PI3EQX1204-C Document number: DS40033 Rev.1-2 13 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C ESD Specification • • 2000V HBM 500V CDM Application Diagram VCC 0-48in 50 ohm 220nF 220nF AXRX+ AXTX+ AXRX- AXTX- 220nF 50 ohm 0-48in 220nF PI3EQX1204-C AGND PI3EQX1204-C Document number: DS40033 Rev.1-2 PRSNT# VCC 3.3V SCL SCL AGND 0V SDA SDA 14 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C AC/DC Specifications - SCL/SDA for I2C BUS Symbol Parameter VIH DC input logic high VIL DC input logic low VOL DC output logic low IOL = 3mA Current Through Pull-Up Resistor High Power specification Ipullup Conditions or Current Source Min. Typ. Max Units VCC/2 + 0.7 VCC + 0.3 V -0.3 VCC/2 - 0.7 V 0.4 V 3.0 3.6 mA VDD Nominal Bus Voltage 3.0 3.6 V Ileak-bus Input leakage per bus segment -200 200 uA Ileak-pin Input leakage per device pin CI Capacitance for SDA/SCL 10 pF Freq Bus Operation Frequency 100k Hz TBUF "Bus Free Time Between Stop and Start condition" THD:STA Hold time after (Repeated) Start condition. After this period, the first clock is generated. TSU:STA TSU:STO -15 uA 1.3 us 0.6 us Repeated start conidtion setup time 0.6 us Stop condition setup time 0.6 us THD:DAT Data hold time 0 ns TSU:DAT Data setup time 100 ns Tlow Clock low period 1.3 us Thigh Clock high period tF Clock/Data fall time 0.6 tR tpor At Ipull-up, Max 50 us 300 ns Clock/Data rise time 300 ns "Time in which a device must be operation after power-on reset" 500 ms Note: (1) Recommended value. (2) Recommended maximum capacitance load per bus segment is 400pF. (3) Compliant to I2C physical layer specification. (4) Ensured by Design. Parameter not tested in production. PI3EQX1204-C Document number: DS40033 Rev.1-2 15 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C Package Mechanical: 42-Contact TQFN (ZH) 17-0266 Note: For latest package info, please check: https://www.diodes.com/design/support/packaging/pericom-packaging/ Ordering Information Ordering Number Package Code Package Description PI3EQX1204-CZHE ZH 42-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PI3EQX1204-CZHEX ZH 42-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN), Tape & Reel Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • X suffix = Tape/Reel PI3EQX1204-C Document number: DS40033 Rev.1-2 16 www.diodes.com May 2017 ® Diodes Incorporated A product Line of Diodes Incorporated PI3EQX1204-C IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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