ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI101-B
1:1 Active HDMI™ ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Features
Description
ÎÎSupply voltage, VDD = 3.3V ±5%
Pericom Semiconductor’s PI3HDMI101-B 1:1 active ReDriver™
circuit is targeted for high-resolution video networks that are
based on DVI/HDMI™ standards and TMDS signal processing.
The PI3HDMI101-B is an active ReDriver with Hi-Z outputs.
The device receives differential signals from selected video components and drives the video display unit. This solution also
provides a unique advanced pre-emphasis technique to increase
rise and fall times which are reduced during transmission across
long distances.
ÎÎSupport
for both DVI and HDMI™ signals
ÎÎSupports
both AC-coupled and DC-coupled inputs
ÎÎSupports
DeepColor™
ÎÎHigh
ÎÎ5V
Performance, up to 2.5 Gbps per channel
Tolerance on I2C path
ÎÎIntegrated
50-ohm (±10%) termination resistors at each high
speed signal input
ÎÎIntegrated
Each complete HDMI/DVI channel also has slower speed, side
band signals, that are required to be switched. Pericom’s solution provides a complete solution by integrating the side band
buffer together with the high speed buffer in a single solution.
Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter
caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer
cables (up to 25 meters).
Rx termination detection circuit
ÎÎConfigurable
output swing control
(400mV, 500mV, 600mV, 750mV, 1000mV)
ÎÎConfigurable
Pre-Emphasis levels
(0dB, 1.5dB, 3.5dB, & 6.0dB, 9.0dB)
ÎÎConfigurable
De-Emphasis
(0dB, -3.5dB, -6.0dB, -9.5dB)
ÎÎOptimized
ÎÎ Single
Equalization
The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 36bit DeepColor™ support, which is offered by HDMI revision 1.3.
The PI3HDMI101-B also provides enhanced robust ESD/EOS
protection of 8kV, which is required by many consumer video
networks today.
default setting will support all cable lengths
ÎÎ8kV
Contact ESD protection on all input data/clock channels
per IEC61000-4-2
ÎÎHot
insertion support on output high speed pins & SCL/SDA
pins only
ÎÎPropagation
ÎÎHigh
The Optimized Equalization provides the user a single optimal
setting that can provide HDMI compliance for all cable lengths: 1
meter to 20 meters and color depths of 8bit/ch, or 12bit/ch.
delay ≤ 1ns
Impedance Outputs when disabled
ÎÎPackaging
Pericom also offers the ability to fine tune the equalization settings in situations where cable length is known. For example,
if 25 meter cable length is required, Pericom's solution can be
adjusted to 16dB EQ to accept 25 meter cable length.
(Pb-free & Green): 42-contact TQFN (ZH42)
Using Pericom's patent-pending Rx termination detection circuit,
PI3HDMI101-B can automatically disable its own input 50-Ohm
termination when no 50-Ohm termination is detected in the
HDMI Rx chipset. If a switch is used between the PI3HDMI101-B
and the HDMI Rx, our part can detect the 50-Ohm termination
in the switch to determine if our input should be off or on.
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13-0005
1
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
IADJ
SCL_R
SDA_R
SDA_T
Pin Configuration
EQ_S0
EQ_S1
GND
IN_CLK–
IN_CLK+
VDD
IN_D0–
IN_D0+
GND
IN_D1–
IN_D1+
VDD
IN_D2–
IN_D2+
GND
RxSENSE
DCC_EN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
42 41 40 39
GND
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
SCL_T
VDD
GND
OUT_CLK–
OUT_CLK+
VDD
OUT_D0–
OUT_D0+
GND
OUT_D1–
OUT_D1+
VDD
OUT_D2–
OUT_D2+
GND
VDD
OC_S3
OE
OC_S0
OC_S1
OC_S2
18 19 20 21
TMDS Receiver Block
Each high speed data and clock input has integrated equalization that can eliminate deterministic jitter caused by input cables.
All activity can be configured using pin strapping. The Rx block is designed to receive all relevant signals directly from the HDMI™
connector without any additional circuitry, 3 High speed TMDS data, 1 pixel clock, and DDC signals. TMDS channels have the following termination scheme for Rx Sense support. The switching between 50-Ohm termination vs. 250K-Ohm termination is done
automatically. The PI3HDMI101-B monitors the 50-Ohm termination in the Rx chipset behind our part, and when this 50-Ohm
termination is not present, we disable our 50-Ohm termination at our input.
DD
K-
IN_Dx+/-, IN_CLK+/-
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PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
I2C Buffer
IADJ,DDC_EN
BufferT
PortR
PortT
BufferR
The VOL of the Buffer R is around 0.2V.
The VOL of the Buffer T is around 0.7V.
Functional Truth Tables
IADJ
External Pull-Up Range
H
1K-Ohm to 2K-Ohm (HDMI spec)
L
> 3K-Ohm (4.7K-Ohm typically)
DDC_EN
Port T / Port R (if no external pull-up resistor
L
Hi-Z (I2C buffer disable)
H
(I2C buffer enable)
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13-0005
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PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Pin Description
Pin #
Pin Name
I/O
Description
5
IN_CLK+
8
IN_D0+
11
IN_D1+
I
TMDS Positive inputs
14
IN_D2+
4
IN_CLK-
7
IN_D0-
10
IN_D1-
I
TMDS Negative inputs
13
IN_D2-
3, 9, 15, 24, 30, 36
GND
P
Ground
18
OE
I
Output Enable, Active LOW
41
SCL_R
I/O
DDC Clock , Source Side
40
SDA_R
I/O
DDC Data, Source Side
6, 12, 16, 23, 27, 33, 37
VDD
P
3.3V Power Supply
34
OUT_CLK+
31
OUT_D0+
28
OUT_D1+
O
TMDS positive outputs
25
OUT_D2+
35
OUT_CLK-
32
OUT_D0-
29
OUT_D1-
O
TMDS negative outputs
26
OUT_D2-
1
EQ_S0
2
EQ_S1
I
Equalizer controls, both pins with internal pull-ups
19
OC_S0
20
21
OC_S1
OC_S2
22
OC_S3
17
DDC_EN
I
I2C path enable
38
SCL_T
I/O
DDC Clock, Sink side
39
SDA_T
I/O
DDC Data, Sink side
42
IADJ
I
High/Low Voltage Selection, depends on I2C external pull-up
range
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Output buffer controls
I
13-0005
Note: All 4 pins have internal pull-ups
4
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Complete high speed input Rx block is as follows:(1)
_S0
_S1
_S2
_S
E
EQ_S0
EQ_S1
2
2 0Ω
IN_
1
+
2
2 0Ω
R e c e iv e r
with E Q
1
IN_
2
2 0Ω
1
IN_D0+
VDD
2
DS
1
IN_D1+
_
-
VDD
R e c e iv e r
with E Q
DS
_D0+
DS
_D1+
_D1-
DS
_D2+
IN_D02
+
2 0Ω
1
2 0Ω
_
2
_D0-
VDD
2 0Ω
R e c e iv e r
with E Q
1
IN_D12
2 0Ω
IN_D2+
1
2
VDD
2 0Ω
1
R e c e iv e r
with E Q
IN_D2-
_D2-
I D
DD _EN
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13-0005
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PS8956B
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PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Truth Table
OE
Function
0
Active
1
All TMDS outputs are Hi-Z
Truth Table 1
OC_S3(2)
OC_S2(2)
OC_S1(2)
OC_S0(2)
Vswing(mv)
Pre/de-emphasis
1
1
1
1
500
0dB
1
1
1
0
600
0dB
1
1
0
1
750
0dB
1
1
0
0
1000
0dB
1
0
1
1
500
0dB
1
0
1
0
500
1.5dB
1
0
0
1
500
3.5dB
1
0
0
0
500
6dB
0
1
1
1
400
0dB
0
1
1
0
400
3.5dB
0
1
0
1
400
6dB
0
1
0
0
400
9dB
0
0
1
1
1000
0dB
0
0
1
0
666
-3.5dB
0
0
0
1
500
-6dB
0
0
0
0
333
-9dB
EQ Setting Value Logic Table
EQ_S1(2)
EQ_S0(2)
Gain (dB)
1
1
Optimized Equalization (Default Setting)
1
0
8
0
1
3
0
0
15
Notes:
1. External pull-ups are required along SCL/SDA path
2. Internal 100K-Ohm pull-ups
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13-0005
6
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature..................................................... –65°C to +150°C
Supply Voltage to Ground Potential.................................–0.5V to +4.0V
DC Input Voltage................................................................–0.5V to VDD
DC Output Current........................................................................ 120mA
Power Dissipation............................................................................ 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Recommended Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Supply Voltage
3.135
3.3
3.465
V
TA
Operating free-air temperature
0
70
°C
TMDS Differential Pins
VID
Receiver peak-to-peak differential input voltage
150
1560
mVp-p
VIC
Input common mode voltage
2
VDD + 0.01
V
VDD
TMDS output termination voltage
3.135
3.3
3.465
V
RT
Termination resistance
45
50
55
Ohm
Signaling rate
0
2.5
Gbps
Control Pins (OC_Sx, EQ_Sx, OE, DDC_EN)
VIH
LVTTL High-level input voltage
2
VDD
VIL
LVTTL Low-level input voltage
GND
0.8
GND
5.5
V
0.7 x VDD
5.5
V
-0.5
0.3 x VDD
V
-0.5
0.4
V
V
DDC Pins (SCL_R, SCL_T, SDA_R, SDA_T)
VI(DDC)
Input voltage
I2C Pins (SCL_T, SDA_T)
VIH
High-level input voltage
VIL
Low-level input voltage
VICL
Low-level input voltage contention
(1)
I C Pins (SCL_R, SDA_R)
2
VIH
High-level input voltage
0.7 x VDD
5.5
V
VIL
Low-level input voltage
-0.5
0.3 x VDD
V
Notes:
1. V IL specification is for the first low level seen by the SCL/SDA lines. V ICL is for the second and subsequent low levels seen by the SCL_T/SDA_T lines.
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13-0005
7
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
TMDS Compliance Test Results
Item
HDMI 1.3 Spec
Pericom Product Spec
Termination Supply Voltage, VDD
3.3V ≤ 5%
3.30 ± 5%
Terminal Resistance
50-Ohm ± 10%
45 to 55-Ohm
Single-ended high level output voltage, VH
VDD ± 10mV
VDD ±10mV
Single-ended low level output voltage, VL
( VDD - 600mV) ≤ VL ≤ ( VDD- 400mV)
( VDD - 600mV) ≤ VL ≤ ( VDD 400mV)
Single-ended output swing voltage, Vswing
400mV ≤ Vswing ≤ 600mV
400mV ≤ Vswing ≤ 600mV
Single-ended standby (off) output voltage, Voff
VDD ± 10mV
VDD ± 10mV
Operating Conditions
Source DC Characteristics at TP1
Transmitter AC Characteristics at TP1
75ps ≤ Risetime/Falltime ≤ 0.4 Tbit
Risetime/Falltime (20%-80%)
(75ps ≤ tr/tf ≤ 242ps) @ 1.65 Gbps
Intra-Pair Skew at Transmitter Connector, max
Inter-Pair Skew at Transmitter Connector, max
0.15 Tbit
(90.9ps @ 1.65 Gbps)
0.2 Tpixel
(1.2ns @ 1.65 Gbps)
0.25 Tbit
Clock Jitter, max
(151.5ps @ 1.65 Gbps)
240ps
60ps max
100ps max
82ps max
Sink Operating DC Characteristics at TP2
Input Differential Voltage Level, Vdiff
Input Common Mode Voltage Level, VICM
150 ≤ Vdiff ≤ 1200mV
150mV ≤ VDIFF ≤ 1200mV
( VDD - 300mV) ≤ Vicm ≤ ( VDD37.5mV)
( VDD - 300mV) ≤ Vicm ≤ ( VDD37.5mV)
Or
Or
VDD ±10%
VDD ±10%
Sink DC Characteristics When Source Disabled or Disconnected at TP2
Differential Voltage Level
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VDD ± 10mV
13-0005
VDD ±10mV
8
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
Test Conditions
ICC
Supply Current
VIH = VDD, VIL = VDD - 0.4V,
RT = 50-Ohm, VDD = 3.3V
PD
Min.
Data Inputs = 1.65 Gbps HDMI data
pattern
Power Dissipation
CLK Inputs = 165 MHz clock
Typ.(1) Max.
Units
120
mA
400
mW
8
mA
OC_Sx = Low, x = 0,1,2,3
ICCQ
OE = HIGH, VDD = 3.3V, RxSense =
LOW
Standby Current
TMDS Differential Pins
VOH
Single-ended high-level output voltage
VDD10
VDD
+ 10
VOL
Single-ended low-level output voltage
VDD 600
VDD 400
Vswing
Single-ended output swing voltage
400
600
VOD(O)
Overshoot of output differential voltage
VOD(U)
VDD = 3.3V, RT = 50-Ohm
Pre-emphasis/De-emphasis = 0dB
mV
6%
15%
Undershoot of output differential
voltage
12%
25%
ΔVOC(SS)
Change in steady-state common-mode
output voltage between logic states
0.5
5
mV
|I(OS)|
Short circuit output current
12
mA
VODE(SS)
Steady state output differential voltage
VODE(PP)
Peak-to-peak output differential voltage
VI(open)
Single-ended input voltage under high
impedance input or open input
R INT
Input termination resistance
OC_Sx = GND, Data Inputs = 250
Mbps HDMI data pattern,
2x
Vswing
560
840
800
1200
II = 10µA
VDD 10
VDD +
mV
10
VIN = 2.9V
45
25 MHz pixel clock
50
mVp-p
55
ohm
Control Pins (OE, DDC_EN, IADJ)
IIH
High-level digital input current
VIH = 2V or VDD
-10
10
µA
IIL
Low-level digital input current
VI = GND or 0.8 V
-10
10
µA
VI = 5.5 V
-50
50
VI = VDD
-20
20
I C Pins (SCL_T, SDA_T) (T Port)
2
µA
Iikg
Input leakage current
IOH
High-level output current
VO = 3.6 V
-10
10
µA
IIL
Low-level input current
VIL = GND
-40
40
µA
VOL
Low-level output voltage
0.65
0.9
V
IOL = 2.5 mA
IADJ = H
(Table Continued)
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13-0005
9
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Electrical Characteristics (Cont..)
Symbol
Parameter
Test Conditions
CIO
Input/output capacitance
VOH(TTL)1
TTL High-level output voltage
IOH = -8 mA
VOL(TTL) 1
TTL Low-level output voltage
IOL = 8 mA
Min.
Typ.(1) Max.
VI = 5.0 V or 0 V, Freq = 100kHz
25
VI = 3.0 V or 0 V, Freq = 100kHz
10
Units
pF
2.4
V
0.4
V
Note:
1. Voh/Vol of external driver at the R and T ports.
I2C Pins (SCL_R, SDA_R) (R Port)
VI = 5.5 V
-50
50
VI = VDD
-20
20
High-level output current
VO = 3.6 V
-10
10
µA
IIL
Low-level input current
VIL = GND
-10
10
µA
VOL
Low-level output voltage
IOL = 4 mA, IADJ = H
0.2
V
CI
Input capacitance
VI = 5.0 V or 0 V, Freq = 100kHz
25
VI = 3.0 V or 0 V, Freq = 100kHz
10
Iikg
Input leakage current
IOH
µA
pF
Switching Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
Typ.(1) Max.
Units
TMDS Differential Pins
2000
tpd
Propagation delay
tr
Differential output signal rise time (20%
- 80%)
tf
Differential output signal fall time (20%
- 80%)
tsk(p)
Pulse skew
10
50
tsk(D)
Intra-pair differential skew
23
50
tsk(o)
Inter-pair differential skew(2)
tjit(pp)
Peak-to-peak output jitter from TMDS
clock channel
tjit(pp)
Peak-to-peak output jitter from
TMDS data channel
tDE
VDD = 3.3V, RT = 50-Ohm,
pre-emphasis/de-emphasis = 0dB
75
240
75
240
100
pre-emphasis/de-emphasis = 0dB,
Data Inputs = 1.65 Gbps HDMI data
pattern
CLK input = 165 MHz clock
de-emphasis = -3.5dB, Data Inputs =
250 Mbps HDMI data pattern,
CLK output = 25 MHz clock
De-emphasis duration
15
30
18
50
ps
240
(Table Continued)
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13-0005
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PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Switching Characteristics (Cont..)
Symbol
Parameter
Test Conditions
Min.
Typ.(1) Max.
tSX
Select to switch output
10
ten
Enable time
200
tdis
Disable time
10
Units
ns
I C PINS (SCL_R, SDA_R, SCL_T, SDA_T)
2
Propagation delay time, low-to-high-level
output SCL_T/SDA_T to SCL_R/SDA_R
IADJ = VDD
CLOAD = 300 pF
500
tPHL
Propagation delay time, high-to-low-level
output SCL_T/SDA_T to SCL_R/SDA_R
Tbuffer :
Rpu = 2K, Vpu = 3.0V
136
tPLH
Propagation delay time, low-to-high-level
output SCL_T/SDA_T to SCL_R/SDA_R
tPHL
Propagation delay time, high-to-low-level
output SCL_T/SDA_T to SCL_R/SDA_R
Rbuffer :
Rpu = 1.2K, Vpu = 3.3V or
Rpu = 1.8K, Vpu = 5V
IADJ = GND
CLOAD = 100 pF
tPLH
tr
SCL_T/SDA_T Output signal rise time
tf
SCL_T/SDA_T Output signal fall time
tr
SCL_R/SDA_R Output signal rise time
tf
SCL_R/SDA_R Output signal fall time
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13-0005
450
ns
136
999
See Fig. A
90
999
90
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PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Symbol
Parameter
tset
t hold
Test Conditions
Min.
Typ.
Max.
Enable to start condition
6
10
Enable after stop condition
6
10
Units
ns
IADJ=L
3.3V±10%
VDD
R=1.2kΩ
L
V DD
RSCL/RSDA
Input
V CC /2
0.1V
t PHL
PULSE
GENERATOR
D.U.T.
VIOUT
VIN
C=100pF
L
t PLH
3.3V±10%
80%
80%
TSCL/TSDA
Input
1.5V
20%
20%
VOL
tf
tf
IADJ=H
3.3V±10%
VDD
PULSE
GENERATOR
R=2kΩ
L
RSCL/RSDA
Input
1.5V
0.1V
t PHL
D.U.T.
VIN
V DD
VIOUT
t PLH
5V±10%
80%
C=300pF
L
80%
TSCL/TSDA
Input
20%
tf
20%
tf
V DD /2
VOL
t PLH
Figure A. I2C Timing Test Circuit and Definition
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PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
TMDS output oscillation elimination
The TMDS inputs do not incorporate a squelch circuit. Therefore, we recommend the input to be externally biased to prevent output
oscillation. One pin will be pulled high to VDD with the other grounded through a 1.5K-Ohm resistor as shown.
VDD
RINT
A
RINT
TMDS
Receiver
Y
TMDS
Driver
Z
B
ss
ss
RT
AVDD
RT
TMDS Input Fail-Safe Recommendation
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13-0005
13
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Recommended Power Supply Decoupling Circuit
Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1µF decoupling capacitors on
each VDD pins of our part, there are four 0.1µF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins
on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1µF decoupling capacitors should be adjusted
according to the actual number of VDD pins. On top of 0.1µF decoupling capacitors on each VDD pins, it is recommended to put a
10µF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended
for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the
power supply conditions of other circuits.
10µF
Ferrite Bead
From main
power supply
0.1µF
V DD
0.1µF
V DD
P e r ic o m P a r t
0.1µF
V DD
0.1µF
V DD
Figure 1 Recommended Power Supply Decoupling Circuit Diagram
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13-0005
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PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Requirements on the Decoupling Capacitors
There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R.
Layout and Decoupling CapacitorPlacement Consideration
i. Each 0.1µF decoupling capacitor should be placed as close as possible to each VDD pin.
ii. VDD and GND planes should be used to provide a low impedance path for power and ground.
iii. Via holes should be placed to connect to VDD and GND planes directly.
iv. Trace should be as wide as possible
v. Trace should be as short as possible.
vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria.
vii. 10µF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1µF capacitors.
viii. Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large
current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part.
Bypass noise
V DD P la ne
Power Flow
G N D P la ne
0 .1 uF
P e r ic o m P a r t
Figure 2 Layout and Decoupling Capacitor Placement Diagram
All trademarks are property of their respective owners.
13-0005
15
PS8956B
03/06/13
PI3HDMI101-B
1:1 Active HDMITM ReDriver™ with Optimized Equalization
& I2C Buffer and RxTerm detection circuitry
Application Information
Supply Voltage
All VDD pins are recommended to have a 0.01µF capacitor tied from VDD to GND to filter supply noise
TMDS inputs
Standard TMDS terminations have already been integrated into Pericom’s PI3HDM101-A device. Therefore, external terminations
are not required. Any unused port must be left floating and not tied to GND.
Package Mechanical: 42-pin, Low Profile Quad Flat Package (ZH42)
Notes:
1. All dimensions are in millimeters. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220.
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
DATE: 11/14/12
DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH42
DOCUMENT CONTROL #: PD-2035
REVISION:D
12-0529
Ordering Information
Ordering Code
Package Code
Package Description
PI3HDMI101-BZHE
ZH
42-pin, Pb-free & Green TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
• HDMI & DeepColor are trademarks of Silicon Image
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
All trademarks are property of their respective owners.
13-0005
16
PS8956B
03/06/13
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