PI3HDMI101ZHEX

ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI™ ReDriver™ with Optimized Equalization & I2C Buffer Features Description • • • • • • • Pericom Semiconductor’s PI3HDMI101 1:1 active ReDriver™ circuit is targeted for high-resolution video networks that are based on DVI/HDMITM standards and TMDS signal processing. The PI3HDMI101 is an active ReDriver with Hi-Z outputs. The device receives differential signals from selected video components and drives the video display unit. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. Each complete HDMI/DVI channel also has slower speed, side band signals, that are required to be switched. Pericom’s solution provides a complete solution by integrating the side band buffer together with the high speed buffer in a single solution. Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 36bit Deep Color™ support, which is offered by HDMI revision 1.3. The PI3HDMI101 also provides enhanced robust ESD/EOS protection of 8kV, which is required by many consumer video networks today. The Optimized Equalization provides the user a single optimal setting that can provide HDMI compliance for all cable lengths: 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. Pericom also offers the ability to fine tune the equalization settings in situations where cable length is known. For example, if 25meter cable length is required, Pericom's solution can be adjusted to 16dB EQ to accept 25meter cable length. • • • • • • • • • • Supply voltage, VDD = 3.3V ±5% Support for both DVI and HDMITM signals Supports both AC-coupled and DC-coupled inputs Supports Deep ColorTM High Performance, up to 2.5 Gbps per channel 5V Tolerance on I2C path Integrated 50-Ohm (±10%) termination resistors at each high speed signal input Rx Sense Support, CLK-off channel is switched to 250K-Ohm pull-up vs. 50-Ohm pull-up Configurable output swing control (400mV, 500mV, 600mV, 750mV, 1000mV) Configurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, & 6.0dB, 9.0dB) Configurable De-Emphasis (0dB, -3.5dB, -6.0dB, -9.5dB) Optimized Equalization Single default setting will support all cable lengths 8kV Contact ESD protection on all input/output data channels per IEC 61000-4-2 Hot insertion support on output high speed pins & SCL/SDA pins only Propagation delay ≤ 1ns High Impedance Outputs when disabled Packaging (Pb-free & Green): 42-contact TQFN (ZH42) 09-0055 All trademarks are property of their respective owners. 1 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM IADJ SCL_R SDA_R SDA_T Pin Configuration 42414039 38 1 37 2 36 3 35 4 34 5 33 6 32 7 31 8 30 9 GND 29 10 28 11 27 12 26 13 25 14 24 15 23 16 22 17 18192021 SCL_T VDD GND OUT_CLK– OUT_CLK+ VDD OUT_D0– OUT_D0+ GND OUT_D1– OUT_D1+ VDD OUT_D2– OUT_D2+ GND VDD OC_S3 OE OC_S0 OC_S1 OC_S2 EQ_S0 EQ_S1 GND IN_CLK– IN_CLK+ VDD IN_D0– IN_D0+ GND IN_D1– IN_D1+ VDD IN_D2– IN_D2+ GND Rx_Sense DCC_EN TMDS Receiver Block Each high speed data and clock input has the same integrated equalization that can eliminate deterministic jitter caused by input traces or cables. All activity can be configured using pin strapping. The Rx block is designed to receive all relevant signals directly from the HDMI™ connector without any additional circuitry, 3 High speed TMDS data, 1 pixel clock, and DDC signals. Pixel clock channel has following termination scheme for Rx Sense support. Rx Sense L AV DD R2 H 250Kohm R2 switch is open, CLK+/termination is 250k R2 switch is closed, CLK+/termination is 50 Control Rx Sense R1 CLK+/- 09-0055 All trademarks are property of their respective owners. 2 Although the TMDS clock input channel (pin 4 and 5) has different termination scheme when port is off, user can still connect TMDS data channels to these pins for better layout if required. Any of the 4 differential inputs and outputs can have data or clock signals passing through. PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM I2C Buffer IADJ,DDC_EN BufferT PortR PortT BufferR The VOL of the Buffer R is around 0.2V. The VOL of the Buffer T is around 0.7V. Functional Truth Tables IADJ H L External Pull-Up Range 1KΩ to 2KΩ (HDMI spec) > 3KΩ (4.7KΩ typically) DDC_EN L H Port T / Port R (if no external pull-up resistor Hi-Z (I2C buffer disable) (I2C buffer enable) 09-0055 All trademarks are property of their respective owners. 3 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Pin Description Pin # Pin Name I/O Description 5 8 11 14 4 7 10 13 IN_CLK+ IN_D0+ IN_D1+ IN_D2+ IN_CLKIN_D0IN_D1IN_D2- I TMDS Positive inputs I TMDS Negative inputs 3, 9, 15, 24, 30, 36 GND P Ground 18 OE I Output Enable, Active LOW 41 SCL_R I/O DDC Clock , Source Side 40 SDA_R I/O DDC Data, Source Side 6, 12, 23, 27, 33, 37 34 31 28 25 35 32 29 26 1 2 19 20 21 22 VDD OUT_CLK+ OUT_D0+ OUT_D1+ OUT_D2+ OUT_CLKOUT_D0OUT_D1OUT_D2EQ_S0 EQ_S1 OC_S0 OC_S1 OC_S2 OC_S3 P 3.3V Power Supply O TMDS positive outputs O TMDS negative outputs I Equalizer controls, both pins with internal pull-ups I Output buffer controls Note: All 4 pins have internal pull-ups 17 DDC_EN I I2C path enable 38 SCL_T I/O DDC Clock, Sink side 39 SDA_T I/O DDC Data, Sink side 16 Rx_Sense I Rx_Sense control 42 IADJ I High/Low Voltage Selection, depends on I2C external pull-up range 09-0055 All trademarks are property of their respective owners. 4 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Complete high speed input Rx block is as follows: EQ_S0 OC_S0 OC_S1 OC_S2 OC_S3 OE Control EQ_S1 250kΩ R2 R2 VDD 150kΩ R1 IN_CLK+ R1 TMDS drive R e c e iv e r with E Q IN_CLK50Ω OUT_CLK+ OUT_CLK- VDD 50Ω IN_D0+ R e c e iv e r with E Q TMDS drive OUT_D0+ TMDS drive OUT_D1+ OUT_D1- OUT_D0- IN_D050Ω VDD 50Ω IN_D1+ R e c e iv e r with E Q IN_D150Ω VDD 50Ω IN_D2+ TMDS drive R e c e iv e r with E Q IN_D2- OUT_D2+ OUT_D2- IADJ, DDC_EN Buffer T Port T Port R Buffer R 09-0055 All trademarks are property of their respective owners. 5 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Truth Table OE Function 0 Active 1 All TMDS outputs are Hi-Z Truth Table 1 OC_S3(2) OC_S2(2) 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 OC_S1(2) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OC_S0(2) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vswing (mV) 500 600 750 1000 500 500 500 500 400 400 400 400 1000 660 500 330 Pre/De-emphasis 0 0 0 0 0 1.5dB 3.5dB 6dB 0 3.5dB 6dB 9dB 0 -3.5dB -6dB -9dB EQ Setting Value Logic Table Setting Value @ 825MHz EQ_S1(2) EQ_S0(2) 0 0 3dB on all high speed inputs 0 1 8dB on all high speed inputs 1 0 12dB on all high speed inputs 1 1 16dB on all high speed inputs Notes: 1. External pull-ups are required along SCL/SDA path 2. Internal 100Kohm pull-ups 09-0055 All trademarks are property of their respective owners. 6 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature .................................................... –65°C to +150°C Supply Voltage to Ground Potential................................–0.5V to +4.0V DC Input Voltage ...............................................................–0.5V to VDD DC Output Current....................................................................... 120mA Power Dissipation ........................................................................... 1.0W Recommended Operating Conditions Symbol Parameter Min. Typ. Max. Units Supply Voltage 3.135 3.3 3.465 V 0 70 °C 150 1560 mVp-p 2 VDD + 0.01 VDD TA Operating free-air temperature TMDS Differential Pins VID Receiver peak-to-peak differential input voltage VIC Input common mode voltage VDD TMDS output termination voltage RT Termination resistance when RxSense pin is HIGH TMDS Data Signaling rate Rate V 3.135 3.3 3.465 45 50 55 ohm 0.25 2.5 Gbps Control Pins (OC_Sx, EQ_Sx, OE, DDC_EN) VIH LVTTL High-level input voltage 2 VDD VIL LVTTL Low-level input voltage GND 0.8 GND 5.5 0.7 x VDD 5.5 -0.5 0.3 x VDD -0.5 0.4 V DDC Pins (SCL_R, SCL_T, SDA_R, SDA_T) VI(DDC) Input voltage V 2 I C Pins (SCL_T, SDA_T) VIH High-level input voltage VIL Low-level input voltage VICL Low-level input voltage contention (1) V 2 I C Pins (SCL_R, SDA_R) VIH High-level input voltage 0.7 x VDD 5.5 VIL Low-level input voltage -0.5 0.3 x VDD V Note: 1. VIL specification is for the first low level seen by the SCL/SDA lines. VICL is for the second and subsequent low levels seen by the TSCL/TSDA lines. 09-0055 All trademarks are property of their respective owners. 7 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Electrical Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter IDD Supply Current PD Power Dissipation IDDQ Standby Current Test Conditions Min. VIH = VDD, VIL = VDD - 0.4V, RT = 50-ohm, VDD = 3.3V Data Inputs = 1.65 Gbps HDMI data pattern CLK Inputs = 165 MHz clock OC_Sx = Low, x = 0,1,2,3 OE = HIGH, VDD = 3.3V, Source = off Typ.(1) Max. Units 120 mA 400 mW 2 mA TMDS Differential Pins VOH Single-ended high-level output voltage VDD10 VDD + 10 VOL Single-ended low-level output voltage VDD - 600 VDD - 400 400 600 Vswing Single-ended output swing voltage VOD(O) Overshoot of output differential voltage VOD(U) ΔVOC(SS) I(OS) VDD = 3.3V, RT = 50-ohm Pre-emphasis/De-emphasis = 0dB 6% 15% Undershoot of output differential voltage 12% 25% 2x Vswing Change in steady-state common-mode output voltage between logic states 0.5 5 mV 12 mA Short circuit output current VODE(SS) Steady state output differential voltage VODE(PP) Peak-to-peak output differential voltage OC_Sx = GND, Data Inputs = 250 Mbps HDMI data pattern, 25 MHz pixel clock, x = 0,1,2,3 Single-ended input voltage under high impedance input or open input II = 10μA Input termination resistance VIN = 2.9V, RxSense pin = HIGH 45 VI(open) RINT mV 560 840 800 1200 VDD - 10 VDD + 10 mV 55 ohm 50 mVp-p Control Pins (OE, DDC_EN, IADJ) IIH High-level digital input current VIH = 2V or VDD -10 10 IIL Low-level digital input current VI = GND or 0.8 V -10 10 VI = 5.5 V -50 50 VI = VDD -20 20 μA I2C Pins (SCL_T, SDA_T) (T Port) Iikg Input leakage current IOH High-level output current VO = 3.6 V -10 10 IIL Low-level input current VIL = GND -40 40 VOL Low-level output voltage IOL = 2.5 mA IADJ = H 0.65 0.9 V CIO1 Input/output capacitance VDD = 0V or 3.0V, Frequency = 100kHz 7 pF VOH(TTL)2 TTL High-level output voltage VOL(TTL) 2 TTL Low-level output voltage IOH = -8 mA IOL = 8 mA 4 2.4 0.4 μA V Note: 1. Measured at Vbias = 0V or 5V, Vrms = 0.2V; Vbias = 1.65V, Vrms = 0.84V; Vbias = 2.5V, Vrms = 1.2V. 2. Voh/Vol of external driver at the R and T ports. (Table Continued) 09-0055 All trademarks are property of their respective owners. 8 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM I2C Pins (SCL_R, SDA_R Port) VI = 5.5 V -50 50 VI = VDD -10 10 High-level output current VO = 3.6 V -10 10 Low-level input current VIL = GND -10 10 Low-level output voltage IOL = 4 mA, IADJ = H 0.2 VI = 5.0 V or 0 V, Freq = 100kHz 25 VI = 3.0 V or 0 V, Freq = 100kHz 10 Iikg Input leakage current IOH IIL VOL Input capacitance CI μA V pF Switching Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter Test Conditions Min. Typ.(1) Max. Units TMDS Differential Pins tpd Propagation delay 2000 tr Differential output signal rise time (20% - 80%) tf Differential output signal fall time (20% - 80%) tsk(p) Pulse skew tsk(D) Intra-pair differential skew tsk(o) Inter-pair differential skew VDD = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 75 240 75 240 10 50 23 50 100 (2) tCLKjit(pp) Peak-to-peak output jitter for TMDS clock channel tDatajit(pp) Peak-to-peak output jitter for TMDS data channels pre-emphasis/de-emphasis = 0dB, Data Inputs = 1.65 Gbps HDMI data pattern CLK input = 165 MHz clock de-emphasis = -3.5dB, Data Inputs = 250 Mbps HDMI data pattern, CLK output = 25 MHz clock 15 30 18 50 tDE De-emphasis duration tSX Select to switch output 10 ten Enable time 200 tdis Disable time 10 ps 240 ns 2 I C PINS (SCL_R, SDA_R, SCL_T, SDA_T) tPLH Propagation delay time, low-to-high-level output SCL_T/SDA_T to SCL_R/SDA_R tPHL Propagation delay time, high-to-low-level output SCL_T/SDA_T to SCL_R/SDA_R tPLH Propagation delay time, low-to-high-level output SCL_T/SDA_T to SCL_R/SDA_R tPHL Propagation delay time, high-to-low-level output SCL_T/SDA_T to SCL_R/SDA_R tr SCL_T/SDA_T Output signal rise time tf SCL_T/SDA_T Output signal fall time tr SCL_R/SDA_R Output signal rise time tf SCL_R/SDA_R Output signal fall time IADJ = VDD CLOAD = 300 pF Tbuffer : Rpu = 2K, Vpu = 3.0V 500 136 Rbuffer : Rpu = 1.2K, Vpu = 3.3V or Rpu = 1.8K, Vpu = 5V IADJ = GND CLOAD = 100 pF 450 136 999 90 See Fig. A 999 90 tset Enable to start condition 6 10 thold Enable after stop condition 6 10 09-0055 All trademarks are property of their respective owners. ns 9 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM IADJ=L V DD 3.3V±10% VDD R=1.2kΩ L RSCL/RSDA Input V DD /2 0.1V t PHL PULSE GENERATOR D.U.T. VIOUT VIN t PLH 3.3V±10% 80% C=100pF L 80% TSCL/TSDA Input 1.5V 20% 20% VOL tf tf IADJ=H 3.3V±10% VDD R=2kΩ L V DD RSCL/RSDA Input 1.5V 0.1V t PHL PULSE GENERATOR D.U.T. VIOUT VIN t PLH 5V±10% 80% C=300pF L 80% TSCL/TSDA Input V DD /2 20% tf 20% tf VOL t PLH Figure A. I2C Timing Test Circuit and Definition 09-0055 All trademarks are property of their respective owners. 10 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM TMDS output oscillation elimination The TMDS inputs do not incorporate a squelch circuit. Therefore, we recommend the input to be externally biased to prevent output oscillation. One pin will be pulled high to VDD with the other grounded through a 1.5K-ohm resistor as shown. VDD RINT RINT TMDS Receiver TMDS Driver ss RT AVCC ss RT 1.5Kohm TMDS Input Fail-Safe Recommendation 09-0055 All trademarks are property of their respective owners. 11 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Recommended Power Supply Decoupling Circuit Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1μF decoupling capacitors on each VDD pins of our part, there are four 0.1μF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1μF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1μF decoupling capacitors on each VDD pins, it is recommended to put a 10μF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of other circuits. 10μF Ferrite Bead From main power supply 0.1μF V DD 0.1μF V DD P e r ic o m P a r t 0.1μF V DD 0.1μF V DD Figure 1 Recommended Power Supply Decoupling Circuit Diagram 09-0055 All trademarks are property of their respective owners. 12 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Requirements on the Decoupling Capacitors There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R. Layout and Decoupling CapacitorPlacement Consideration i. Each 0.1μF decoupling capacitor should be placed as close as possible to each VDD pin. ii. VDD and GND planes should be used to provide a low impedance path for power and ground. iii. Via holes should be placed to connect to VDD and GND planes directly. iv. Trace should be as wide as possible v. Trace should be as short as possible. vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. vii. 10μF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1μF capacitors. viii. Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. Bypass noise V DD P la ne Power Flow 0 .1 uF G N D P la ne P e r ic o m P a r t Figure 2 Layout and Decoupling Capacitor Placement Diagram 09-0055 All trademarks are property of their respective owners. 13 PS8924C 10/05/09 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI101 1:1 Active HDMI Redriver with Optimized Equalization & I2C Buffer TM Application Information Supply Voltage All VDD pins are recommended to have a 0.01μF capacitor tied from VDD to GND to filter supply noise TMDS inputs Standard TMDS terminations have already been integrated into Pericom’s PI3HDM101 device. Therefore, external terminations are not required. Any unused port must be left floating and not tied to GND. Package Mechanical: 42-pin, Low Profile Quad Flat Package (ZH42) Notes: 1. All dimensions are in millimeters, angles in degrees. 2. Coplanarity applies to the exposed thermal pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended Land Pattern is for reference only. 5. Thermal Pad Soldering Area Note: DATE: 02/17/09 DESCRIPTION: 42-contact Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH (ZH42) REVISION: C DOCUMENT CONTROL #: PD-2035 09-0116 • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code PI3HDMI101ZHE ZH Package Description 42-pin, Pb-free & Green TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X Suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 09-0055 All trademarks are property of their respective owners. 14 PS8924C 10/05/09