ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI201
2:1 Active HDMI™ Compatible Switch with Optimized
Equalization for Enhanced Signal Integrity
Features
Description
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Pericom Semiconductor’s PI3HDMI201 2:1 active switch circuit
is targeted for high-resolution video networks that are based
on DVI/HDMI™ standards and TMDS signal processing. The
PI3HDMI201 is an active 2 TMDS to 1 TMDS receiver switch
with Hi-Z outputs. The device receives differential signals from
selected video components and drives the video display unit. It
provides three controllable output swings. The allowable output
swings are 500mV, 750mV and 1000mV. This solution also
provides a unique advanced pre-emphasis technique to increase
rise and fall times which are reduced during transmission across
long distances.
Each complete HDMI/DVI channel also has slower speed, side
band signals, that are required to be switched. Pericom’s solution
provides a complete solution by integrating the side band switch
together with the high speed switch in a single solution. Using
Equalization at the input of each of the high speed channels,
Pericom can successfully eliminate deterministic jitter caused by
long cables from the source to the sink. The elimination of the
deterministic jitter allows the user to use much longer cables (up
to 25 meters).
The maximum DVI/HDM Bandwidth of 2.5 Gbps provides 36bit DeepColor™ support, which is offered by HDM revision 1.3.
Due to its active uni-directional feature, this switch is designed
for usage only for the video receiver’s side. For consumer video
networks, the device sits at the receiver’s side to switch between
multiple video components, such as PC, DVD, STB, D-VHS,
etc. The PI3HDMI201 also provides enhanced robust ESD/EOS
protection of ±6kV, which is required by many consumer video
networks today.
The Optimized Equalization provides the user a single optimal
setting that can provide HDMI compliance in regards to jitter for
all cable lengths: 1meter to 20meters and color depths of 8bit/ch,
or 12bit/ch.
Pericom also offers the ability to fine tune the equalization
settings in situations where cable length is known. For example,
if 25meter cable length is required, Pericom's solution can be
adjusted to 16dB EQ to accept 25meter cable length.
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Supply voltage, VDD = 3.3V ±5%
Each Port can support DVI or HDMI™ signals
Supports both AC-coupled and DC-coupled inputs
Supports DeepColor™
High Performance, up to 2.5 Gbps per channel
Switching support for 3 side band signals
(SCL, SDA and HPD)
5V Tolerance on all side band signals
SCL, SDA, and HPD pins are the only pins that can support
HOT INSERTION
Integrated 50-Ohm (±10%) termination resistors at each high
speed signal input
TMDS input termination control on all high speed inputs
HDCP reset circuitry for quick communication when
switching from one port to another
Configurable output swing control
(500mV, 750mV, 1000mV)
Configurable Pre-Emphasis levels
(0dB, 1.5dB, 3.5dB, & 6.0dB)
Configurable De-Emphasis
(0dB, -3.5dB, -6.0dB, -9.5dB)
Optimized Equalization
Single default setting will support all cable lengths
ESD spec on all input TMDS pins is ±6kV per IEC61000-4-2
Propagation delay ≤ 2ns
High Impedance Outputs when disabled
Packaging (Pb-free & Green): 56-contact TQFN (ZF56)
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
GND
SCLA
SDAA
HPDA
OE
SEL1
53
52
51
50
49
CLK-A
55
54
CLK+A
56
Pin Configuration (Top View)
VDD
1
48
VDD
D0-A
2
47
HPD_Sink
D0+A
3
46
SDA_sink
GND
4
45
SCL_sink
D1-A
5
44
GND
D1+A
6
43
CLK-
VDD
7
42
CLK+
D2-A
8
41
VDD
D2+A
9
40
D0-
GND
GND
10
39
D0+
CLK-B
11
38
GND
CLK+B
12
37
D1-
VDD
13
36
D1+
29
OC_S2
28
20
EQ_S0
OC_S1
D2-B
27
30
SEL2
19
26
OC_S0
VDD
25
31
SCLB
18
EQ_S1
GND
D1+B
24
D1-B
32
SDAB
D2+
17
HPDB
GND
33
23
D2-
16
22
VDD
34
21
35
15
GND
14
D2+B
D0-B
D0+B
Receiver Block
Each input has integrated equalization that can eliminate deterministic jitter caused by 25meter 24AWG
cables. All activity can be configured using pin strapping. The Rx block is designed to receive all relevant signals directly from the HDMITM connector without any additional circuitry, 3 High speed TMDS
data, 1 pixel clock, 1 HPD signal, and DDC signals. TMDS channels have following termination scheme
for Rx Sense support.
AVdd
R2
250K-Ohm
R1
CLKx+/-, Dx+/-
x = A or B
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Pin Description
Pin #
Pin Name
I/O
3
6
9
56
D0+A
D1+A
D2+A
CLK+A
I
Port A TMDS Positive inputs
15
18
21
12
D0+B
D1+B
D2+B
CLK+B
I
Port B TMDS Positive inputs
2
5
8
55
D0-A
D1-A
D2-A
CLK-A
I
Port A TMDS Negative inputs
14
17
20
11
D0-B
D1-B
D2-B
CLK-B
I
Port B TMDS Negative inputs
4, 10, 16, 22, 32, 38, 44, 54
GND
51
HPDA
O
Port A HPD output
23
HPDB
O
Port B HPD output
47
HPD_Sink
I
Sink side hot plug detector input.
50
OE
I
Output Enable, Active LOW
53
SCLA
I/O
Port A DDC Clock
25
SCLB
I/O
Port B DDC Clock
45
SCL_Sink
I/O
Sink Side DDC Clock
52
SDAA
I/O
Port A DDC Data
24
SDAB
I/O
Port B DDC Data
46
SDA_Sink
I/O
Sink Side DDC Data
49
SEL1
I
1, 7, 13, 19, 35, 41, 48
VDD
39
36
33
42
D0+
D1+
D2+
CLK+
O
TMDS positive outputs
40
37
34
43
D0D1D2CLK-
O
TMDS negative outputs
28
26
EQ_S0
EQ_S1
I
Equalizer controls, Internal pull-ups are added to both.
31
30
29
OC_S0
OC_S1
OC_S2
I
Output buffer controls
Note: all 3 pins have internal pull-ups
27
SEL2
I
Source Input Selector (See Truth Table)
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Description
Ground
Source Input Selector (See Truth Table)
3.3V Power Supply
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Switch Block Diagram
CLK+A
CLK-A
R1
R2
R2
R1
R2
R2
R2
V DD
R e c e iv e r
with E Q
V DD
R e c e iv e r
with E Q
V DD
R e c e iv e r
with E Q
V DD
VDD
R1
R1
R2
...
CLK+B
R1
R2
R2
R e c e iv e r
with E Q
R2
R2
D0+A
R1
R1
R1
EQ_S1
D0-A
D1+A
D1-A
D2+A
D2-A
EQ_S0
R1
R e c e iv e r
with E Q
R1
OC_S0
CLK-B
R2
R2
D0+B
OC_S1
OC_S2
OC_S3
V DD
R1
2-to-1
R e c e iv e r
with E Q
R1
MUX
D0-B
R2
R2
TDMS
Drive
D0-
V DD
TDMS
Drive
R1
R e c e iv e r
with E Q
D1+
D1-
...
D1+B
R1
D0+
D1-B
R2
R2
D2+B
V DD
TDMS
Drive
R1
R1
R e c e iv e r
with E Q
D2+
D2-
CLK+
D2-B
TDMS
Drive
CLK-
OE
SEL1
SEL2
HPDA
HPD_SINK
Control Logic
HPDB
SCLA
SDAA
SCL_SINK
SDA_SINK
SCLB
SDAB
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Truth Table
OE
SEL1
SEL2
0
1
X
0
0
1
0
0
0
1
X
X
Function for TMDS output
HPDA
HPDB
HPD_sink
L
L
HPD_sink
L
L
Follow SEL1 and SEL2
Follow SEL1 and SEL2
Port A is active & TMDS Rx
Termination on Port B goes to
250K-Ohm
Port B is active, & TMDS Rx
Termination on Port A goes to
250K-Ohm
All TMDS outputs & TMDS
inputs are Hi-Z, SCL/SDA (Port
A & B) are off
All TMDS outputs are Hi-Z
OC Setting Value Logic Table
Input Control Pins
OC_S2
OC_S1
1
1
1
Setting Value
Vswing (mV)
Pre-emphasis (dB)
1
500
0
1
0
750
0
1
0
1
1000
0
1
0
0
600
0
0
1
1
500
0
0
1
0
500
1.5
0
0
1
500
3.5
0
0
0
500
6
(1)
(1)
OC_S0
(1)
Note:
1. Integrated pull-ups
EQ Setting Value Logic Table for high speed data bits (TMDS CLK input is left at 3dB default always)
EQ_S1(1)
0
0
1
EQ_S0(1)
0
1
0
1
1
Setting Value
15dB on all high speed data inputs
3dB on all high speed data inputs
8dB on all high speed data inputs
Optimized Equalization on all high speed data inputs (Default setting which can support all
cable lengths from 1meter to 20meters)
Notes:
1) Integrated internal pull-ups
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................... –65°C to +150°C
Supply Voltage to Ground Potential................................–0.5V to +4.0V
DC Input Voltage ...............................................................–0.5V to VDD
DC Output Current....................................................................... 120mA
Power Dissipation ........................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Recommended Operating Conditions
Symbol
VDD
TA
Parameter
Min.
Typ.
Max.
Units
Supply Voltage
3.135
3.3
3.465
V
0
70
°C
150
1560
mVp-p
2
VDD + 0.01
V
Operating free-air temperature
TMDS Differential Pins (DX±A, DX±B, CLK±A, CLK±B)
VID
Receiver peak-to-peak differential input voltage
VIC
Input common mode voltage
VDD
TMDS output termination voltage
RT
3.135
3.3
3.465
V
Termination resistance
45
50
55
Ohm
Signaling rate
0
2.5
Gbps
Control Pins (OC_Sx, EQ_Sx, SEL, OE)
VIH
LVTTL High-level input voltage
2
VDD
VIL
LVTTL Low-level input voltage
GND
0.8
GND
5.5
V
DDC Pins (SCL, SCL_SINK, SDA, SDA_SINK)
VI(DDC)
Input voltage
V
Status Pins (HPD_SINK)
VIH
LVTTL High-level input voltage
2
5.3
VIL
LVTTL Low-level input voltage
GND
0.8
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
TMDS Compliance Test Results
HDMITM 1.3 Spec
Pericom Product Spec
Termination Supply Voltage, VDD
3.3V ≤ 5%
3.30 ± 5%
Terminal Resistance
50-Ohm ± 10%
45 to 55-Ohm
Single-ended high level output voltage, VH
VDD ± 10mV
VDD ±10mV
Single-ended low level output voltage, VL
( VDD - 600mV) ≤ VL ≤ ( VDD - 400mV)
( VDD - 600mV) ≤ VL ≤
( VDD - 400mV)
Single-ended output swing voltage, Vswing
400mV ≤ Vswing ≤ 600mV
400mV ≤ Vswing ≤ 600mV
Single-ended standby (off) output voltage, Voff
VDD ± 10mV
VDD ± 10mV
Risetime/Falltime (20%-80%)
75ps ≤ Risetime/Falltime ≤ 0.4 Tbit
(75ps ≤ tr/tf ≤ 242ps) @ 1.65 Gbps
240ps
Intra-Pair Skew at Transmitter Connector, max
0.15 Tbit
(90.9ps @ 1.65 Gbps)
60ps max
Inter-Pair Skew at Transmitter Connector, max
0.2 Tpixel
(1.2ns @ 1.65 Gbps)
100ps max
Clock Jitter, max
0.25 Tbit
(151.5ps @ 1.65 Gbps)
82ps max
Input Differential Voltage Level, Vdiff
150 ≤ Vdiff ≤ 1200mV
150mV ≤ VDIFF ≤ 1200mV
Input Common Mode Voltage Level, VICM
( VDD - 300mV) ≤ Vicm ≤
( VDD-37.5mV)
Or
VDD ±10%
( VDD - 300mV) ≤ Vicm ≤
( VDD-37.5mV)
Or
VDD ±10%
Item
Operating Conditions
Source DC Characteristics at TP1
Transmitter AC Characteristics at TP1
Sink Operating DC Characteristics at TP2
Sink DC Characteristics When Source Disabled or Disconnected at TP2
Differential Voltage Level
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VDD ± 10mV
7
VDD ±10mV
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
ICC
Supply Current
PD
Power Dissipation
ICCQ
Standby Current
Test Conditions
Min.
VIH = VDD, VIL = VDD - 0.4V,
RT = 50-Ohm, VDD = 3.3V,
OC_SX = LOW, x = 0, 1, 2
OE = HIGH, SEL1 = Low,
SEL2 = Low, VDD=3.3V
Typ.(1)
Max.
Units
120
mA
400
mW
8
mA
TMDS Differential Pins (DX±A, DX±B, DX±, CLK±A, CLK±B, CLK±)
VOH
Single-ended high-level output voltage
VDD10
VDD +
10
VOL
Single-ended low-level output voltage
VDD
- 600
VDD
- 400
400
600
Vswing
Single-ended output swing voltage
VOD(O)
Overshoot of output differential voltage
VDD = 3.3V, RT = 50-Ohm
Pre-emphasis/De-emphasis = 0dB
mV
6%
15%
VOD(U)
Undershoot of output differential voltage
12%
25%
ΔVOC(SS)
Change in steady-state common-mode
output voltage between logic states
0.5
5
mV
12
mA
|I(OS)|
Short circuit output current
2x
Vswing
VODE(SS) Steady state output differential voltage
560
840
VODE(PP)
OC_Sx = GND, Dx±AB = 250
Mbps HDMITM data pattern,
Peak-to-peak output differential voltage X = 0, 1, 2
CLK±A, B = 25 MHz clock
800
1200
Single-ended input voltage under high
impedance input or open input
II = 10μA
VDD
- 10
VDD + 10
mV
Input termination resistance
VIN = 2.9V
45
55
Ohm
VI(open)
RINT
50
mVp-p
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
VI = 5.5V
-50
50
VI = VDD
-20
20
|Ilkg|
Input leakage current
CIO
Input/output capacitance
VI = 0V
RON
Switch resistance
IO = 3mA, VO = 0.4V
Switch output voltage
VI = 3.3V, II = 100μA
VPASS
7.5
1.5
(2)
μA
pF
25
50
2.0
2.5
(3)
Ohm
V
Status Pins (HPD)
VOH(TTL) TTL High-level output voltage
IOH = -4mA
VOL(TTL) TTL Low-level output voltage
IOL = 4mA
2.4
V
0.4
V
(Table Continued)
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Electrical Characteristics (Continued)
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Units
Control Pins (SEL, OE)
|IIH|
High-level digital input current
|IIL|
Low-level digital input current
VIH= 2.0V or VDD
-10
10
-10
10
VIH = 5.3V
-50
50
VIH = 2.0V or VDD
-10
10
VIL = GND or 0.8V
-10
10
VIL = GND or 0.8V
μA
Status Pins (HPD_SINK)
|IIH|
High-level digital input current
|IIL|
Low-level digital input current
μA
Notes:
1. All typical values are at 25°C and with a 3.3V supply.
2. The value is tested in full temperature range at 3.0V.
3. The value is tested in full temperature range at 3.6V.
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Switching Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Units
TMDS Differential Pins (Dx±, CLK±)
tpd
Propagation delay
2000
tr
Differential output signal rise time
(20% - 80%)
tf
Differential output signal fall time
(20% - 80%)
tsk(p)
Pulse skew
tsk(D)
Intra-pair differential skew
tsk(o)
Inter-pair differential skew
tjit(pp)
Peak-to-peak output jitter from CLK±
residual jitter
tjit(pp)
Peak-to-peak output jitter from
Dx± residual jitter
VDD = 3.3V, RT = 50-Ohm,
pre-emphasis/de-emphasis = 0dB
75
240
75
240
10
50
23
50
100
(2)
pre-emphasis/de-emphasis = 0dB,
Dx±A, B = 1.65 Gbps HDMITM data
pattern, x = 0, 1, 2
CLK±A, B = 165 MHz clock
de-emphasis = -3.5dB, Dx±A, B =
250 Mbps HDMITM data pattern,
x = 0, 1, 2
CLK±A, B = 25 MHz clock
15
30
18
50
tDE
De-emphasis duration
tSX
Select to switch output
10
ten
Enable time
200
tdis
Disable time
10
ps
240
ns
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
tpd(DDC)
Propagation delay from SCLn to
SCL_SINK or SDAn to SDA_SINK or
SDA_SINK to SDAn
CL = 10pF
0.4
2.5
2
6.0
ns
Control and Status Pins (SEL, HPD_SINK, HPD)
tpd(HPD)
tsx(HPD)
Propagation delay (from HPD_SINK to
the active port of HPD)
Switch time (from port select to the latest valid status of HPD)
CL = 10pF
ns
3
6.5
Notes:
1. All typical values are at 25°C and with a 3.3V supply.
2. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs
are tied together.
Application Information
Supply Voltage
All VDD pins are recommended to have a 0.1μF capacitor tied from VDD to GND to filter supply noise
TMDS inputs
Standard TMDS terminations have already been integrated into Pericom’s PI3HDMI201 device. Therefore, external terminations
are not required. Any unused port must be left floating and not tied to GND.
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
TMDS output oscillation elimination
The TMDS inputs do not incorporate a squelch circuit. Therefore, we recommend the input to be externally
biased to prevent output oscillation. One pin will be pulled high to VDD with the other grounded through a
1.5KOhm resistor as shown.
VDD
RINT
RINT
TMDS
Receiver
ss
TMDS
Driver
RT
AVDD
ss
RT
1.5Kohm
TMDS Input Fail-Safe Recommendation
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Recommended Power Supply Decoupling Circuit
Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1μF decoupling capacitors
on each VDD pins of our part, there are four 0.1μF decoupling capacitors are put in Figure 1 with an assumption of only four VDD
pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1μF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1μF decoupling capacitors on each VDD pins, it is recommended to put a
10μF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended
for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the
power supply conditions of other circuits.
10μF
Ferrite Bead
From main
power supply
0.1μF
V DD
0.1μF
V DD
P e r ic o m P a r t
0.1μF
V DD
0.1μF
V DD
Figure 1 Recommended Power Supply Decoupling Circuit Diagram
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Requirements on the Decoupling Capacitors
There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R.
Layout and Decoupling CapacitorPlacement Consideration
i. Each 0.1μF decoupling capacitor should be placed as close as possible to each VDD pin.
ii. VDD and GND planes should be used to provide a low impedance path for power and ground.
iii. Via holes should be placed to connect to VDD and GND planes directly.
iv. Trace should be as wide as possible
v. Trace should be as short as possible.
vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria.
vii. 10μF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1μF capacitors.
viii. Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large
current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part.
V DD P la ne
Bypass noise
Power Flow
0 .1 uF
G N D P la ne
P e r ic o m P a r t
Figure 2 Layout and Decoupling Capacitor Placement Diagram
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PI3HDMI201
2:1 Active HDMI™ Compatible Switch with
Optimized Equalization for Enhanced Signal Integrity
Package Mechanical: 56-pin, Low Profile Quad Flat Package (ZF56)
1
DATE: 05/15/08
DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN)
PACKAGE CODE: ZF56
REVISION: C
DOCUMENT CONTROL #: PD-2024
08-0208
Ordering Information
Ordering Code
Package Code
PI3HDMI201ZFE
ZF
Package Description
56-pin, Pb-free & Green TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
• HDMI & DeepColor are trademarks of Silicon Image
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
All trademarks are property of their respective owners.
14
09-0017
PS8957B
07/29/09