ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with Optimized
Equalization for Enhanced Signal Integrity
Features
Description
• Supply voltage, VDD = 3.3V ±5%
• Each of the three input ports can support HDMI™ or DVI
signals
• Supports both AC-coupled and DC-coupled inputs
• Supports DeepColor™
• High Performance, up to 2.5 Gbps per channel
• Switching support for 3 side band signals
(SCL, SDA and HPD)
• 5V Tolerance on all side band signals
• SCL, SDA, and HPD pins are the only pins that can support
HOT INSERTION
• Integrated 50-ohm (±10%) termination resistors at each high
speed signal input
• TMDS input termination control on all high speed inputs
• HDCP reset circuitry for quick communication when
switching from one port to another
• Configurable output swing control
• Configurable Pre-Emphasis levels
• Configurable De-Emphasis
• Optimized Equalization
Single default setting will support all cable lengths
• 8kV Contact ESD protection on all input data/clock channels
per IEC61000-4-2
• Propagation delay ≤ 2ns
• High Impedance Outputs when disabled
• Packaging (Pb-free & Green):
− 80-pin LQFP (FF80)
− 64-pin TQFN (ZL64)
Pericom Semiconductor’s PI3HDMI301 3:1 active switch circuit
is targeted for high-resolution video networks that are based
on DVI/HDMI™ standards and TMDS signal processing. The
PI3HDMI301 is an active 3 TMDS to 1 TMDS receiver switch
with Hi-Z outputs. The device receives differential signals from
selected video components and drives the video display unit. It
provides controllable output swings, as well as provides a unique
advanced pre-emphasis technique to increase rise and fall times
which are reduced during transmission across long distances.
Each complete HDMI/DVI channel also has slower speed, side
band signals, that are required to be switched. Pericom’s solution
provides a complete solution by integrating the side band switch
together with the high speed switch in a single solution. Using
Equalization at the input of each of the high speed channels,
Pericom can successfully eliminate deterministic jitter caused by
long cables from the source to the sink. The elimination of the
deterministic jitter allows the user to use much longer cables (up
to 25 meters).
The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 36-bit
Deep Color™ support, which is offered by HDMI™ revision 1.3.
Due to its active uni-directional feature, this switch is designed
for usage only for the video receiver’s side. For consumer video
networks, the device sits at the receiver’s side to switch between
multiple video components, such as PC, DVD, STB, D-VHS,
etc. The PI3HDMI301 also provides enhanced robust ESD/EOS
protection of 8kV, which is required by many consumer video
networks today.
The Optimized Equalization provides the user a single optimal
setting that can provide passing results for HDMI jitter tests for
all cable lengths: 1meter to 20meters with DeepColor support up
to 36bits.
Pericom also offers the ability to fine tune the equalization settings
in situations where cable length is known. For example, if 25meter
cable length is required, Pericom's solution can be adjusted to
16dB EQ to accept 25meter cable length.
09-0054
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1
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
EQ_S1
GND
D2+3
D2-3
VDD
D1+3
D1-3
GND
D0+3
D0-3
VDD
CLK+3
CLK-3
GND
SCL3
SDA3
HPD3
VDD
OE
EQ_S0
Pin Configuration (Top View)
61
60 59 5857 56 55 54 53 52 51 5049 48 47 4645 44 43 42 41
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1718 19 20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
HPD_SINK
SDA_SINK
SCL_SINK
GND
GND
CLKCLK+
VDD
D0D0+
GND
D1D1+
VDD
D2D2+
GND
S3
S2
S1
OC_S3
SDA1
SCL1
GND
CLK-1
CLK+1
VDD
D0-1
D0+1
GND
D1-1
D1+1
VDD
D2-1
D2+1
GND
VDD
OC_S1
OC_S0
OC_S2
VDD
HPD2
SDA2
SCL2
GND
GND
CLK-2
CLK+2
VDD
D0-2
D0+2
GND
D1-2
D1+2
VDD
D2-2
D2+2
GND
VDD
HPD1
1 64 63 62 61
60 59 58 57 56 55 54 53 52 51 50 49 48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
09-0054
D2+3
D2–3
VDD
D1+3
D1–3
D0+3
D0–3
VDD
CLK+3
CLK–3
SCL3
SDA3
HPD3
VDD
OE
EQ_S0
S3
D2+
D2–
VDD
D1+
D1–
D0+
D0–
VDD
CLK+
CLK–
SCL_SINK
SDA_SINK
HPD_SINK
GND
S1
S2
SDA1
SCL1
CLK–1
CLK+1
VDD
D0–1
D0+1
D1–1
D1+1
VDD
D2–1
D2+1
VDD
OC-S1
OC_S0
OC_S2
D2+2
D2–2
VDD
D1+2
D1–2
D0+2
D0–2
VDD
CLK+2
CLK–2
SCL2
SDA2
HPD2
EQ_S1
OC_S3
HPD1
(Top View)
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2
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Receiver Block1
Each input has integrated equalization that can eliminate deterministic jitter caused
by 25meter 24AWG cables. All activity can be configured using pin strapping. The
Rx block is designed to receive all relevant signals directly from the HDMITM connector without any additional circuitry, 3 High speed TMDS data, 1 pixel clock, 1 HPD
signals, and DDC signals. TMDS Channels have following termination scheme for Rx
Sense support.
AVdd
R1
250Kohm
R2
CLK+/-, Dx+/-
Note:
1. R1 + R2 = 50
09-0054
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3
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Pin Description
80 LQFP Pin #
64 TQFN Pin #
Pin Name
I/O
Description
9, 12, 15, 6
7, 9,12, 4
D0+1, D1+1, D2+1, CLK+1
I
Port 1 TMDS Positive inputs
71, 74, 77, 68
57, 59, 62, 54
D0+2, D1+2, D2+2, CLK+2
I
Port 2 TMDS Positive inputs
52, 55, 58, 49
43, 45, 48, 40
D0+3, D1+3, D2+3, CLK+3
I
Port 3 TMDS Positive inputs
8, 11, 14, 5
6, 8, 11, 3
D0-1, D1-1, D2-1, CLK-1
I
Port 1 TMDS Negative inputs
70, 73, 76, 67
56, 58, 61, 53
D0-2, D1-2, D2-2, CLK-2
I
Port 2 TMDS Negative inputs
51, 54, 57, 48
42, 44, 47, 39
D0-3, D1-3, D2-3, CLK-3
I
Port 3 TMDS Negative inputs
4, 10, 16, 24, 30,
36, 37, 47, 53, 59,
65, 66, 72, 78
GND
Ground
80
63
HPD1
O
Port 1 HPD output
62
50
HPD2
O
Port 2 HPD output
44
36
HPD3
O
Port 3 HPD output
40
32
HPD_Sink
I
Sink side hot plug detector input. High: 5-V
power signal asserted from source to sink
and EDID is ready.
Low: No 5-V power signal asserted from
source to sink, or EDID is not ready.
42
34
OE
I
Output Enable, Active LOW
3
2
SCL1
I/O
Port 1 DDC Clock
64
52
SCL2
I/O
Port 2 DDC Clock
46
38
SCL3
I/O
Port 3 DDC Clock
38
31
SCL_Sink
I/O
Sink Side DDC Clock
2
1
SDA1
I/O
Port 1 DDC Data
63
51
SDA2
I/O
Port 2 DDC Data
45
37
SDA3
I/O
Port 3 DDC Data
39
31
SDA_Sink
I/O
Sink Side DDC Data
21, 22, 23
17, 18, 19
S1, S2, S3
I
Source Input Control
7, 13, 17, 27, 33,
43, 50, 56, 61, 69,
75, 79
5, 10, 22, 27, 35,
41, 46, 55, 60
VDD
31, 28, 25, 34
25, 23, 20, 28
D0+, D1+, D2+, CLK+
O
TMDS positive outputs
32, 29, 26, 35
26, 24, 21, 29
D0-, D1-, D2-, CLK-
O
TMDS negative outputs
41, 60
33, 49
EQ_S0, EQ_S1
I
19, 18, 20, 1
15, 14, 16, 64
OC_S0, OC_S1,
OC_S2, OC_S3
I
09-0054
All trademarks are property of their respective owners.
3.3V Power Supply
4
Equalizer controls, both controls have
internal pull-ups
Output buffer controls, all control bits have
internal pull-ups
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Switch Block Diagram
CLK+1
CLK-1
R1
250kΩ
R2
R2
R2
250kΩ
R1
R2
250kΩ
R1
R2
V DD
R e c e iv e r
with E Q
V DD
R e c e iv e r
with E Q
V DD
...
250kΩ
CLK+2
R e c e iv e r
with E Q
V DD
VDD
250kΩ
R1
R2
250kΩ
R2
R2
R1
R2
R2
R e c e iv e r
with E Q
250kΩ
250kΩ
R1
250kΩ
R1
250kΩ
R1
EQ_S1
D0+1
D0-1
D1+1
D1-1
D2+1
D2-1
EQ_S0
R1
R e c e iv e r
with E Q
R1
OC_S0
CLK-2
250kΩ
R2
R2
OC_S1
OC_S2
OC_S3
V DD
250kΩ
D0+2
R1
3-to-1
R e c e iv e r
with E Q
R1
R2
R2
V DD
250kΩ
D1+
TDMS
Drive
R1
R e c e iv e r
with E Q
D1-
...
D1+2
R1
D0-
MUX
D0-2
250kΩ
D0+
TDMS
Drive
D1-2
250kΩ
R2
R2
V DD
D2+2
D2+
TDMS
Drive
250kΩ
D2-
R1
R e c e iv e r
with E Q
R1
CLK+
D2-2
TDMS
Drive
250kΩ
R2
R2
CLK-
V DD
250kΩ
CLK+3
R1
OE
R e c e iv e r
with E Q
R1
CLK-3
250kΩ
R2
R2
V DD
250kΩ
D0+3
R1
R e c e iv e r
with E Q
R1
S1
D0-3
S2
250kΩ
R2
R2
V DD
S3
250kΩ
R1
R e c e iv e r
with E Q
R1
...
D1+3
D1-3
250kΩ
R2
R2
V DD
250kΩ
D2+3
R1
R1
R e c e iv e r
with E Q
D2-3
HPD1
HPD_SINK
Control Logic
HPD2
HPD3
SCL1
SDA1
SCL_SINK
SDA_SINK
SCL2
SDA2
SCL3
SDA3
09-0054
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PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Truth Table
Control Pins
I/O Selected
Hot Plug Detect Status
OE
S1
S2
S3
TMDS outputs
L
H
x
x
Port1
SCL_Sink
SDA_Sink
SCL1
SDA1
HPD1
HPD2
HPD3
HPD_Sink
L
L
L
L
H
x
Port2
SCL2
SDA2
L
HPD_Sink
L
L
L
L
L
L
L
H
L
Port3
None (Hi-Z)
SCL3
SDA3
None (Hi-Z)
L
L
L
L
HPD_Sink
L
H
X
X
X
None (Hi-Z)
Follow S1, S2, S3
Follow S1, S2, S3
OC Setting Value Logic Table
0 Input Control Pins
(1)
OC_S1
(1)
Setting Value
OC_S0
(1)
0
0
0
0
0
0
0
1
333
500
Pre-emphasis/De-emphasis
(dB)
-9.5
-6
0
0
1
0
666
-3.5
0
0
1
1
1000
0
0
0
1
1
0
0
0
1
160
270
-9
-6
0
1
1
0
340
-3.5
0
1
1
1
500
0
1
0
0
0
500
6
1
0
0
1
500
3.5
1
0
1
0
500
1.5
1
0
1
1
500
0
1
1
0
0
600
0
1
1
0
1
1000
0
1
1
1
0
750
0
1
1
1
1
500
0
OC_S3
OC_S2
(1)
Vswing (mV)
EQ Setting Value Logic Table for high speed data bits (TMDS CLK input is left at 3dB default always)
EQ_S1(1)
0
0
1
1
EQ_S0(1)
0
1
0
1
Setting Value
15dB on all high speed data inputs
3dB on all high speed data inputs
8dB on all high speed data inputs
Optimized Equalization on all high speed data inputs (Default setting which can support all
cable lengths from 1meter to 20meters)
Notes:
1) Integrated internal pull-ups
09-0054
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PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................... –65°C to +150°C
Supply Voltage to Ground Potential................................–0.5V to +4.0V
DC Input Voltage ...............................................................–0.5V to VDD
DC Output Current....................................................................... 120mA
Power Dissipation ........................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Recommended Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
VDD
Supply Voltage
3.135
3.3
3.465
V
TA
Operating free-air temperature
0
70
°C
TMDS Differential PinS
VID
Receiver peak-to-peak differential input voltage
150
1560
mVp-p
VIC
Input common mode voltage
2
VDD + 0.01
V
VDD
TMDS output termination voltage
3.135
3.3
3.465
V
RT
Termination resistance
45
50
55
ohm
Signaling rate
0.25
2.5
Gbps
Control Pins (OC_Sx, EQ_Sx, Sx, OE)
VIH
LVTTL High-level input voltage
2
VDD
VIL
LVTTL Low-level input voltage
GND
0.8
GND
5.5
V
DDC Pins (SCLx, SCL_SINK, SDAx, SDA_SINK)
VI(DDC)
Input voltage
V
Status Pins (HPD_SINK)
VIH
LVTTL High-level input voltage
2
5.3
VIL
LVTTL Low-level input voltage
GND
0.8
09-0054
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7
V
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
TMDS Compliance Test Results
HDMITM 1.3 Spec
Pericom Product Spec
Termination Supply Voltage, VDD
3.3V ≤ 5%
3.30 ± 5%
Terminal Resistance
50-ohm ± 10%
45 to 55-ohm
Single-ended high level output voltage, VH
VDD ± 10mV
VDD ±10mV
Single-ended low level output voltage, VL
( VDD - 600mV) ≤ VL ≤ ( VDD - 400mV)
( VDD - 600mV) ≤ VL ≤ ( VDD 400mV)
Single-ended output swing voltage, Vswing
400mV ≤ Vswing ≤ 600mV
400mV ≤ Vswing ≤ 600mV
Single-ended standby (off) output voltage, Voff
VDD ± 10mV
VDD ± 10mV
Risetime/Falltime (20%-80%)
75ps ≤ Risetime/Falltime ≤ 0.4 Tbit
(75ps ≤ tr/tf ≤ 242ps) @ 1.65 Gbps
240ps
Intra-Pair Skew at Transmitter Connector, max
0.15 Tbit
(90.9ps @ 1.65 Gbps)
60ps max
Inter-Pair Skew at Transmitter Connector, max
0.2 Tpixel
(1.2ns @ 1.65 Gbps)
100ps max
Clock Jitter, max
0.25 Tbit
(151.5ps @ 1.65 Gbps)
82ps max
Input Differential Voltage Level, Vdiff
150 ≤ Vdiff ≤ 1200mV
150mV ≤ VDIFF ≤ 1200mV
Input Common Mode Voltage Level, VICM
( VDD - 300mV) ≤ Vicm ≤
( VDD-37.5mV)
Or
VDD ±10%
( VDD - 300mV) ≤ Vicm ≤
( VDD-37.5mV)
Or
VDD ±10%
Item
Operating Conditions
Source DC Characteristics at TP1
Transmitter AC Characteristics at TP1
Sink Operating DC Characteristics at TP2
Sink DC Characteristics When Source Disabled or Disconnected at TP2
Differential Voltage Level
09-0054
All trademarks are property of their respective owners.
VDD ± 10mV
VDD ±10mV
8
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
ICC
Supply Current
PD
Power Dissipation
ICCQ
Standby Current
Test Conditions
Min.
VIH = VDD, VIL = VDD - 0.4V,
RT = 50-ohm, VDD = 3.3V
Data Input = 1.65 Gbps HDMITM data
pattern
CLK Input = 165 MHz clock
OE = HIGH, S1 = S2 = S3 = LOW
Typ.(1)
Max.
Units
200
mA
660
mW
8
mA
TMDS Differential Pins
VOH
Single-ended high-level output
voltage
VDD10
VDD +
10
VOL
Single-ended low-level output
voltage
VDD 600
VDD 400
Vswing
Single-ended output swing voltage
400
600
VOD(O)
Overshoot of output differential
voltage
VOD(U)
Undershoot of output differential
voltage
VDD = 3.3V, RT = 50-ohm
Pre-emphasis/De-emphasis = 0dB
Change in steady-state commonΔVOC(SS) mode output voltage between logic
states
|I(OS)|
Short circuit output current
VODE(SS)
Steady state output differential
voltage
VODE(PP)
Peak-to-peak output differential
voltage
OC_Sx = GND, Data Input = 250
Mbps HDMITM data pattern
CLK Input = 25 MHz clock
x = 0, 1, 2, 3
VI(open)
Single-ended input voltage under
high impedance input or open input
RINT
Input termination resistance
mV
6%
15%
12%
25%
0.5
5
mV
12
mA
2x
Vswing
560
840
800
1200
II = 10μA
VDD 10
VDD + 10 mV
VIN = 2.9V
45
mVp-p
50
55
ohm
DDC I/O Pins (SCLx, SCL_SINK, SDAx, SDA_SINK)
VI = 5.5V
-50
50
VI = VDD
-10
10
|Ilkg|
Input leakage current
CIO
Input/output capacitance
VI = 0V
7.5
RON
Switch resistance
IO = 3mA, VO = 0.4V
25
50
ohm
VPASS
Switch output voltage
VI = 3.3V, II = 100μA
1.5(2)
2.0
2.5(3)
V
VOH(TTL) TTL High-level output voltage
IOH = -4mA
2.4
VOL(TTL) TTL Low-level output voltage
IOL = 4mA
μA
pF
Status Pins (HPD)
V
0.4
V
(Table Continued)
09-0054
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9
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Electrical Characteristics (Continued)
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Units
Control Pins (OC_Sx, EQ_Sx, Sx, OE)
IIH
High-level digital input current
VIH= 2.0V or VDD
-10
10
IIL
Low-level digital input current
VIL = GND or 0.8V
-10
10
VIH = 5.3V
-50
50
VIH = 2.0V or VDD
-10
10
VIL = GND or 0.8V
-10
10
μA
Status Pins (HPD_SINK)
IIH
High-level digital input current
IIL
Low-level digital input current
μA
Notes:
1. All typical values are at 25°C and with a 3.3V supply.
2. The value is tested in full temperature range at 3.0V.
3. The value is tested in full temperature range at 3.6V.
09-0054
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10
PS8959B
10/01/09
ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Switching Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Units
TMDS Differential Pins
tpd
Propagation delay
tr
Differential output signal rise time
(20% - 80%)
tf
Differential output signal fall time
(20% - 80%)
2000
VDD = 3.3V, RT = 50-ohm,
pre-emphasis/de-emphasis = 0dB
75
140
75
140
tsk(p)
Pulse skew
10
50
tsk(D)
Intra-pair differential skew
23
50
tsk(o)
Inter-pair differential skew(2)
TCLKjit(pp)
Peak-to-peak output jitter from
TMDS CLK channel residual jitter
TDATAjit(pp)
Peak-to-peak output jitter from
TMDS data residual jitter
tDE
De-emphasis duration
tSX
Select to switch output
10
ten
Enable time
200
tdis
Disable time
10
100
pre-emphasis/de-emphasis = 0dB,
Data Input = 1.65 Gbps HDMITM data
pattern
CLK Input = 165 MHz clock
de-emphasis = -3.5dB,
Data Input = 250 Mbps HDMITM data
pattern, CLK Input = 25 MHz clock
15
30
18
50
ps
240
ns
DDC I/O Pins (SCLx, SCL_SINK, SDAx, SDA_SINK)
tpd(DDC)
Propagation delay from SCLn to
SCL_SINK or SDAx to SDA_SINK
or SDA_SINK to SDAx
CL = 10pF
0.4
2.5
2
6.0
ns
Control and Status Pins (OC_SX, EQ_SX, Sx, HPD_SINK, HPDx)
tpd(HPD)
tsx(HPD)
Propagation delay (from HPD_SINK
to the active port of HPDx)
Switch time (from port select to the
latest valid status of HPDx)
CL = 10pF
ns
3
6.5
Notes:
1. All typical values are at 25°C and with a 3.3V supply.
2. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs
are tied together.
Application Information
Supply Voltage
All VDD pins are recommended to have a 0.01μF capacitor tied from VDD to GND to filter supply noise
TMDS inputs
Standard TMDS terminations have already been integrated into Pericom’s PI3HDMI301 device. Therefore, external terminations
are not required. Any unused port must be left floating and not tied to GND.
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
TMDS output oscillation elimination
The TMDS inputs do not incorporate a squelch circuit. Therefore, we reccomend the input to be externally
biased to prevent output oscillation. One pin will be pulled high to VDD with the other grounded through a
1.5K-Ohm resistor as shown.
VDD
RINT
RINT
TMDS
Receiver
TMDS
Driver
ss
RT
AVCC
ss
RT
1.5Kohm
TMDS Input Fail-Safe Recommendation
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Recommended Power Supply Decoupling Circuit
Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1μF decoupling capacitors
on each VDD pins of our part, there are four 0.1μF decoupling capacitors are put in Figure 1 with an assumption of only four VDD
pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1μF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1μF decoupling capacitors on each VDD pins, it is recommended to put a
10μF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended
for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the
power supply conditions of other circuits.
10μF
Ferrite Bead
From main
power supply
0.1μF
V DD
0.1μF
V DD
P e r ic o m P a r t
0.1μF
V DD
0.1μF
V DD
Figure 1 Recommended Power Supply Decoupling Circuit Diagram
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PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Requirements on the Decoupling Capacitors
There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R.
Layout and Decoupling CapacitorPlacement Consideration
i. Each 0.1μF decoupling capacitor should be placed as close as possible to each VDD pin.
ii. VDD and GND planes should be used to provide a low impedance path for power and ground.
iii. Via holes should be placed to connect to VDD and GND planes directly.
iv. Trace should be as wide as possible
v. Trace should be as short as possible.
vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria.
vii. 10μF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1μF capacitors.
viii. Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large
current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part.
Bypass noise
V DD P la ne
Power Flow
0 .1 uF
G N D P la ne
P e r ic o m P a r t
Figure 2 Layout and Decoupling Capacitor Placement Diagram
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PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Package Mechanical: 80-pin, Low Profile Quad Flat Package (FF80)
Top View:
DATE: 03/18/09
DESCRIPTION: 80-contact, Low Profile Quad Flat Package (LQFP)
PACKAGE CODE: FF (FF80)
DOCUMENT CONTROL #: PD-2064
REVISION: A
07-0100
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
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ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI301
3:1 Active Switch for HDMI™ Signals with
Optimized Equalization for Enhanced Signal Integrity
Package Mechanical: 64-pin, Quad Flat Package (ZL64)
Bottom View:
Top View:
DATE: 10/28/08
DESCRIPTION: 64-contact, Thin Fine Pitch Quad Flat No-Lead, TQFN
PACKAGE CODE: ZL
REVISION: B
DOCUMENT CONTROL #: PD-2067
08-0530
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Description
PI3HDMI301FFE
FF
80-pin, Pb-free & Green LQFP
PI3HDMI301ZLE
ZL
64-pin, Pb-free & Green TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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