PI3PCIE2612-BZFEX

PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Features Description • 6 Differential Channel, 1 to 2 demux that will support 5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1 signals on the second path • Insertion Loss for high speed channels @ 2.0 Gbps: -2.0dB • Low Bit-to-Bit Skew , 7ps max (between '+' and '-' bits) • Latched Mux Select • Matched paths for all PCIe signals • Low Crosstalk for high speed channels: -35dB@2.5 GHz • Low Off Isolation for high speed channels: -35dB@2.5 GHz • VDD Operating Range: 3.3V ± 10% • ESD Tolerance: 8kV HBM on Display Port Path output 4kV HBM on PCI-Express path output • Low channel-to-channel skew, 35ps max • Packaging (Pb-free & Green): – 56 TQFN (ZFE) Pericom Semiconductor’s PI3PCIE2612-B one to two Mux/ Demux is targeted for next generation systems that combine PCIExpress Gen2 signals with Display Port Signals. Application Routing DP and PCIExpress Gen1 or Gen2 signals with low signal attenuation. Truth Table (SEL control) GND 49 D1+ 52 D1- D053 VDD D0+ 54 50 VDD 51 GND 43 Tx0+ IN_1+ 7 42 Tx0- IN_1- 8 41 Tx1+ IN_2+ 9 40 Tx1- IN_2- 10 39 Tx2+ GND 11 38 Tx2- IN_3+ 12 37 Tx3+ IN_3- 13 36 Tx3- OUT+ 14 35 GND OUT- 15 34 VDD GND 16 33 AUX+ VDD 17 32 AUX- X+ 18 31 HPD X- 19 30 NC GND 20 29 GND 28 6 GND D3- VDD 27 44 VDD 5 26 D3+ IN_0- Rx0+ Logic Control 45 25 SEL LE# 4 Rx0- Rx0+ Rx0Rx1+ Rx1- D2- IN_0+ 24 AUX+ AUXHPD NC 46 23 OUT+ OUTX+ X- 3 Rx1- Tx2+ Tx2Tx3+ Tx3- D2+ LE# Rx1+ Tx0+ Tx0 Tx1+ Tx1 - GND 47 22 D2+ D2D3+ D3- 48 2 VDD IN_2+ IN_2IN_3+ IN_3- 1 SEL 21 D0+ D0D1+ D1- GND GND IN_0+ IN_0IN_1+ IN_1- 55 Block Diagram 56 Pin Diagram (top-side view) Truth Table (Latch control) Function SEL LE# Internal mux select PCI-Express Gen2 path is active (Tx) L 0 Respond to changes on SEL Digital Video Port is active (Dx) H 1 Latched 08-0147 1 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Application Example PI3PCIE2612-B DP/PCIe2.0 (1:2) Mux GMCH DP/TMDS/ PCIe genII IN x4 PEG Dx HPD HPD / PEG RX Aux / PEG RX x12 Tx x2 PEG RX AUX x2 PEG RX Rx DP Path will support 2.7 Gbps Rx Tx PCIe Path will support 5 Gbps x14 Rx x16 PEG Connector Pin Description Pin Number Pin Name 33 AUX+ Type O 32 AUX- O 54, 53 D0+, D0- O 52, 51 D1+, D1- O 47, 46 D2+, D2- O 45, 44 D3+, D3- O 08-0147 Description Differential input from HDMI/DP connector. AUX+ makes a differential pair with AUX-. AUX+ is passed through to the OUT+ pin when SEL = 1. Differential input from HDMI/DP connector. AUX- makes a differential pair with AUX+. AUX- is passed through to the OUTpin when SEL = 1. Analog “pass through” output#1 corresponding to IN_0+ and IN_0-, when SEL = 1. Analog “pass through” output#1 corresponding to IN_1+ and IN_1-, when SEL = 1. Analog “pass through” output#1 corresponding to IN_2+ and IN_2-, when SEL = 1. Analog “pass through” output#1 corresponding to IN_3+ and IN_3-, when SEL = 1. 2 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Pin Number Pin Name 1, 11, 16, 20, GND 21, 28, 29, 35, 48, 49, 56 31 HPD Type Power Ground. Description I 4 IN_0+ I 5 IN_0- I 7 IN_1+ I 8 IN_1- I 9 IN_2+ I 10 IN_2- I 12 IN_3+ I 13 IN_3- I 3 LE# I The HPD signal comes from the HDMI or DP connector. This is a low frequency, 0V to 5V (HDMI) or 3.6V (DP) input signal at the connector. The HPD input at the mux is 3.6V max, so HDMI HPD must be shifted down from 5V before it is passed to the mux. Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0-. Differential input from GMCH PCIE outputs. IN_0- makes a differential pair with IN_0+. Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1-. Differential input from GMCH PCIE outputs. IN_1- makes a differential pair with IN_1+. Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2-. Differential input from GMCH PCIE outputs. IN_2- makes a differential pair with IN_2+. Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3-. Differential input from GMCH PCIE outputs. IN_3- makes a differential pair with IN_3+. The latch gate is controlled by LE. 3.6V tolerant, low-voltage, single-ended input. 30 NC 14 OUT+ Do Not Connect O 15 OUT- O 26 Rx0+ I/O 25 Rx0- I/O 24 Rx1+ I 08-0147 Pass-through output from AUX+ input when SEL = 1. Passthrough output from Rx0+ input when SEL = 0. Pass-through output from AUX- input when SEL = 1. Passthrough output from Rx0- input when SEL = 0. Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0-. Rx0+ is passed through to the OUT+ pin when SEL = 0. Differential input from PCIE connector or device. Rx0- makes a differential pair with Rx0+. Rx0- is passed through to the OUTpin when SEL = 0. Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1-. Rx1+ is passed through to the X+ pin when SEL = 0. (Continued) 3 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Pin Number 23 Pin Name Rx1- Type I 2 SEL I 43, 42 Tx0+,Tx0- O 41, 40 Tx1+, Tx1- O 39, 38 Tx2+, Tx2- O 37, 36 Tx3+, Tx3- O 6, 17, 22, 27, 34, 50, 55 18 VDD Power X+ I/O 19 X- I 08-0147 Description Differential input from PCIE connector or device. Rx1- makes a differential pair with Rx1+. Rx1- is passed through to the X- pin on a path that matches the Rx1+ to X+ path. SEL controls the mux through a Àow-through latch. 3.6V tollerant low-voltage single-ended output SEL = 0 for PCIE Mode SEL = 1 for DP Mode Analog “pass through” output#2 corresponding to IN_0+ and IN_0-, when SEL = 0. Analog “pass through” output#2 corresponding to IN_1+ and IN_1-, when SEL = 0. Analog “pass through” output#2 corresponding to IN_2+ and IN_2-, when SEL = 0. Analog “pass through” output#2 corresponding to IN_3+ and IN_3-, when SEL = 0. 3.3V DC Supply, 3.3V +/- 10% HPD: Low frequency, 0V to 5V/3.3V (nominal) input signal at the connector. This signal comes from the HDMI/DP connector. X+: Analog “pass through” output corresponding to Rx1+. X- is an analog “pass-through” output corresponding to the Rx1input. The path from Rx1- to X- must be matched with the path from Rx1+ to X+. X+ and X- form a differential pair when the pass-through mux mode is selected. 4 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................................–65°C to +150°C Supply Voltage to Ground Potential ................................–0.5V to +4.6V DC Input Voltage .............................................................. –0.5V to VDD DC Output Current ....................................................................... 120mA Power Dissipation ........................................................................... 0.5W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci¿cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Units 3.3 3.6 V VDD 3.3V Power Supply 3.0 IDD Total current from VDD 3.3V supply Case temperature range for operation within spec. 0 2.5 mA -40 85 Celcius Max Units TCASE DC Electrical Characteristics (TA = –40°C to +85°C, VDD = 3.3V ± 10%) Parameter Description Test Conditions Min Typ(1) VIH-EN(2) Input high level 2.0 3.6 V VIL-EN(2) Input Low Level 0 0.8 V IIN_EN(2) Input Leakage Current Measured with input at VIH-EN max and –10 10 uA RON On Resistance VDD = Min., VIN = 1.3V, IIN = 40mA CON On Channel Capacitance VIN = 0, VDD = 3.3V VIL-EN min 10 3.0 Ohm pF Note: 1. Typical values are at VDD = 3.3V, TA = 25°C ambient and maximum loading. 2. For SEL and LE# inputs 08-0147 5 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Dynamic Electrical Characteristics for IN_x+/-, Rxy+/-, and Txy+/Parameter Description Test Conditions Min. Typ.(1) DDIL Differential Insertion Loss f=1.2GHz f=2.5GHz f=5.0GHz f=7.5GHz -1.5 -2.0 -5.0 -9.0 DDILOFF Differential Off Isolation f= 0 to 3.0GHz f= 5.0GHz -23.0 -20.0 DDRL Differential Return Loss f= 0 to 2.8GHz f= 2.8 to 5.0GHz f= 5.0 to 7.5GHz -14.0 -8.0 -4.0 DDNEXT Near End Crosstalk f= 0 to 2.5GHz f= 2.5 to 5.0GHz f= 5.0 to 7.5GHz -32.0 -26.0 -20.0 Max. Units dB Dynamic Electrical Characteristics for Dx+/Parameter Description Test Conditions Min. Typ.(1) DDILDP Display Port Differential Insertion Loss f= 0 to 1.35GHz f= 1.35 to 2.7GHz -1.5 -4.5 DDRLDP Display Port Differential Return Loss f= 0 to 2.7GHz -14 Display Port Near End Crosstalk f= 0 to 2.7GHz -32.0 DDNEXTDP Max. Units dB Switching Characteristics (TA= -40º to +85ºC, VDD = 3.3V±10%) Parameter Description Test Conditions Min. Typ. Max. Units tPZH, tPZL Line Enable Time - SEL to DX±, TXY±, RXY±, AUX±, HPD See "Test Circuit for Electrical Characteristics" 0.5 12.0 ns tPHZ, tPLZ Line Disable Time - SEL to DX±, TXY±, RXY±, AUX±, HPD See "Test Circuit for Electrical Characteristics" 0.5 12.0 ns tb-b Bit-to-bit skew within the same differential See "Test Circuit for Electripair cal Characteristics" 7 ps tch-ch Channel-to-channel skew See "Test Circuit for Electrical Characteristics" 35 ps 08-0147 6 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Differential Insertion Loss Differential Return Loss 08-0147 7 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Off Isolation Crosstalk 08-0147 8 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Tx Eye Diagram, 5.0 Gbps Dx Eye Diagram, 2.7 Gbps 08-0147 9 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Test Circuit Test Circuit Test Circuit 08-0147 10 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Test Circuit for Electrical Characteristics(1-5) Switch Positions 2 x VDD VDD 200-ohm Pulse Generator VIN D.U.T VOUT 4pF CL RT Test Switch tPLZ, tPZL 2 x VDD tPHZ, tPZH GND Prop Delay Open 200-ohm Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR ” MHz, ZO = 50ȍ, tR ” 2.5ns, tF ” 2.5ns. 5. The outputs are measured one at a time with one transition per measurement. Switching Waveforms VDD SEL VDD/2 VDD/2 0V Output 1 tPZL tPLZ VDD/2 VOH VOL + 0.15V tPHZ tPZH VOH – 0.15V VDD/2 VOL VOH VOL Output 2 Voltage Waveforms Enable and Disable Times 08-0147 11 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Applications Information Differential Input Characteristics for IN_x+/- and Rxx+/- signals. Symbol Parameter Min Nom Max Tbit Unit Interval 199.94 200.00 200.06 VRX-Diffp-p Differential Input Peak 0.175 1.200 to Peak Voltage TRX-EYE VCM-AC-pp Minimum Eye Width at TBD IN_D input pair. AC Peak CommonMode Input Voltage Units Ps V Tbit 100 mV ZRX-DIFF-DC DC Differential Input Impedance ZRX-DC DC Input Impedance 80 100 120 Ω 40 50 60 Ω VRX-Bias Rx input termination voltage 0 2.0 V DDIL Differential Insertion Loss DDRL Differential Return Loss DDNEXT Near End Crosstalk •-[0.6*(f)+0.5] dB up to 2.5 GHz (for example, •-2 dB at f = 2.5 GHz); •-[1.2*(f-2.5)+2] dB for 2.5 GHz < f ” 5 GHz (for example, •-5 dB at f = 5 GHz); •-[1.6*(f-5)+5] dB for 5 GHz < f ” 7.5 GHz (for example, •-9 dB at f = 7.5 GHz); ” -14 dB up to 2.8 GHz; ” -8 dB up to 5 GHz; ” -4 dB up to 7.5 GHz. -32 dB max up to 2.5 GHz; 26 dB max up to 5.0 GHz; -20 dB max up to 7.5 GHz; ” -20 dB up to 3 GHz; DDIL when Differential Insertion switch is off Loss when switch is off 08-0147 Comments De¿ned by Gen2 spec. VRX-DIFFp-p = 2*|VRXD+ - VRX-D-|. Applies to IN_D and RX_IN signals. 12 VCM-AC-pp = |VRX-D+ + VRX-D-| / 2 – VRX-CM-DC. VRX-CM-DC = DC(avg) of |VRX-D++ VRX-D-| / 2 VCM-AC-pp includes all frequencies above 30kHz. Rx DC Differential Mode impedance. Required IN_D+ as well as IN_D- DC impedance (50 Ω +/- 20% tolerance). Includes mux resistance. Intended to limit powerup stress on PCIE output buffers. dB dB dB dB PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout PCIe Gen2 Output Characteristics Symbol Parameter ZRX-DIFF-DC DC Differential Input Impedance ZRX-DC DC Input Impedance Min 80 Nom 100 Max 120 Units Ω 40 50 60 Ω 2.0 V VRX-Bias Rx input termination volt- 0 age DDIL Differential Insertion Loss DDRL Differential Return Loss DDNEXT Near End Crosstalk DDIL when switch is off Differential Insertion Loss when switch is off 08-0147 •-[0.6*(f)+0.5] dB up to 2.5 GHz (for example, •-2 dB at f = 2.5 GHz); •-[1.2*(f-2.5)+2] dB for 2.5 GHz < f ” 5 GHz (for example, •-5 dB at f = 5 GHz); •-[1.6*(f-5)+5] dB for 5 GHz < f ” 7.5 GHz (for example, •-9 dB at f = 7.5 GHz); ” -14 dB up to 2.8 GHz; ” -8 dB up to 5 GHz; ” -4 dB up to 7.5 GHz. -32 dB max up to 2.5 GHz; -26 dB max up to 5.0 GHz; -20 dB max up to 7.5 GHz; ” -20 dB up to 3 GHz; 13 Comments Rx DC Differential Mode impedance. Required IN_D+ as well as IN_D- DC impedance (50Ω +/- 20% tolerance). Includes mux resistance. Intended to limit power-up stress on PCIE output buffers. dB dB dB dB PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Display Port Output Characteristics Symbol Parameter Tbit Unit Interval Min 333 Nom Max Units ps VRX-Diffp-p Differential Input Peak to 0.340 Peak Voltage 1.38 V TJIT Jitter added to high-speed signals 7.4 ps DDIL Differential Insertion Loss DDRL DDNEXT Differential Return Loss Near End Crosstalk HPD Input Characteristics Symbol Parameter VIH-HPD Input high level VIL-HPD IIN_HPD HPD Input Low Level HPD input leakage current THPD HPD_IN to HPD propagation delay. TRF-HPD HPD rise/fall time. Termination Resistors Symbol Parameter RDDC DDC Termination Resistors 08-0147 •-[0.75*(f)+0.5] dB up to 1.35 GHz; •-[2.2*(f-1.35)+1.5] dB for 1.35 GHz < f ” 2.7 GHz ” -14 dB up to 2.7 GHz -32 dB max up to 2.7 GHz dB Min Max 3.6 Units V |10| uA 200 ns 20 ns Max 2.2k Units W Nom dB dB 0 1 Min 1.3K Nom 1.5k 14 Comments Normal Tbit at 2.7Gb/ s=370ps. 333ps=370ps10% VRX-DIFFp-p = 2*|VRX-D+ - VRX-D|. Applies to IN_D and RX_IN signals. Jitter budget for highspeed signals as they pass through the display mux. 7.4ps = 0.02 Tbit at 2.7Gb/s For example, •-1.5 dB at f = 1.35 GHz For example, •-4.5 dB at f = 2.7 GHz Comments Low-speed input changes state on cable plug/ unplug. V Measured with HPD at VIH-HPD max and VIL-HPD min Time from HPD_IN changing state to HPD changing state. Includes HPD rise/fall time. Time required to transition from VOH-HPD to VOL-HPD or from VOL-HPD to VOHHPD. Comments Applies to both 3.3V and 5V pull up resistors. PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Switch Signal Integrity Requirements and Test Procedures for 5.0 Gb/s Signal integrity requirements for 5.0 Gb/s applications of the switch are speci¿ed. Also included are the requirements of the test ¿xture for switch S-parameter measurements. Signal Integrity Requirements The procedures outlined in ANSI Electronics Industry Alliance (EIA) standards documents shall be followed: • EIA 364-101 – Attenuation Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems • EIA 364-90 – Crosstalk Ratio Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems • EIA 364-108- Impedance, ReÀection Coef¿cient, Return Loss, and VSWR Measured in the Time and Frequency Domain Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems Signal Integrity Requirements and Test Procedures for 5.0 Gb/s Parameter Differential Insertion Loss (DDIL) Procedure EIA 364-101 The EIA standard shall be used with the following considerations: 1. The measured differential S parameter shall be referenced to a 100 ohms differential impedance. 2. The test ¿xture shall meet the test ¿xture requirement de¿ned in Section 1.12. 3. The test ¿xture effect shall be removed from the measured S parameters. Refer to Note 1. Differential EIA 364-108 Return Loss The EIA standard shall be used with the following considerations: (DDRL) 1. The measured differential S parameter shall be referenced to a 100 ohms differential impedance. 2. The test ¿xture shall meet the test ¿xture requirement in Section 1.12. 3. The test ¿xture effect shall be removed. Refer to Note 1. Intra-pair Skew Intra-pair skew must be achieved by design; measurement not required. Differential Near EIA 364-90 End Crosstalk The EIA standard must be used with the following considerations: (DDNEXT) 1. The crosstalk requirement is with respect to all the adjacent differential pairs Differential EIA 364-101 Insertion Loss (DDIL) when switch is turned off Requirements •-[0.6*(f)+0.5] dB up to 2.5 GHz (for example, •-2 dB at f = 2.5 GHz); •-[1.2*(f-2.5)+2] dB for 2.5 GHz < f ” 5 GHz (for example, •-5 dB at f = 5 GHz); •-[1.6*(f-5)+5] dB for 5 GHz < f ” 7.5 GHz (for example, •-9 dB at f = 7.5 GHz); Refer to Figure 1. ” -14 dB up to 2.8 GHz; ” -8 dB up to 5 GHz; ” -4 dB up to 7.5 GHz. Refer to Figure 2. 5 ps max -32 dB max up to 2.5 GHz; -26 dB max up to 5.0 GHz; -20 dB max up to 7.5 GHz; See Figure 3. ” -20 dB up to 3 GHz; Notes: 1. The speci¿ed S parameters requirements are for switch component only, not including the test ¿xture effect. While the TRL calibration method is recommended, other calibration methods are allowed. 08-0147 15 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout 0 SDD21 Zref=100 Ohms -1 Differential Insertion Loss [dB] -2 -3 -4 -5 -6 -7 -8 -9 -10 0 1 2 3 4 5 6 7 8 9 10 Frequency, GHz Figure 1: Illustration of differential insertion loss requirement. 0 SDD11 Zref=100 Ohms Differential Return Loss [dB] -5 -10 -15 -20 -25 -30 0 1 2 3 4 5 6 7 8 9 10 Frequency, GHz Figure 2: Illustration of differential return loss requirement. 08-0147 16 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout -10 SDD21 Zref=85 Ohms Differential Near End Crosstalk, dB -15 -20 -25 -30 -35 -40 -45 0 1 2 3 4 5 Frequency, GHz 6 7 8 Figure 3: Illustration of different ial near end crosstalk requirement. Switch Test Fixture Requirements The test ¿xture for switch S-parameter measurement shall be designed and built to speci¿c requirements, as described below, to ensure good measurement quality and consistency: • The test ¿xture shall be a FR4-based PCB of the microstrip structure; the dielectric thickness or stackup shall be about 4 mils. • The total thickness of the test ¿xture PCB shall be 1.57 mm (0.62”). • The measurement signals shall be launched into the switch from the top of the test ¿xture, capturing the through-hole stub effect. • Traces between the DUT and measurement ports (SMA or microprobe) should be uncoupled from each other, as much as possible. Therefore, the traces should be routed in such a way that traces will diverge from each other exiting from the switch pin ¿eld. • The trace lengths between the DUT and measurement port shall be minimized. The maximum trace length shall not exceed 1000 mils. The trace lengths between the DUT and measurement port shall be equal. • All of the traces on the test board and add-in card must be held to a characteristic impedance of 50 Ohms with a tolerance of +/- 7%. • SMA connector is recommended for ease of use. The SMA launch structure shall be designed to minimize the connection discontinuity from SMA to the trace. The impedance range of the SMA seen from a TDR with a 60 ps rise time should be within 50+/-7 ohms. 08-0147 17 PS8932C 07/31/08 PI3PCIE2612-B High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, BTX Pinout Packaging Mechanical: 56-Contact TQFN (ZFE) DATE: 05/15/08 DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 DOCUMENT CONTROL #: PD-2024 REVISION: C Ordering Information Ordering Code PI3PCIE2612-BZFE Package Code Package Description ZF Pb-free & Green, 56-contact TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 08-0147 18 PS8932C 07/31/08