PART OBSOLETE - USE PI3PCIE3412A
A product Line of
Diodes Incorporated
PI3PCIE3412
3.3V, PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch, with Single Enable
Features
Description
•
•
•
•
•
•
•
•
•
•
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The PI3PCIE3412 is an 8 to 4 differential channel multiplexer/
demultiplexer switch. This solution can switch 2 full PCI
Express® 3.0, lanes to one of two locations. Using a unique design
technique, Diodes has been able to minimize the impedance of
the switch such that the attenuation observed through the switch
is minimal. The unique design technique also offers a layout
targeted for PCI Express signals, which minimizes the channel to
channel skew as well as channel to channel crosstalk as required
by the PCI Express specification. PI3PCIE3412 can also be used
for application up to 12Gbps
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4 Differential Channel, 2:1 Mux/DeMux
PCI Express® 3.0 Performance, 8.0Gbps
Bi-directional Operation
Low Bit-to-Bit Skew, 10ps max
Low channel-to-channel skew, 20ps max
Low Crosstalk: -35dB@4 GHz
High Off Isolation: -22dB@4 GHz (8.0Gbps)
Low insertion loss: -1.3dB@4 GHz (8.0Gbps)
Return loss: -21dB@4 GHz
Support for DP1.2 - HBR2, HBR, RBR
Supply Voltage 3.3V
Industrial Temperature Range: -40oC to 85oC
Packaging (Pb-free & Green):
– 42-contact, TQFN (ZH42), 3.5 x 9mm
– 40-contact, TQFN (ZL40), 3 x 6mm
Application
Routing of PCI Express 3.0, DP1.2, USB3.0, SAS2.0, SATA3.0,
XAUI, RXAUI signals with low signal attenuation.
Pin Configuration - 42- Contact TQFN
GND
GND
VDD
GND
B0+
B0-
VDD
GND
VDD
GND
Pin Configuration - 40- Contact TQFN
A0+
A0VDD
A1+
A1VDD
SEL
GND
A2+
A2VDD
GND
A3+
A3-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
40 39 38 37 36 35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A0+
A0GND
VDD
A1+
A1VDD
SEL
GND
A2+
A2VDD
GND
A3+
A3GND
B1+
B1C0+
C0C1+
C1VDD
GND
B2+
B2B3+
B3C2+
C2-
42 41 40 39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
B0+
B0B1+
B1C0+
C0C1+
C1VDD
B2+
B2B3+
B3C2+
C2C3+
C3-
18 19 20 21
VDD
GND
VDD
GND
C3C3+
GND
GND
VDD
GND
15 16 17 18 19 20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
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PI3PCIE3412
Block Diagram
A0+
B0+
A0-
B0-
A1+
B1+
A1-
B1-
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C0+
C0-
C1+
C1-
A2+
B2+
A2-
B2-
A3+
B3+
A3-
B3-
C2+
C2-
C3+
C3-
SEL
Truth Table
Function
SEL
AN to BN
L
AN to CN
H
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PI3PCIE3412
Pin Description
Pin #
40-TQFN
Pin Name
2
1
A0+
3
2
A0–
6
4
A1+
5
A1–
9
A2+
10
A2–
13
A3+
14
A3–
36
B0+
35
B0−
34
B1+
33
B1−
26
B2+
25
B2−
24
B3+
23
B3−
32
C0+
31
C0–
30
C1+
29
C1–
22
C2+
21
C2–
20
C3+
19
C3−
7
SEL
I
3, 6, 11, 17,
28, 38
V DD
Pwr
3.3V ±10% Positive Supply Voltage
GND
Pwr
Power ground
7
11
12
15
16
38
37
36
35
29
28
27
26
34
33
32
31
25
24
23
22
9
I/O
Description
I/O
Signal I/O, Channel 0, Port A
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42-TQFN
5, 8, 13,18,
20, 30, 40,
42
1, 4, 10, 14,
8, 12, 15, 16,
17, 19, 21, 39,
18, 27, 37,
41, Center
39, 40
Pad
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I/O
Signal I/O, Channel 1, Port A
I/O
Signal I/O, Channel 2, Port A
I/O
Signal I/O, Channel 3, Port A
I/O
Signal I/O, Channel 0, Port B
I/O
Signal I/O, Channel 1, Port B
I/O
Signal I/O, Channel 2, Port B
I/O
Signal I/O, Channel 3, Port B
I/O
Signal I/O, Channel 0, Port C
I/O
Signal I/O, Channel 1, Port C
I/O
Signal I/O, Channel 2, Port C
I/O
Signal I/O, Channel 3, Port C
Operation mode Select
(when SEL=0: A→B, when SEL=1: A→C
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PI3PCIE3412
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
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Storage Temperature .....................................................–65°C to +150°C
Supply Voltage to Ground Potential ................................–0.5V to +4.6V
Channel DC Input Voltage ................................................. –0.5V to 1.5V
DC Output Current ....................................................................... 120mA
Power Dissipation ............................................................................ 0.5W
SEL DC Input Voltage ....................................................... –0.5V to 4.6V
Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
VDD
3.3V Power Supply
IDD
Total current from VDD 3.3V supply
Conditions
Min.
Typ.
Max.
Units
3.0
3.3
3.6
V
0.15
1
mA
1.6
Vppd
0
0.8
-40
85
V
oC
SEL = 0V or VDD
VI/O-DIF
Differential Voltage (differential pins)
VI/O-CM
Common Mode Voltage (differiential pins)
TA
Operating temperature range
DC Electrical Characteristics for Switching over Operating Range
Parameters Description
Test Conditions(1)
Min. Typ.(1)
Max.
Units
VIH - SEL
Input HIGH Voltage, SEL Input
2
3.6
VIL - SEL
Input LOW Voltage, SEL Input
0
0.8
VIK
Clamp Diode Voltage
VDD = Max., IIN = –18mA
Input HIGH Current, SEL
VDD = Max., VIN = VDD
±5
Input LOW Current, SEL
VDD = Max., VIN = 0V
±5
IIN - SEL
Input Leakage Current, SEL Input
VIN = VIH - SEL Max or VIL - SEL Min
–10
+10
IIH
Input HIGH Current, A X, BX, CX
VDD = Max., VIN = 1.5V
–10
+10
Input LOW Current, A X, BX, CX
VDD = Max., VIN = 0V
–10
+10
IOZH
HighZ HIGH Current, BX, CX
VDD = Max., VIN = 1.5V
–10
+10
µA
IOZL
HighZ LOW Current, BX, CX
VDD = Max., VIN = 0V
–10
+10
µA
CI/O-ON
ON state I/O capacitance
IIH
IIL
IIL
–0.7
RON
ON state resistance
VDD = 3.3V, IO = 8mA, VIN = 0.8V
Note:
1. Typical values are at VDD = 3.3V, TA = 25°C ambient and maximum loading.
V
–1.2
µA
µA
µA
1.5
pF
5
Ω
Switching Characteristics
Parameters
Description
tPZH, tPZL
Min.
Typ.
Max.
Line Enable Time - SEL to AN, BN, CN
2
20
25
tPHZ , tPLZ
Line Disable Time - SEL to AN, BN, CN
0.5
5
25
tb-b
Bit-to-bit skew within the same differential pair
5
10
ps
tch-ch
Channel-to-channel skew
20
ps
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Test Conditions
4
Units
ns
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PI3PCIE3412
Dynamic Electrical Characteristics
Typ.(1)
Max.
f= 50MHz - 1.25GHz
-0.8
-1
Differential Insertion Loss
f=1.25GHz - 2.5GHz
-1.0
-1.2
(VIN = -10dBm, DC = 0V)
f=2.5GHz - 4GHz
-1.3
-1.6
f=5GHz
-1.8
-2.2
Parameter Description
DDILOFF
Differential Off Isolation
DDRL
Differential Return Loss
DDNEXT
VI F
BW
Min.
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DDIL
Test Conditions
Near End Crosstalk
Max Signal Frequency Range
f= 50MHz - 1.25GHz
-26.3
-32.9
f=1.25GHz - 2.5GHz
-21.4
-26.7
f=2.5GHz - 4GHz
-17.6
-22
f=5GHz
-16
-20
f= 50MHz - 1.25GHz
-20
-25
f=1.25GHz - 2.5GHz
-18.4
-23
f=2.5GHz - 4GHz
-16.8
-21
f=5GHz
-9.6
-12
f= 50MHz - 1.25GHz
-34.1
-42.6
f=1.25GHz - 2.5GHz
-30.5
-38.1
f=2.5GHz - 4GHz
-28.1
-35.1
f=5GHz
-27.2
-34
Insertion loss 1.5dB,
VIN=0.623Vpp, DC=0V
4.0
Insertion loss 1.5dB,
VIN=0.623Vpp, DC=0.9V
4.0
Insertion loss 3dB,
VIN=0.623Vpp, DC=0V
8.0
Insertion loss 3dB,
VIN=0.623Vpp, DC=0.9V
8.0
-3dB Bandwidth
8.2
Units
dB
dB
dB
dB
GHz
GHz
Notes:
1. Guaranteed by design. Typical values are at VDD = 3.3V , Ta = 25°C ambient and maximum loading.
+
+
BALANCED
PORT1
–
BALANCED
PORT1
+
+
50
–
–
50
BALANCED
– PORT2
+
–
DUT
BALANCED
PORT2
DUT
Diff. Insertion Loss and Return Test
Circuit
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Diff. Off Isolation Test Circuit
5
BALANCED
PORT1
BALANCED
PORT2
+
+ 50
–
– 50
+
+ 50
–
– 50
DUT
Diff. Near End Xtalk Test Circuit
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PI3PCIE3412
Differential Insertion Loss
Differential Return Loss
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PI3PCIE3412
Differential Off Isolation
Differential Crosstalk
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PI3PCIE3412
5.0 Gbps RX signal eye without PI3PCIE3412
5.0 Gbps RX signal eye with PI3PCIE3412
8.0 Gbps RX signal eye without PI3PCIE3412
8.0 Gbps RX signal eye with PI3PCIE3412
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PI3PCIE3412
Test Circuit for Electrical Characteristics(1-5)
Switch Positions
VDD
Port1
COM Port
Switch
tPLZ , tPZL
3.0V
tPHZ , tPZH
GND
Prop Delay
Open
N
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Port2
D.U.T
Test
4pF
CL
xEN
200-ohm
Pulse
Notes:
Generator
1. CL = Load capacitance: includes jig and probe capacitance.
2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator
3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Output 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.
5. The outputs are measured one at a time with one transition per measurement.
Switching Waveforms
xEN
VDD
50%
50%
0V
Output 1
Tsw
Tsw
VOH
50%
VOL
Tsw
Tsw
VOH
50%
VOL
Output 2
Voltage Waveforms Enable and Disable Times
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PI3PCIE3412
DP1.2 Application
C101
C102
C103
C104
C105
C106
1u_0805
0.1u_0402
0.1u_0402
0.1u_0402
0.1u_0402
3V3_1
DP Source 1
4.7u_0805
3V3_1
At least 1pc 4.7uF and 4pc 0.1uF
decoupling capacitors are
recommended.
Each decoupling capacitor should
be connected to PCB power plane
via shortest path.
3V3_1
C107
DP_LANEx
AUX_N1
AUX_P1
C108
1u_0805
C109
C110
0.1u_0402
0.1u_0402
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
50
DP_LANEx#
Same goes for
other 3 lanes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND
A0+
A0GND
VDD
A1+
A1VDD
SEL
GND
A2+
A2VDD
GND
A3+
A3GND
HEATGND
VDD
GND
VDD
GND
(0 - 1.2V)
VDD
GND
VDD
GND
50
DP
TX
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
B0+
B0B1+
B1C0+
C0C1+
C1VDD
B2+
B2B3+
B3C2+
C2C3+
C3-
C111
0.1u_0402
C112
0.1u_0402
C113
0.1u_0402
C114
0.1u_0402
C115
0.1u_0402
C116
0.1u_0402
C117
0.1u_0402
C118
0.1u_0402
18
19
20
21
3V3_1
C119
DP_AUX
50
AUX
TX
AUX_N2
AUX_P2
VDD and GND pins should be
shorted to PCB power planes
via shortest paths.
(0 - 1.2V)
50
DP_AUX#
0.1u_0402
0.1u_0402
C125
0.1u_0402
C126
0.1u_0402
C127
5V_1 and 3V3_1 should be
employed at the same time.
AUX
RX
5V_1
U102
DP_HPD
C123
C124
AUX_P1
AUX_P2
DP_AUX
AUX_N1
AUX_N2
DP_AUX#
1
2
3
4
5
6
7
8
IN VDD
S1A #EN
S2A S1D
DA S2D
S1B DD
S2B S1C
DB S2C
GND DC
16
15
14
13
12
11
10
9
0.1u_0402
C128
0.1u_0402
C129
0.1u_0402
C130
0.1u_0402
LCD_VCC
LCD_VCC
LCD_VCC LCD_Self_Test
LCD_VCC
LCD_GND
H_GND
LCD_GND
AUX_CH_N
LCD_GND
LCD_GND
AUX_CH_P
H_GND
HPD
Lane0_P
BL_GND
Lane0_N
BL_GND
H_GND
BL_GND
Lane1_P
BL_GND
Lane1_N
BL_ENABLE
BL_PWM_DIM
H_GND
Lane2_P
NC
Lane2_N
NC
H_GND
BL_PWR
Lane3_P
BL_PWR
Lane3_N
BL_PWR
H_GND
BL_PWR
NC
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HPD1
4Lane eDP Source Receptacle
PI3PCIE3412
Vbias_TX
3V3_1
J101
N
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U101
43
42
41
40
39
Vbias_TX
0.1u_0402
0.1u_0402
C120
1u_0805
C121
C122
0.1u_0402
0.1u_0402
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3V3_1
J102
LCD_VCC
LCD_VCC
LCD_VCC LCD_Self_Test
LCD_VCC
LCD_GND
H_GND
LCD_GND
AUX_CH_N
LCD_GND
AUX_CH_P
LCD_GND
H_GND
HPD
Lane0_P
BL_GND
Lane0_N
BL_GND
H_GND
BL_GND
Lane1_P
BL_GND
Lane1_N
BL_ENABLE
H_GND
BL_PWM_DIM
Lane2_P
NC
Lane2_N
NC
H_GND
BL_PWR
Lane3_P
BL_PWR
Lane3_N
BL_PWR
H_GND
BL_PWR
NC
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
HPD2
4Lane eDP Source Receptacle
HPD1
HPD2
DP_HPD
PI5V330
C131
0.1u_0402
SEL_GPIO1
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Packaging Information
Notes:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220
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DATE: 07/11/13
DESCRIPTION: 40-contact, Thin Fine Pitch Quad Flat No-Lead, TQFN
PACKAGE CODE: ZL (ZL40)
DOCUMENT CONTROL #: PD-2165
11
REVISION: --
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PI3PCIE3412
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Packaging Information
Note: For latest package info, please check: http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics/
Ordering Information
Ordering Code
Package Code
Package Description
PI3PCIE3412ZLE
ZL
40-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PI3PCIE3412ZLEX
ZL
40-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN), Tape & Reel
PI3PCIE3412ZHE
ZH
42-contact, Very Thin Quad Flat No-Lead (TQFN)
PI3PCIE3412ZHEX
ZH
42-contact, Very Thin Quad Flat No-Lead (TQFN), Tape & Reel
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
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PI3PCIE3412
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER
THE LAWS OF ANY JURISDICTION).
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Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or
any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer
or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all
the companies whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes
Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein
may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval
of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably
expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge
and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated
products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by
Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes
Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
All trademarks are property of their respective owners.
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