PI3PCIE3415AZHEX

A product Line of Diodes Incorporated PI3PCIE3415A 3.3V, PCI Express® 3.0 2-Lane, 2:1 Mux/DeMux Switch Features Description ÎÎ4 Differential Channel, 2:1 Mux/DeMux The PI3PCIE3415A is an 8 to 4 differential channel multiplexer/ demultiplexer switch. This solution can switch 2 full PCI Express® 3.0, lanes to one of two locations. Using a unique design technique, Diodes has been able to minimize the impedance of the switch such that the attenuation observed through the switch is negligible. The unique design technique also offers a layout targeted for PCI Express signals, which minimizes the channel to channel skew as well as channel to channel crosstalk as required by the PCI Express specification. ÎÎPCI Express® 3.0 Performance, 8.0Gbps ÎÎPinout optimized for placement between two PCIe slots ÎÎBi-directional operation ÎÎLow Bit-to-Bit Skew, 10ps max ÎÎLow Crosstalk: -48dB @4GHz ÎÎHigh Off Isolation: -22dB @4GHz ÎÎLow Insertion Loss: -1.2dB @4GHz ÎÎReturn Loss: -15dB @4GHz Application ÎÎVDD Operating Range: +3.3V Routing of PCI Express 3.0, DP1.2, USB3.0, SAS2.0, SATA3.0, XAUI, RXAUI signals with low signal attenuation. ÎÎIndustrial Temperature Range: -40oC to 85oC ÎÎESD Tolerance: 1.5kV HBM ÎÎLow channel-to-channel skew, 20ps max ÎÎPackaging (Pb-free & Green): àà 42-contact, TQFN (ZH42), 3.5 x 9mm àà 40-contact, TQFN (ZL40), 3 x 6mm Block Diagram AI + AI – BI + BI – CI + CI – DI + DI – Truth Table AOa + AOa – BOa + BOa – AOb + AOb – BOb + BOb – COa + COa – DOa + DOa – Function SEL xIy to xOay L xIy to xOby H COb + COb – DOb + DOb – SEL PI3PCIE3415A Document Number DS40126 Rev 1-2 1 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Pin Description 42-Contact TQFN (Top-Side View) AIAI+ GND GND VDD GND GND VDD GND VDD Pin Description 40-Contact TQFN (Top-Side View) AOb+ AObBI+ BIBOb+ BObVDD GND CI+ CICOb+ CObDI+ DI- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 40 39 38 37 36 35 AI+ AI34 33 32 31 30 29 28 27 26 25 24 23 22 21 AOa+ AOaVDD BOa+ BOaGND VDD SEL GND COa+ COaVDD DOa+ DOa- AOb+ AObBI+ BIBOb+ BObVDD CI+ CICOb+ CObDI+ DIDOb+ DOb- PI3PCIE3415A Document Number DS40126 Rev 1-2 42 41 40 39 GND 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 GND AOa+ AOaGND VDD BOa+ BOaVDD SEL GND COa+ COaVDD GND DOa+ DOaGND 18 19 20 21 GND VDD GND VDD VDD GND GND DOb+ DObGND 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Signal Descriptions Pin Number 42-TQFN 40-TQFN Pin Name Type Description 1, 2 39, 40 AI+, AI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the AOa+, AOa- pin respectively when SEL=0. Signal is routed to the AOb+, AOb- pin respectively when SEL = 1. 37, 36 34, 33 AOa+, AOa- Differential I/O Differential analog pass-through I/O. Signal from AI+ and AI- is routed to AOa+ and AOa- respectively when SEL=0. 3, 4 1, 2 AOb+, AOb- Differential I/O Differential analog pass-through I/O. Signal from AI+ and AI- is routed to AOb+ and AOb- respectively when SEL=1. 5, 6 3, 4 BI+, BI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the BOa+, BOa- pin respectively when SEL=0. Signal is routed to the BOb+, BOb- pin respectively when SEL = 1. 33, 32 31, 30 BOa+, BOa- Differential I/O Differential analog pass-through I/O. Signal from BI+ and BI- is routed to BOa+ and BOa- respectively when SEL=0. 7, 8 5, 6 BOb+, BOb- Differential I/O Differential analog pass-through I/O. Signal from BI+ and BI- is routed to BOb+ and BOb- respectively when SEL=1. 10, 11 9, 10 CI+, CI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the COa+, COa- pin respectively When SEL=0. Signal is routed to the COb+, COb- pin respectively when SEL = 1. 28, 27 25, 24 COa+, COa- Differential I/O Differential analog pass-through I/O. Signal from CI+ and CI- is routed to COa+, COa- pin respectively when SEL = 0. 12, 13 11, 12 COb+, COb- Differential I/O Differential analog pass-through I/O. Signal from CI+ and CI- is routed to COb+, COb- pin respectively when SEL = 1. 14, 15 13, 14 DI+, DI- Differential I/O Differential I/O pair from PCIE signal source. Signal is routed to the DOa+, DOa- pin respectively When SEL=0. Signal is routed to the DOb+, DOb- pin respectively when SEL = 1. 24, 23 22, 21 DOa+, DOa- Differential I/O Differential analog pass-through I/O. Signal from DI+ and DI- is routed to DOa+, DOa- pin respectively when SEL = 0. 16, 17 16, 17 DOb+, DOb- Differential I/O Differential analog pass-through I/O. Signal from DI+ and DI- is routed to DOb+, DOb- pin respectively when SEL = 1. 18, 20, 22, 15, 18, 20, 26, 25, 29, 35, 38, 29, 35, 37, 38, GND 40, 42 Center Pad Ground input Ground 30 27 SEL 3.6V tolerant low-voltage SEL controls the mux through a flow-through latch. single-ended input 9, 19, 21, 26, 31, 34, 39, 41 7, 19, 23, 28, 32, 36 VDD Power supply PI3PCIE3415A Document Number DS40126 Rev 1-2 Power, 3.3V ±10% 3 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................................–65°C to +150°C Supply Voltage to Ground Potential .................................–0.5V to +3.7V Channel DC Input Voltage ................................................. –0.5V to 1.5V DC Output Current ........................................................................ 120mA SEL DC Input Voltage ....................................................... –0.5V to 3.7V Junction Temperature...................................................................... 125°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics Recommended Operating Conditions Symbol Parameter VDD 3.3V Power Supply IDD Total current from VDD 3.3V supply TA Operating temperature range Conditions SEL = 0V or VDD Min. Typ. Max. Units 3.0 3.3 3.6 V 0 0.15 1 mA 85 oC Max. Units -40 DC Electrical Characteristics (TA = –40°C to +85°C, VDD = 3.3V ± 10%) Test Conditions Min. Typ.(1) Parameter Description VIH-SEL Input high level, SEL input 2.0 3.6 V VIL-SEL Input Low Level, SEL input 0 0.8 V IIN_SEL Input Leakage Current, SEL input Measured with input at VIH-SEL max and VIL-SEL min –10 10 uA IIH Input High Current, xI, xO VDD = Max, VIN = 1.5V –10 10 uA IIL Input Low Current, xI, xO VDD = Max, VIN = 0V –10 10 uA IIH Input High Current, SEL VDD = Max, VIN = VDD –5 5 uA IIL Input Low Current, SEL VDD = Max, VIN = 0V –5 5 uA IOZH HighZ High Current xOa, xOb VDD = Max, VIN = 1.5V –10 10 uA IOZL HighZ Low Current xOa, xOb VDD = Max, VIN = 0V –10 10 uA Note: 1. Typical values are at V DD = 3.3V, TA = 25°C ambient and maximum loading. PI3PCIE3415A Document Number DS40126 Rev 1-2 4 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Dynamic Electrical Characteristics for xI+/-, xOy+/Parameter DDIL DDILOFF DDRL DDNEXT Description Differential Insertion Loss Differential Off Isolation Differential Return Loss Near End Crosstalk Test Conditions Typ.(1) Max. f=50MHz -1.25GHz -0.8 -1.0 f=1.25GHz - 2.5GHz -1.1 -1.3 f=2.5GHz - 4GHz -1.2 -1.5 f=5.0GHz -1.7 -2.0 -25.8 -32.2 -20.6 -25.8 -17.6 -22.0 -15.4 -19.3 f=50MHz - 1.25GHz -18.2 -22.7 f=1.25GHz - 2.5GHz -16.8 -21.0 f=2.5GHz - 4GHz -12 -15.0 f=5.0GHz -8 -10.0 f=50MHz -1.25GHz -44.8 -56 f=1.25GHz - 2.5GHz -41.6 -52 f=2.5GHz - 4GHz -38.4 -48 -36 -45 f= 0 to 4.0GHz f=5.0GHz BW Min. Bandwidth -3dB Units dB 8.4 GHz Switching Characteristics Parameter Description tPZH, tPZL Line Enable Time - SEL to xI+/-, xOy+/- tPHZ , tPLZ Line Disable Time - SEL to xI+/-, xOy+/- tb-b Bit-to-bit skew within the same differential See "Test Circuit for pair Electrical Characteristics" tch-ch Channel-to-channel skew PI3PCIE3415A Document Number DS40126 Rev 1-2 Test Conditions See "Test Circuit for Electrical Characteristics" See "Test Circuit for Electrical Characteristics" See "Test Circuit for Electrical Characteristics" 5 Min. Typ. Max. Units 0.5 15 25 ns 0.5 5 25 ns 4 10 ps 20 ps www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A 5.0 Gbps RX signal eye without PI3PCIE3415A 5.0 Gbps RX signal eye with PI3PCIE3415A 8.0 Gbps RX signal eye without PI3PCIE3415A 8.0 Gbps RX signal eye with PI3PCIE3415A PI3PCIE3415A Document Number DS40126 Rev 1-2 6 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Differential Insertion Loss Differential Return Loss PI3PCIE3415A Document Number DS40126 Rev 1-2 7 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Differential Off Isolation Differential Crosstalk PI3PCIE3415A Document Number DS40126 Rev 1-2 8 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Test Circuit for Electrical Characteristics(1-5) 3.0 V VDD 200-ohm Pulse Generator VIN SEL VOUT D.U.T 4pF CL RT *VOUT = Port 1 or Port 2 200-ohm tpZH/HZ = COM Port is High tpLZ/ZL = COM Port is Low Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns. 5. The outputs are measured one at a time with one transition per measurement Switch Positions Test Switch tPLZ , tPZL 3.0V tPHZ , tPZH GND Switching Waveforms SEL 1.5V VDD/2 VDD 0V Output 1 tPZL tPLZ 1.5V VOH VOL + 0.15V tPHZ tPZH VOH – 0.15V 1.5V VOL VOH VOL Output 2 Voltage Waveforms Enable and Disable Times PI3PCIE3415A Document Number DS40126 Rev 1-2 9 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A BALANCED PORT1 + BALANCED PORT1 + + + 50 – – 50 BALANCED – PORT2 – + – DUT DUT Differential Off Isolation Test Circuit Differential Insertion Loss and Return Test Circuit BALANCED PORT1 BALANCED PORT2 BALANCED PORT2 + + 50 – – 50 + + 50 – – 50 DUT Differential Near End Xtalk Test Circuit Part Marking Information PI3PCIE 3415AZHE YYWWXX PI3PCIE3415A Document Number DS40126 Rev 1-2 YY : Year WW : Workweek 1st X: Assembly Code 2nd X: Fab Code 10 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Packaging Mechanical: 42-TQFN (ZH) 17-0266 PI3PCIE3415A Document Number DS40126 Rev 1-2 11 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A Packaging Mechanical: 40-TQFN (ZL) 17-0681 For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/ Ordering Information Ordering Code Package Code Package Description PI3PCIE3415AZHEX ZH 42-contact, Very Thin Quad Flat No-Lead (TQFN), (width 24mm) PI3PCIE3415AZHE+DRX ZH 42-contact, Very Thin Quad Flat No-Lead (TQFN), (width 16mm) PI3PCIE3415AZLEX ZL 40-pin, 3x6mm (TQFN) Notes: • Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/ • E = Pb-free and Green • X suffix = Tape/Reel PI3PCIE3415A Document Number DS40126 Rev 1-2 12 www.diodes.com November 2017 Diodes Incorporated A product Line of Diodes Incorporated PI3PCIE3415A IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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