PI3VDP1430ZBE

PI3VDP1430 Dual Mode DisplayPort to HDMI Level shifter and Re-driver Features Description • Re-drives HDMI1.4a signal across long PCB trace • Converts low-swing AC coupled differential input to HDMI™ rev 1.4a compliant open-drain current steering Rx terminated differential output • HDMI level shifting operation up to 2.97Gbps per lane (297MHz pixel clock) for stereo video • Integrated 50-ohm termination resistors for AC-coupled differential inputs. • Enable/Disable feature to turn off TMDS outputs to enter lowpower state. • 3.3 Power supply required. • Integrated ESD protection to 8kV contact on all high speed I/O pins (IN_x and OUT_x) per IEC61000-4-2 test spec, level 4 • DDC level shifters from 5V from sink side down to 3.3V on source side • Level shifter for HPD signal from HDMI/DVI connector • Integrated pull-down on HPD_sink input guarantees "input low" when no display is plugged in • Packaging (Pb-Free & Green) – 48 TQFN, 7mm x 7mm (ZBE) Pericom Semiconductor’s PI3VDP1430 provides the ability to use a Dual-mode DP transmitter in HDMI™ mode. This flexibility provides the user a choice of how to connect to their favorite display. All signal paths accept AC coupled video signals. The PI3VDP1430 converts this AC coupled signal into an HDMI rev 1.4a compliant signal with proper signal swing. This conversion is automatic and transparent to the user. The PI3VDP1430 supports up to 2.97Gbps, which provides stereo video functionality as described in the HDMI 1.4a specifrication. Block Diagram OE# INx_D4+ INx_D4- Pin Configuration SCL_SINK GND VDD OE# 31 HPD_SINK 32 SDA_SINK 33 DDC_EN VDD 34 GND EQ_1 EQ_0 GND 35 30 29 28 27 26 25 24 IN_D1- 38 23 OUT_D1- IN_D1+ 39 22 OUT_D1+ VDD 40 21 VDD 41 20 OUT_D2- IN_D2+ 42 19 OUT_D2+ GND 43 18 GND IN_D3- 44 17 OUT_D3- IN_D3+ 45 16 OUT_D3+ 46 15 VDD 47 14 OUT_D4- IN_D4+ 48 13 12 OUT_D4+ All trademarks are property of their respective owners. 10 11 VDD 9 OC_3 8 SCL_SOURCE 7 HPD_SOURCE 6 SDA_SOURCE GND 5 OC_2(REXT ) OC_1 VDD OC_0 GND 4 OUT_D1+ OUT_D1- IN_D1+ IN_D1- HPD_SOURCE Rx HPD HPD_SINK DDC_EN (0V TO 3.3V) SCL_SOURCE SDA_SOURCE 14-0186 Rx 0V GND VDD IN_D4- 3 OUT_D2+ OUT_D2- IN_D2+ IN_D2- GND IN_D2- GND Rx 0V 37 2 OUT_D3+ OUT_D3- INx_D3+ INx_D3- GND 1 Rx 0V 48-Pin TQFN (ZDE/ZBE) 36 OUT_D4+ OUT_D4- 0V 1 SCL_SINK SDA_SINK 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Pin Assignment Pin Name Type OE# I IN_D4+ IN_D4– IN_D3+ IN_D3– IN_D2+ IN_D2– IN_D1+ IN_D1– OUT_D4+ OUT_D4– OUT_D3+ OUT_D3– OUT_D2+ OUT_D2– OUT_D1+ OUT_D1– I I I I I I I I O O O O O O O O (Continued) Description 5.5V tolerant low-voltage single-ended input Enable for level shifter path OE# IN_D Termination OUT_D Outputs 1 >100KΩ High-Z 0 50Ω Active Differential input Differential input Differential input Differential input Differential input Differential input Differential input Differential input TMDS Differential output TMDS Differential output TMDS Differential output TMDS Differential output TMDS Differential output TMDS Differential output TMDS Differential output TMDS Differential output All trademarks are property of their respective owners. 14-0186 2 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Pin Name HPD_SINK HPD_SOURCE SCL_SOURCE SDA_SOURCE SCL_SINK SDA_SINK DDC_EN Type Description Low Frequency, 0V to 5V (nominal) input signal. This signal comes from the HDMI connector. Voltage High 5V tolerance single-ended input indicates "plugged" state; voltage low indicated "unplugged". HPD_SINK is pulled down by an integrated 100K ohm put-down resistor. HPD_SOURCE: 0V to 3.3V (nominal) output signal. 3.3V single-ended output This is level-shifted version of the HPD_SINK signal. 3.3V DDC Data I/O. Pulled up by external terminaSingle-ended 3.3V open-drain tion to 3.3V. Connected to SCL_SINK through voltDDC I/O age-limiting integrated NMOS passgate. 3.3V DDC Data I/O. Pulled up by external termination Single-ended 3.3V open-drain to 3.3V. Connected to SDA_SINK through voltageDDC I/O limiting integrated NMOS passgate. 5V DDC Clock I/O. Pulled up by external termination Single-ended 5V open-drain to 5V. Connected to SCL_SOURCE through voltageDDC I/O limiting integrated NMOS passgate. 5V DDC Data I/O. Pulled up by external termination Single-ended 5V open-drain to 5V. Connected to SDA_SOURCE through voltageDDC I/O limiting integrated NMOS passgate. Enables bias voltage to the DDC passgate level shifter gates. (May be implemented as a bias voltage connection to the DDC pass gates themselves.) 5.0V tolerant Single-ended input DDC_EN Passgate 0V Disabled 3.3V Enabled VDD 3.3V DC Supply OC_2 (REXT) 3.3V single-ended control input OC_3 Analog connection to external component or supply OC_0 OC_1 EQ_0 EQ_1 Output and Input jitter elimination control All trademarks are property of their respective owners. 14-0186 3.3V ± 10% Acceptable connections to OC_1 (REXT) pin are: Resistor to GND; Resistor to 3.3V; NC. (Resistor should be 0-ohm). Acceptable connections to OC_3 pin are: short to 3.3V or to GND; NC. Control pins are to enable Jitter elimination features. For normal operation these pins are tied GND or to VDD. Please see the truth tables for more information. 3 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Table 1: Truth Table OC_3(1) OC_2(1) 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 OC_1(1) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Table 2: Truth Table EQ_1(1) EQ_0(1) 0 0 1 1 0 1 0 1 OC_0(1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vswing (mV) 500 600 750 1000 500 500 500 500 400 400 400 400 1000 1000 1000 1000 Pre/De-emphasis 0 0 0 0 0 1.5dB 3.5dB 6dB 0 3.5dB 6dB 9dB 0 -3.5dB -6dB -9dB Equalization @ 1.25GHz (dB) 3 6 9 12 Notes: 1) These signals have internal 100kohm pull-ups. All trademarks are property of their respective owners. 14-0186 4 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Absolute Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature.....................................–65°C to +150°C Supply Voltage to Ground Potential.............–0.5V to +5V DC Input Voltage..........................................–0.5V to VDD DC Output Current .......................................120mA Power Dissipation .........................................1.0W Thermal Characteristics Symbol Parameter TJmax Junction Temperature RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient Rating Unit 125 °C 23.65 9.1 °C/W Electrical Characteristics Table 3: Power Supplies and Temperature Range Symbol Parameter VDD Power Supply ICC ICCQ TCASE Min Nom Max Units 3.3 3.6 V 100 mA 2 mA 85 Celcius 2.89 Max Current Standby Current Consumption Case temperature range for operation with spec. All trademarks are property of their respective owners. -40 14-0186 5 Comments Total current from VDD 3.3V supply when de-emphasis/pre-emphasis is set to 0dB. OE# = HIGH 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Table 4: OE# Description OE# Asserted (low voltage) Unasserted (high voltage) Device State Differential input buffers and output buffers enabled. Input impedance = 50Ω Low-power state. Differential input buffers and termination are disabled. Differential inputs are in a high-impedance state. Comments Normal functioning state for IN_D to OUT_D level shifting function. Intended for lowest power condition when: • No display is plugged in or • The level shifted data path is disabled HPD_SINK input and HPD_SOURCE output OUT_D level-shifting outputs are disare not affected by OE# SCL_SOURCE, abled. SCL_SINK, SDA_SOURCE and SDA_SINK OUT_D level-shifting outputs are in highsignals and functions are not affected by OE# impedence state. Internal bias currents are turned off. Table 5: Differential Input Characteristics for IN_D and RX_IN signals Symbol Parameter Min Nom Max Units Comments Tbit is determined by the display mode. Nominal bit rate ranges from 250Mbps Tbit Unit Interval 360 ps to 2.5Gbps per lane. Nominal Tbit at 2.5 Gbps=400ps. 360ps=400ps-10% Differential Input Peak VRX-DIFFp-p=2'|VRX-D+ x VRX-D-| 0.175 1.2 V VRX-DIFFp-p to Peak Voltage Applies to IN_D and RX_IN signals Minimum Eye Width The level shifter may add a maximum of 0.8 Tbit TRX-EYE at IN_D input pair 0.02UI jitter VCM-AC-pp = |VRX-D+ + VRX-D-|/2 VRX-CM-DC. AC Peak VRX-CM-DC = DC(avg) of|VRX-D+ + VCM-AC-pp Common Mode Input 100 mV VRX-D-|/2 Voltage VCM-AC-pp includes all frequencies above 30 kHz. Required IN_D+ as well as IN_D- DC ZRX-DC 40 50 60 Ω impedance (50Ω ± 20% tolerance). Intended to limit power-up stress on 0 2.0 V VRX-Bias chipset's PCIE output buffers. Differential inputs must be in a high im100 ZRX-HIGH-Z kΩ pedance state when OE# is HIGH. All trademarks are property of their respective owners. 14-0186 6 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver TMDS Outputs The level shifter's TMDS outputs are required to meet HDMI 1.4a specifications. The HDMI 1.4a Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.4 specification. Table 6: Differential Output Characteristics for TMDS_OUT signals Symbol VH VL VSWING IOFF Parameter Min Nom Single-ended VDD high level out- VDD-10mV put voltage Single-ended low level out- VDD-600mV VDD-500mV put voltage Single-ended 450mV 500mV output swing voltage Single-ended current in high-Z state Max Units Comments VDD is the DC termination VDD+10mV V voltage in the HDMI or DVI Sink. VDD is nominally 3.3V VDD-400mV 600mV V V 50 µA TR Rise time 125ps 0.4Tbit ps TF Fall time 125ps 0.4Tbit ps TSKEWINTRA TSKEWINTER TJIT Intra-pair differential skew 30 ps Inter-pair laneto-lane output skew 100 ps Jitter added to TMDS signals 25 ps All trademarks are property of their respective owners. 14-0186 7 The open-drain output pulls down from VDD. Swing down from TMDS termination voltage (3.3V ± 10%) Measured with TMDS outputs pulled up to VDD Max _(3.6V) through 50Ω resistors. Max Rise/Fall time @2.7Gbps = 148ps. 125ps = 148-15% Max Rise/Fall time @2.7Gbps = 148ps. 125ps = 148-15% This differential skew budget is in addition to the skew presented between D+ and D- paired input pins. HDMI revision 1.3 source allowable intra-pair skew is 0.15Tbit. This lane-to-lane skew budget is in addition to skew between differential input pairs Jitter budget for TMDS signals as they pass through the level shifter. 25ps = 0.056 Tbit at 2.25 Gb/s 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver TMDS Output Oscillation Elimination The inputs do not incorporate a squelch circuit. Therefore, we recommend the input to be externally biased to prevent output oscillation. Pericom recommends to add a 1.5Kohm pull-up to the Clock input. VBIAS 3.3V RINT 1.5Kohm RINT DMDP Receiver TMDS Driver SS RT AVDD SS RT TMDS Input Fail-Safe Recommendation All trademarks are property of their respective owners. 14-0186 8 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Table 8: HPD Input Characteristics Symbol Parameter Min Input High Level VIH-HPD 2.0 VIL-HPD IIN-HPD VOH-HPDB VOL-HPDB THPD TRF-HPDB HPD_sink Input Low Level HPD_sink Input Leakage Current HPD_sink Output High-Level HPD_sink Output Low-Level HPD_sink to HPD_source propagation delay Nom Max Units 5.0 5.3 V 0.8 V 70 μA Measured with HPD_sink at VIH-HPD max and VIL-HPD min 2.5 VDD V VDD = 3.3V ± 10% 0 0.02 V 0 HPD_source rise/ fall time 200 ns 20 ns 1 Comments Low-speed input changes state on cable plug/unplug Time from HPD_sink changing state to HPD_source changing state. Includes HPD_source rise/fall time Time required to transition from VOHHPDB to VOL-HPDB or from VOL-HPDB to VOH-HPDB Table 9: OE# Input and DDC_EN Symbol Parameter Min VIH Input High Level VIL Input Low Level IIN Input Leakage Current Nom Max Units 2.0 VDD V 0 0.8 V 10 μA Comments TMDS enable input changes state on cable plug/unplug Measured with input at VIH-EN max and VIL-EN min Table 10: Termination Resistors Symbol RHPD Parameter Min Nom Max Units Comments HPD_sink input pulldown resistor. 80K 100k 120K Ω Guarantees HPD_sink is LOW when no display is plugged in. All trademarks are property of their respective owners. 14-0186 9 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Recommended Power Supply Decoupling Circuit Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1µF decoupling capacitors on each VDD pins of our part, there are four 0.1µF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1µF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1µF decoupling capacitors on each VDD pins, it is recommended to put a 10µF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of other circuits. 10µF Ferrite Bead From main power supply 0.1µF V DD 0.1µF V DD P e r ic o m P a r t 0.1µF V DD 0.1µF V DD Figure 1 Recommended Power Supply Decoupling Circuit Diagram All trademarks are property of their respective owners. 14-0186 10 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Requirements on the Decoupling Capacitors There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R. Layout and Decoupling CapacitorPlacement Consideration i. Each 0.1µF decoupling capacitor should be placed as close as possible to each VDD pin. ii. VDD and GND planes should be used to provide a low impedance path for power and ground. iii. Via holes should be placed to connect to VDD and GND planes directly. iv. Trace should be as wide as possible v. Trace should be as short as possible. vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. vii. 10µF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1µF capacitors. viii. Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. Bypass noise V DD P la ne Power Flow G N D P la ne 0 .1 uF P e r ic o m P a r t Figure 2 Layout and Decoupling Capacitor Placement Diagram All trademarks are property of their respective owners. 14-0186 11 10/29/14 PI3VDP1430 Dual Mode DP to HDMI Level shifter and Re-driver Package Mechanical : 48-pin TQFN UNIT: mm 1 DATE: 02/11/09 Notes: 1. All dimensions are in millimeters, angles are in degrees. 2. Coplanarity applies to the exposed thermal pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZB48 DOCUMENT CONTROL #: PD-2080 REVISION: A 09-0091 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php • The epad size is 5.1 x 5.1 mm Ordering Information Ordering Code Package Code PI3VDP1430ZBE ZBE Package Description 48-pin Pb-free & Green, TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X Suffix = Tape/Reel All trademarks are property of their respective owners. 14-0186 12 10/29/14