PI3WVR31313AZLE

A product Line of Diodes Incorporated PI3WVR31313A DP/HDMI 1:3 De-multiplexer switches Features Description ÎÎDP/HDMI 1:3 De-multiplexer switch with 4 high speed PI3WVR31313A has two passive output port1 and port2, one active (DP to HDMI) output port3. Passive output ports support DP1.2 at 5.4Gbps. Active port3 support HDMI1.4b at 3.4Gbps. All three output ports support auto port priority selection. Input port accepts DP1.2 and DP++ signals associated with output ports as described above. differential channel and AUX/DDC, HPD and CAB_DET signal channels ÎÎTwo passive output ports for DP1.2 at5.4Gbps signals ÎÎOne active output port with integrated DP to HDMI re- driver (level shifter) supports HDMI 1.4 at 3.4Gbps ÎÎPin control mode supports auto port priority selection Application ÎÎPin control mode supports port3 with DDC bi-direction buffer switch only ÎÎNotebook ÎÎI2C control mode supports auto port priority selection ÎÎI2C control mode supports port3 with 8 levels equalization and 5 levels pre-emphasis Pin Configuration: TQFN-60 ÎÎI2C control mode supports port3 with either DDC bi- AUXN AUXP SCL3 SDA3 AUX2P/SCL2 AUX2N/SDA2 CAB_2 AUX1P/SCL1 AUX1N/SDA1 CAB_1 direction buffer switch or DDC passive switch ÎÎVery low operating power when passive port1 and port2 are selected ÎÎ3.3V power supply ÎÎ2KV HBM ESD protection for all I/O pins 60 59 58 57 56 55 54 53 52 51 OEB SCL SDA VDD HPD_SRC CAB_SRC D0P D0N D1P D1N D2P D2N D3P D3N SDA_CTL/PRI_SEL SCL_CTL/EQ I2C_A1/PRE_EMP I2C_A2/ROUT_SEL HPD3 HPD2 ÎÎSupport Type2 cable ID register ÎÎPackaging: 60 pin TQFN package (5x9mm, 0.4mm pitch) Center Pad TQFN-60 5x9 mm 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VDD D0P1 D0N1 D1P1 D1N1 D2P1 D2N1 D3P1 D3N1 D0P2 D0N2 D1P2 D1N2 D2P2 D2N2 D3P2 D3N2 CEXT HPD1 MS 21 22 23 24 25 26 27 28 29 30 CLKN3 CLKP3 VDD D0N3 D0P3 D1N3 D1P3 VDD D2N3 D2P3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 All trademarks are property of their respective owners. 17-0053 1 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Block Diagram CEXT CAB_SRC HPD_SRC HPD1 120KΩ HPD2 120KΩ VDD LDO HPD3 120KΩ CAB_1 CAB_2 100KΩ pull High AUX1P/SCL1 AUX1N/SDA1 AUX2P/SCL2 AUX2N/SDA2 AUXP AUXN SDA SCL SDA3 SCL3 cable ID D[0:3]P1 D[0:3]N1 VDD 0//VDD D[0:3]P D[0:3]N D[0:3]P2 D[0:3]N2 10K pull Low RT Port select RT GND ROUT ROUT D[0:3]P3 D[0:3]N3 Rpd Rpd GND OEB MS PRI_SEL EQ PRE_EMP ROUT_SEL Control & Status Register I2C Controller SDA_CTL SCL_CTL (share pins) I2C_A1, A2 (share pins) All trademarks are property of their respective owners. 17-0053 2 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Pin Description pin# pin Name 7 D0P 9 D1P 11 D2P 13 D3P 8 D0N 10 D1N 12 D2N 14 D3N 49 D0P1 47 D1P1 45 D2P1 43 D3P1 48 D0N1 46 D1N1 44 D2N1 42 D3N1 41 D0P2 39 D1P2 37 D2P2 35 D3P2 40 D0N2 38 D1N2 36 D2N2 34 D3N2 30 D2P3 27 D1P3 25 D0P3 29 D2N3 26 D1N3 24 D0N3 22 CLKP3 21 CLKN3 All trademarks are property of their respective owners. Signal Type 17-0053 Description I 4 differential pair input (DP or DP++) O 4 differential pair output (DP) for port 1 and port 2 O 4 differential pair output (HDMI) for port 3 3 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A pin# pin Name Signal Type Description 52 AUX1N/SDA1 55 AUX2N/SDA2 53 AUX1P/SCL1 56 AUX2P/SCL2 57 SDA3 58 SCL3 60 AUXN 59 AUXP 3 SDA 2 SCL 32 HPD1 I 20 HPD2 I HPD1-3 for port1-3; 19 HPD3 I HPD_SRC to DP-source 5 HPD_SRC O 51 CAB_1 54 CAB_2 6 CAB_SRC 1 OEB I 15 SDA_CTL/PRI_SE I 16 SCL_CTL/EQ 17 I2C_A1/PRE_EMP I 18 I2C_A2/ROUT_SEL I IO AUX (DP) or DDC (HDMI) to three ports IO AUX to DP-source IO DDC to DP-source CAB_1: CAB_DET to port1 IO CAD_2: CAB_DET to port2 CAB_SRC: CAB_DET to DP-source No CAB_DET for HDMI port3 IO OEB=0, device active; OEB=1, device shut down MS=0, PRI_SEL selects priority in pin control mode; MS=1, SDA_CTL as SDA in I2C control mode MS=0, EQ selects equalization in pin control mode; MS=1, SCL_CTL as SCL in I2C control mode MS=0, PRE_EMP selects Pre-emphasis in pin control mode; MS=1, I2C_A1 as I2C address A1 in I2C control mode MS=0, ROUT_SEL selects source termination in pin control mode; MS=1, I2C_A2 as I2C address A2 in I2C control mode Mode Select: MS pin with weak pull low resistor > 500Kohm 31 MS I MS=0 or half VDD input level for pin control mode, MS=1 for I2C control mode 33 CEXT O 4, 23, 28, 50 VDD Power Center Pad GND Ground All trademarks are property of their respective owners. 17-0053 Internal LDO bypass capacitance, 4.7uf to GND 3.3V VDD Bottom GND EPAD 4 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Pin mapping for dual mode DP source DEMUX to DP output DP mode HDMI/DVI mode WVR31313A input pins WVR31313A port1 output WVR31313A port2 output WVR31313A port3 output ML_lane0(P) TX2+ D0P D0P1 D0P2 D2P3 ML_lane0(N) TX2- D0N D0N1 D0N2 D2N3 ML_lane1(P) TX1+ D1P D1P1 D1P2 D1P3 ML_lane1(N) TX1- D1N D1N1 D1N2 D1N3 ML_lane2(P) TX0+ D2P D2P1 D2P2 D0P3 ML_lane2(N) TX0- D2N D2N1 D2N2 D0N3 ML_lane3(P) TXC+ D3P D3P1 D3P2 CLKP3 ML_lane3(N) TXC- D3N D3N1 D3N2 CLKN3 Function Description The MS pin selects I2C or pin control mode. Pin control mode has only automatic port selection. I2C control mode has automatic port selection. In auto port selection, when only one HPD high detected, the port with HPD high will be selected. When multiple HPD high detected, the PRI_SEL pin(priority select) will determine the priority of the 3 ports. When PRI_SEL=low, the port-priority will be port1-port2-port3 from high to low; when PRI_SEL=high, the port priority will be port1-port3-port2 from high to low; when PRI_SEL=M (open as not connected), the port priority will be port3-port1-port2 from high to low. When port 1 (or port2) is selected and CAB_1 (or CAB_2) is low as in DP mode, the AUX/DDC channels will work as AUX channels. AUXP shall have 100Kohm external resistor to GND and AUXN shall have 100Kohm external resistor to VDD. The data rate of AUX channels will be >720Mbps.The internal DDC switch will be off. When port 1 (or port2) is selected and CAB_1 (or CAB_2) is high when DP to HDMI adapter plugged, the AUX/DDC channels will work as DDC channels. The internal DDC channels are on and the AUX channels are off. The input of DDC channels can tolerate 5V input and voltage of DDC to source will be limited about 3.3V or below. When port 1 or port 2 is selected (passive ports), port3 with HDMI re-driver will shut down. When port 3 is selected, the internal DP to HDMI level shifter will be enabled. There will be 3 EQ and 3 Pre-emphasis settings in pin control mode, 8 EQ and 5 Pre-emphasis settings in I2C control mode. When port 3 is selected, HDMI output can be standard TMDS-open-drain source, as well to be selected with internal source termination as 50 ohm pull up to 3.3V VDD, using ROUT_SEL pin control or I2C control. When port 3 is active as DP to HDMP level shifter, the DDC channel can be selected between bi-direction DDC buffer and passive DDC switch. HPD1, HPD2 and HPD3 are with internal CMOS buffers and can support 3.3V and 5V HPD inputs. Squelch Mode Squelch function will disable HDMI data output (as high impedance)when the voltage and frequency of input clock (TMDS) are below squelch threshold, which will prevent random noise presenting in HDMI data output, thereby prevent noise on sink display. Squelch function will enable-resume HDMI data output when input clock signals are above squelch threshold. All trademarks are property of their respective owners. 17-0053 5 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Truth Table for TMDS port3 EQ – three level pin control PRE-EMP – three level pin control EQ Equalization value PRE_EMP TX pre-emphasis 0 1.5dB 0 0dB open 4.0dB open 1.5dB 1 6.5dB 1 2.5dB MS – three level pin control ROUT_SEL ROUT_SEL Pull-Up Resistors on port3 D[0:3]P3, D[0:3]N3 MS Pin mode/type cable ID 0 No Pull-up resistors 0 Pin mode for Type 2 ID 1 50Ω Pull-up resistors to VDD M(0.5*vdd) Pin mode for Type 1 ID 1 I2C mode Priority Selection Table PRI_SEL (Priority order) HPD1 HPD2 HPD3 HPD_SRC CAB_SRC AUXP/AUXN SDA/SCL 0 0 0 0 0 Hi-Z Hi-Z Hi-Z 0 1 x x HPD1 CAB1=0 AUX1P/AUX1N Hi-Z CAB1=1 Hi-Z SDA1/SCL1 0 0 1 x HPD2 CAB2=0 AUX2P/AUX2N Hi-Z CAB2=1 Hi-Z SDA2/SCL2 0 0 0 1 HPD3 High Hi-Z SDA3/SCL3 M 0 0 0 0 Hi-Z Hi-Z Hi-Z M 1 x 0 HPD1 CAB1=0 AUX1P/AUX1N Hi-Z CAB1=1 Hi-Z SDA1/SCL1 M 0 1 0 HPD2 CAB2=0 AUX2P/AUX2N Hi-Z CAB2=1 Hi-Z SDA2/SCL2 M x x 1 HPD3 High Hi-Z SDA3/SCL3 1 0 0 0 0 Hi-Z Hi-Z Hi-Z 1 1 x x HPD1 CAB1=0 AUX1P/AUX1N Hi-Z CAB1=1 Hi-Z SDA1/SCL1 1 0 1 0 HPD2 CAB2=0 AUX2P/AUX2N Hi-Z CAB2=1 Hi-Z SDA2/SCL2 1 0 x 1 HPD3 High Hi-Z SDA3/SCL3 Note: M=internal half VDD when input=HiZ All trademarks are property of their respective owners. 17-0053 6 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A PRI_SEL (Priority order) HPD1 HPD2 HPD3 D0P D1P D2P D3P D0N D1N D2N D3N 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 1 x x D0P1 D1P1 D2P1 D3P1 D0N1 D1N1 D2N1 D3N1 0 0 1 x D0P2 D1P2 D2P2 D3P2 D0N2 D1N2 D2N2 D3N2 0 0 0 1 D2P3 D1P3 D0P3 CLKP3 D2N3 D1N3 D0N3 CLKN3 M 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z M 1 x 0 D0P1 D1P1 D2P1 D3P1 D0N1 D1N1 D2N1 D3N1 M 0 1 0 D0P2 D1P2 D2P2 D3P2 D0N2 D1N2 D2N2 D3N2 M x x 1 D2P3 D1P3 D0P3 CLKP3 D2N3 D1N3 D0N3 CLKN3 1 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 1 x x D0P1 D1P1 D2P1 D3P1 D0N1 D1N1 D2N1 D3N1 1 0 1 0 D0P2 D1P2 D2P2 D3P2 D0N2 D1N2 D2N2 D3N2 1 0 x 1 D2P3 D1P3 D0P3 CLKP3 D2N3 D1N3 D0N3 CLKN3 Note: M=internal half VDD when input=HiZ All trademarks are property of their respective owners. 17-0053 7 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature ........................................................... –65°C to +150°C Junction Temperature............................................................................. 125°C Supply Voltage to Ground Potential ....................................–0.5V to +4.6V High Speed Channel Input Voltage (DP Mode)........................–0.5V to 2V DDC and HPD channels Input Voltage ....................................–0.5V to 6V DC Output Current ..............................................................................180mA Power Dissipation .................................................................................... 0.6W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Electrical Characteristics Recommended Operation Conditions VDD = 3.3V ±10%, Min and Max apply for TA between -40oC to 85oC Typical values are referenced to TA = 25oC Parameter Description VDD Operating Voltage Test Conditions VDD supply current (Port1 or 2 active) IDD VDD Supply Current (Port3 active) IDDQ VDD Quiescent Supply Current (port3 active w/o TMDS input) Min. Typ. Max. Unit 3.0 3.3 3.6 V VDD=3.3V 1 1.8 mA Output Enable ( open drain 500mv signal-end 0dB pre-emphasis, not including 40mA current to source) 80 100 mA Output Enable ( double termination, 500mv signal-end 0dB pre-emphasis, not including 40mA current to source) 160 200 mA TMDS Output Disable 3.5 5 mA Isd1 Supply shut down current when OEB disable (MS=0) VDD=3.6V, OEB=high 0.1 0.2 mA Isd2 Supply shut down current when OEB disable (MS=1) VDD=3.6V, OEB=high 0.6 1.2 mA All trademarks are property of their respective owners. 17-0053 8 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A DC Electrical Characteristics for Switching over Operating Range Parameter Description Test Conditions Min. Typ. Max. Unit OEB, MS, ROUT_SEL IIH High level digital input current VIH =VDD -10 40 μA IIL Low level digital input current VIL = GND -10 10 μA VIH High level digital input voltage 2.0 VIL Low level digital input voltage 0 V 0.8 V 0.4 V HPD_SRC VOL_HPD_SRC Buffer Output Low Voltage IOL = 4 mA VOH_HPD_SRC Buffer Output Low Voltage IOH = 4 mA 2.4 IIH High level digital input current VIH =VDD -10 40 μA IIL Low level digital input current VIL = GND -10 10 μA VIH High level digital input voltage VDD=3.3V 2.0 VIL Low level digital input voltage V HPD_sink V 0 0.8 V -50 50 uA CAB ILK Input leakage current Switch is off, Vin=5.5V CIO Input/Output capacitance whenpassive switch on RON Passive Switch resistance IO = 3mA, VO = 0.4V Vpass Switch Output voltage VI=3.3V, II=100uA CI(source) Source side CAB capacitance CI(sink) Sink side CAB capacitance when 10 1.5 VI peak-peak = 1V, 100 KHz pF 25 50 Ω 3.0 3.3 V 3.5 pF 6.5 pF SDA/SCL, SDA1/SCL1, SDA2/SCL2 ILK Input leakage current DDC switch is off, Vin=5.5V CIO Input/Output capacitance when passive switch on VI peak-peak = 1V, 100 KHz 8 RON Passive Switch resistance IO = 3mA, VO = 0.4V 25 50 Ω Vpass Switch Output voltage 2.0 2.5 V CI(source) Source side DDC capacitance ( passive switch off. ) CI(sink) Sink side DDC capacitance ( pasVI peak-peak = 1V, 100 KHz sive switch off. ) VI=5.0V, II=100uA VDD=3.3V -50 1.5 VI peak-peak = 1V, 100 KHz 50 uA pF 2.5 pF 5 pF SDA3/SCL3 ( DDC buffer of port3 active) VIH High level input voltage VIL Low level input voltage ILK Input leakage current All trademarks are property of their respective owners. VDD=3.3V DDC switch is off, Vin = 5.5V 17-0053 9 2.0 V 0 0.8 V -10 10 uA www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Parameter Description Test Conditions IIL Low level input current VIL = 0.2V VOL Low level output voltage ILOH CIO Min. Typ. Max. Unit 10 μA IOL = 4mA 0.2 V HIGH-level output leakage current VO=3.6V 10 μA Input/output capacitance VI = 3 V or 0 V; VCC = 3.3 V or 0V -10 4 pF SDA/SCL (DDC buffer of port3 active) VIH High level input voltage VIL Low level input voltage ILK Input leakage current IIL VDD=3.3V 2.0 V 0 0.4 V DDC switch is off, Vin = 5.5V -10 10 uA Low level input current VIL = 0.2V -10 10 μA VOL Low level output voltage IOL = 4mA 0.47 0.6 V ILOH HIGH-level output leakage current VO=3.6V 10 μA CIO Input/output capacitance VI = 3 V or 0 V; VCC = 3.3 V or 0V 0.52 5 8 pF AUXP, AUXN, AUXnP/SCLn, AUXnN/SDAn ILK Input leakage current DDC switch is off, Vin=5.5V CIO Input/Output capacitance when passive switch on VI peak-peak = 1V, 100 KHz 6 pF RON Passive Switch resistance IO = 3mA, VO = 0.3V 5 Ω IO = 3mA, VO = 3.0V 10 Ω Vpass Switch Output voltage CI(source) Source side capacitance ( passive switch off. ) VI peak-peak = 1V, 100 KHz 2.5 pF CI(sink) Sink side capacitance ( passive switch off. ) VI peak-peak = 1V, 100 KHz 3.5 pF VI=5.5V, II=100uA VDD=3.3V -50 50 4 4.5 uA V High Speed Channel (D[0:3]P/N – D[0:3]P1N1, D[0:3]P/N – D[0:3]P2N2) VIK Clamp Diode Voltage (HS Channel) VDD = Max., IIN = –18mA IIH Input HIGH Current VDD = Max., VIN = VDD ±10 IIL Input LOW Current VDD = Max., VIN = GND ±10 RON_HS On resistance between input to out- put for high speed signals All trademarks are property of their respective owners. 17-0053 VINPUT,cm = 0V to 1.2V, VINPUT,diff < 1.0Vp-p, diff, –1.6 8 –1.8 V µA Ohm VDD = 3.0V, IINPUT = 20mA 10 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Parameter Description Test Conditions Min. Typ. Max. Unit VDD+10 mV 50 66 ohm 30 100 uA 100 uA Max. Unit High Speed Channel Port3 (D[0:2]P3/N3, CLKP3/N3) VI(open) Single-ended input voltage under high impedance input or open input IL=10uA VDD-10 RT Input termination resistance VIN=2.9V 45 IOZ Leakage current resistance VDD=3.6V, OEB=High Ioff Power off leakage current VDD=0, VIN=3.6V -100 Dynamic Electrical Characteristics over Operating Range (TA = -40º to +85ºC, VDD = 3.3V ±10%) Parameter Description Test Conditions Min. Typ. TMDS Differential Pins tpd tr tf Propagation delay 2000 Differential output signal rise time 120 (20% - 80%) Differential output signal fall time (20% - 80%) VDD = 3.3V, Rout = 50Ω off, open drain, 0dB pre-emphasis 120 tsk(p) Pulse skew 15 50 tsk(D) Intra-pair differential skew 25 50 tsk(o) Inter-pair differential skew(2) Tjit_clk(pp) Peak-to-peak output jitter CLK residual jitter Tjit_dat(pp) Peak-to-peak output jitter DATA Residual Jitter ten Enable time tdis Disable time ps 100 Data Input = 3.4 Gbps HDMI data pattern from signal generation, short trace. CLK Input = 340 MHz clock 15 40 25 50 when channel is active 10 50 us SCL, SDA channel, AUX channel , CAB channel : passive switches tpd(DDC) Propagation delay from SCLn/ SDAn to SCL/SDA or SCL/SDA to SCLn/SDAn In passive SW on. CL = 10pF, in passive switch 5 ns SCL3, SDA3- SCL,SDA channel : buffers tPLH LOW-to-HIGH propagation delay SCL/SDA to SCL3/SDA3 50 100 150 ns tPHL HIGH-to-LOW propagation delay SCL/SDA to SCL3/SDA3 10 20 40 ns tPLH LOW-to-HIGH propagation delay SCL3/SDA3 to SCL/SDA 50 100 150 ns tPHL HIGH-to-LOW propagation delay SCL3/SDA3 to SCL/SDA 10 20 40 ns All trademarks are property of their respective owners. 17-0053 11 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Parameter Description Test Conditions Min. Typ. Max. Unit 2 4 us 2 4 us Typ. Max. Unit Control and Status Pins (HPDn, HPD_SRC) tpd(HPD) Propagation delay (from HPDx to the active port of HPD_SRC, high to low) tsx(HPD) Switch time (from port select to the latest HPD , manual selection mode) CL = 10pF Dynamic Electrical Characteristics Parameter Description Test Conditions Min. High Speed Channel (D[0:3]P/N – D[0:3]P1N1, D[0:3]P/N - D[0:3]P2N2) XTALK See Fig. 1 for Crosstalk on High Speed Channels Measurement Setup f= 2.7 GHz -32 -30 OIRR OFF Isolation on High Speed Channels See Fig. 2 for Measurement Setup f= 2.7 GHz -19 -17 ILOSS Differential Insertion Loss on High Speed Channels @2.7GHZ (see figure 3) -1.7 -1.5 dB dB R loss Differential Return Loss on High Speed Channels @ 2.7GHz (5.4Gbps) BW_Dx± Bandwidth -3dB for Main high speed path (Dx±) See figure 3 5.1 5.6 GHz BW_AUX Bandwidth -3dB for AUX See figure 3 1.2 1.5 GHz Tstartup VDD valid to channel enable 250 us Twakeup Enabling output by changing OEB from High to Low 250 us Tpd Propagation delay (input pin to output pin) on all channels 80 ps tb-b Bit-to-bit skew within the same differential pair of Dx± channels 5 tch-ch Channel-to-channel skew of Dx± channels All trademarks are property of their respective owners. 17-0053 12 -18 -16 dB 7 ps 35 ps www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A BALANCED PORT1 BALANCED PORT2 BALANCED PORT1 + + 50 – – 50 + + 50 – – 50 + + 50 + – – 50 – BALANCED PORT1 BALANCED PORT2 DUT DUT Fig 1. Crosstalk Setup Fig 2. Off-isolation setup + + – – BALANCED PORT2 DUT Fig 3. Differential Insertion Loss All trademarks are property of their respective owners. 17-0053 13 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Differential Insertion Loss , Vdd=3.3V, 25C D0 to D01 Channel D0 to D02 Channel All trademarks are property of their respective owners. 17-0053 14 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Differential Return Loss , Vdd=3.3V, 25C D0 to D01 Channel D0 to D02 Channel All trademarks are property of their respective owners. 17-0053 15 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A Differential Off Isolation , Vdd=3.3V, 25C All trademarks are property of their respective owners. 17-0053 16 www.diodes.com 03/28/17 A product Line of Diodes Incorporated PI3WVR31313A HPD auto selection timing waveform t1 is the IRQ-HPD (sink) from selected-active port HPD from selected-active port Selected port is active HPD_SRC t1 (