PI4MSD5V9542A
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2 Channel I2Cbus Multiplexer with interrupt logic
Features
Description
1-of-2 bidirectional translating multiplexer
I2C-bus interface logic
Operating power supply voltage :1.65 V to 5.5 V
Allows voltage level translation between 1.2V,
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Channel selection via I2C bus
Power-up with all multiplexer channels deselected
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
JESD78 which exceeds 100 mA
Packages offered: SOIC-14W,TSSOP-14L
The PI4MSD5V9542A is a 1-of-2 bidirectional
translating multiplexer, controlled via the I2C bus. The
SCL/SDA upstream pair fans out to two SCx/SDx
downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time,
determined by the contents of the programmable control
register. Two interrupt inputs, INT0 and INT1, one for
each of the SCx/SDx downstream pairs, are provided.
One interrupt output, INT, which acts as an AND of the
two interrupt inputs, is provided.
A power-on reset function puts the registers in their
default state and initializes the I2C bus state machine
with no channels selected.
The pass gates of the multiplexer are constructed
such that the VCC pin can be used to limit the maximum
high voltage which will be passed by the
PI4MSD5V9542A. This allows the use of different bus
voltages on each SCx/SDx pair, so that1.2V, 1.8 V, 2.5
V, or 3.3 V parts can communicate with 5 V parts
without any additional protection. External pull-up
resistors pull the bus up to the desired voltage level for
each channel. All I/O pins are 5 V tolerant.
Pin Description
Pin Configuration
TSSOP
SOIC
2015-07-0033
Pin
No
Pin
Name
Type
Description
1
A0
Input
address input 0
2
A1
Input
address input 1
3
A2
Input
address input 2
4
INT0
Input
active LOW interrupt input 0
5
SD0
I/O
serial data 0
6
SC0
I/O
serial clock 0
7
GND
Ground
supply ground
8
INT1
Input
active LOW interrupt input 1
9
SD1
I/O
serial data 1
10
SC1
I/O
serial clock 1
11
INT
Output
active LOW interrupt output
12
SCL
I/O
serial clock line
13
SDA
I/O
serial data line
14
VCC
Power
supply voltage
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PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
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Block Diagram
Figure 1: Block Diagram
Maximum Ratings
Storage Temperature .................................................–55°C to +125°C
Supply Voltage port B .................................................–0.5V to +6.0V
Supply Voltage port A ................................................–0.5V to +6.0V
DC Input Voltage ....................................................... –0.5V to +6.0V
Control Input Voltage (EN)… .................................. –0.5V to +6.0V
Total power dissipation (1).......................................................100mW
Input current(EN,VCCA,VCCB,GND).....................................50mA
ESD: HBM Mode .....................................................................8000V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended operation conditions
Symbol
Parameter
Min
Typ
Max
Unit
VCC
VCCA Positive DC Supply Voltage
1.65
-
5.5
V
VEN
Enable Control Pin Voltage
GND
-
5.5
V
I/O Pin Voltage
GND
-
5.5
V
VIO
Δt /ΔV
Input transition rise or fall time
-
-
10
ns/V
TA
Operating Temperature Range
−40
-
+85
°C
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PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
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DC Electrical Characteristics
Unless otherwise specified, -40°C≤TA≤85°C, 1.1V≤Vcc≤3.6V
Symbol
Parameter
Conditions
VCC
Min
Typ
Max
Unit
5.5
V
Supply
VCC
ICC
Istb
VPOR[1]
Supply Voltage
supply current
standby current
power-on reset voltage
1.65
operating mode;
no load;
VI = VCC or GND;
fSCL = 100 kHz
3.6V to 5.5V
65
100
uA
2.3V to 3.6V
20
50
uA
1.65V to 2.3V
10
30
uA
standby mode; VCC =
3.6 V;
no load; VI = VCC or
GND;
fSCL = 0 kHz
no load; VI = VCC or
GND
3.6V to 5.5V
0.3
1
uA
2.3V to 3.6V
0.1
1
uA
1.65V to 2.3V
0.1
1
uA
3.6V to 5.5V
1.3
1.5
V
Input SCL; input/output SDA
VIL
LOW-level input voltage
1.65V to 5.5V
-0.5
+0.3VCC
V
VIH
HIGH-level input voltage
1.65V to 2V
0.75VCC
6
V
2V to 5.5V
0.7VCC
6
V
IOL
LOW-level output current
VOL = 0.4 V
1.65V to 5.5V
3
-
mA
VOL = 0.6 V
1.65V to 5.5V
6
-
mA
IIL
LOW-level input current
VI = GND
1.65V to 5.5V
-1
+1
uA
IIH
HIGH-level input current
VI = VCC
1.65V to 5.5V
-1
+1
uA
Ci
input capacitance
VI = GND
1.65V to 5.5V
-
9
10
pF
VO = 0.4 V;
IO = 15 mA
4.5 V to 5.5 V
4
9
24
Ω
3V to 3.6V
5
11
31
Ω
VO = 0.4 V;
IO = 10mA
2.3V to 2.7V
7
16
55
Ω
1.65V to 2V
9
20
70
Ω
Pass Gate
Ron
ON-state resistance
5V
4.5 V to 5.5 V
3.6
2.8
3.3V
Vpass
switch output voltage
3V to 3.6V
Vin =VCC;
Iout = -100uA
1.6
2.8
1.1
V
V
2
0.9
0.54
V
V
1.5
1.8V
1.65V to 2V
4.5
2.2
2.5V
2.3V to 2.7V
V
V
V
1.3
V
To be continued
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PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
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Continued
Symbol
Parameter
Conditions
VCC
Min
IL
leakage current
VI = VCC or GND
1.65V to 5.5V
-1
Cio
input/output capacitance
VI = VCC or GND
1.65V to 5.5V
Typ
3
Max
Unit
+1
pF
5
pF
Select inputs A0, A1, A2, INT0, INT1
VIL
LOW-level input voltage
1.65V to 5.5V
-0.5
+0.3VCC
V
VIH
HIGH-level input voltage
1.65V to 5.5V
0.7VCC
6
V
ILI
input leakage current
1.65V to 5.5V
-1
+1
uA
Ci
input capacitance
5
pF
VI = GND
VI = GND
1.65V to 5.5V
VOL = 0.4 V
1.65V to 5.5V
3
INT output
IOL
LOW-level output current
IOH
HIGH-level output current
3
mA
1.65V to 5.5V
+10
uA
Max
Unit
1.65V to 5.5V
0.3
ns
1.65V to 5.5V
4
us
1.65V to 5.5V
2
Note: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
AC Electrical characteristics
Tamb = - 40 ºC to +85 ºC; unless otherwise specified.
Symbol
Parameter
tPD[1]
propagation delay
Conditions
from SDA to SDx,
or SCL to SCx
VCC
Min
Typ
INT[2]
tV_INT
tD_INT
tREJ_L
valid time from INTn to
INT signal
delay time from INTn to
INT inactive
LOW-level rejection time
1.65V to 5.5V
us
1
us
tREJ_H
HIGH-level rejection time
1.65V to 5.5V
0.5
Note
[1]Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15 pF load capacitance.
[2] Measurements taken with 1 kΩpull-up resistor and 50 pF load.
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PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
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I2C Interface Timing Requirements
STANDARD MODE
I2C BUS
MIN
MAX
FAST MODE
I2C BUS
MIN
MAX
Symbol
Parameter
fscl
I2C clock frequency
0
tLow
I2C clock high time
4.7
1.3
μs
tHigh
I2C clock low time
4
0.6
μs
tSP
I2C spike time
tSU:DAT
I2C serial-data setup time
100
0
50
400
50
UNIT
kHz
ns
250
100
ns
[1]
0 [1]
μs
tHD:DAT
I2C serial-data hold time
tr
I2C input rise time
1000
300
ns
tf
I2C input fall time
300
300
ns
tBUF
I2C bus free time between stop and start
4.7
1.3
μs
tSU:STA
I2C start or repeated start condition setup
4.7
0.6
μs
tHD:STA
I2C start or repeated start condition hold
4
0.6
μs
tSU:STO
I2C stop condition setup
4
0.6
μs
tVD:DAT
tVD:ACK
Cb
0
[2]
Valid-data time (high to low)
SCL low to SDA output low valid
Valid-data time (low to high) [2]
SCL low to SDA output high valid
Valid-data time of ACK condition
ACK signal from SCL low to SDA output low
I2C bus capacitive load
1
1
μs
0.6
0.6
μs
1
400
1
400
μs
pF
Notes:
[1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL
signal), in order to bridge the undefined region of the falling edge of SCL.
[2] Data taken using a 1-kΩ pullup resistor and 50-pF load Notes
Figure 2. Definition of timing on the I2C-bus
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2 Channel I2C bus Multiplexer
with Interrupt Logic
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Application
I2C bus master
Figure 3. Typical Application
VCC
VPU1
VPU2
1.8V
1.5V-5.5V
1.2V-5.5V
2.5V
1.8V-5.5V
1.8V-5.5V
3.3V
2.7V-5.5V
2.7V-5.5V
5V
4.5V-5.5V
4.5V-5.5V
Note:
If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required.
If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required.
The interrupt inputs should not be left floating.
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PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
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Device addressing
Following a START condition the bus master must output the address of the slave it is accessing. The address of
the PI4MSD5V9542A is shown in Figure 4.
To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while
a logic 0 selects a write operation.
Figure 4:Device address
Control register
Following the successful acknowledgement of the slave address, the bus master will send a byte to the
PI4MSD5V9542A which will be stored in the control register. If multiple bytes are received by the PI4MSD5V9542A,
it will save the last byte received. This register can be written and read via the I2C-bus.
Figure 5: Control register
Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written
after the PI4MSD5V9542A has been addressed. The 3 LSBs of the control byte are used to determine which channel is
to be selected. When a channel is selected, it will become active after a STOP condition has been placed on the I2Cbus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false
conditions are generated at the time of connection.
Bits INT0/, INT1/, D6 and D7 are all writable, but will read the chip status. INT0/ and INT1/ indicate the state of
the corresponding interrupt input. D7 and D6 always read 0.
D7
D6
INT1
INT0
D3
B2
B1
B0
Command
X
X
X
X
X
0
X
X
no channel selected
X
X
X
X
X
1
0
0
channel 0 enabled
X
X
X
X
X
1
0
1
channel 1 enabled
X
X
X
X
X
1
1
X
no channel selected
0
0
0
0
0
0
0
0
no channel selected;
power-up default state
Control register: Write—channel selection; Read—channel status.
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2 Channel I2C bus Multiplexer
with Interrupt Logic
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Interrupt handling
The PI4MSD5V9542A provides 2 interrupt inputs, one for each channel and one open-drain interrupt output.
When an interrupt is generated by any device, it will be detected by the PI4MSD5V9542A and the interrupt output
will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control byte.
Bits 5:4 of the control byte correspond to channel 1, channel 0 of the PI4MSD5V9542A, respectively. Therefore, if
an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the
control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause
bit 4 of the control register to be set on the read. The master can then address the PI4MSD5V9542A and read the
contents of the control byte to determine which channel contains the device generating the interrupt. The master can
then reconfigure the PI4MSD5V9542A to select this channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general
purpose inputs if the interrupt function is not required.If unused, interrupt input(s) must be connected to VCC through
a pull-up resistor.
D7
D6
INT1
0
0
X
INT0
0
D3
B2
B1
B0
X
X
X
X
1
0
no interrupt on channel 0
interrupt on channel 0
0
0
Command
no interrupt on channel 1
X
X
X
X
1
X
interrupt on channel 1
Control register read — interrupt
Power-on reset
When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4MSD5V9542A in a reset
condition until VCC has reached VPOR. At this point, the reset condition is released and the PI4MSD5V9542A
registers and I2C-bus state machine are initialized to their default states (all zeroes), causing all the channels to be
deselected. Thereafter, VCC must be lowered below 0.2 V for at least 5 us in order to reset the device.
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2 Channel I2C bus Multiplexer
with Interrupt Logic
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Voltage translation
The pass gate transistors of the PI4MSD5V9542A are constructed such that the VCC voltage can be used to limit
the maximum voltage that is passed from one I2C-bus to another.
Figure 6:Vpass voltage VS Vcc
Figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the
data specified in Section “DC Electrical characteristics” of this data sheet).
In order for the PI4MSD5V9542A to act as a voltage translator, the Vpass voltage should be equal to, or lower
than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V
and 2.7 V, then Vpass should be equal to or below 2.7 V to clamp the downstream bus voltages effectively.
Looking at Figure 6, we see that Vpass (max) is at 2.7 V when the PI4MSD5V9542A supply voltage is 3.5 V or
lower so the PI4MSD5V9542A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the
bus voltages to their appropriate levels
I2C BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this time are interpreted as control signals
Figure 7: Bit Transfer
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2 Channel I2C bus Multiplexer
with Interrupt Logic
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Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line
while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the STOP condition (P)
Figure 8. Definition of Start and Stop Conditions
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’
Figure 9. System Configuration
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is
not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the
bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master
must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into
account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master
to generate a STOP condition.
Figure 10. Acknowledgment on I2C Bus
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2 Channel I2C bus Multiplexer
with Interrupt Logic
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Data is transmitted to the PI4MSD5V9542A control register using the write mode shown in bellow
Figure 11. Write Control Register
Data is transmitted to the PI4MSD5V9542A control register using the write mode shown in bellow
Figure 12. Read Control Register
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PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
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Mechanical Information
SOIC-14(W)
2015-07-0033
PT0523-4
12
8/18/15
PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mechanical Information
TSSOP-14(L)
Ordering Information
Part No.
Package Code
Package
PI4MSD5V9542AWE
W
14-Pin,150 mil Wide SOIC
PI4MSD5V9542AWEX
W
14-Pin,150 mil Wide SOIC, Tape & Reel
PI4MSD5V9542ALE
L
14-Pin,173 mil Wide TSSOP
PI4MSD5V9542ALEX
L
14-Pin,173 mil Wide TSSOP, Tape & Reel
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2015-07-0033
PT0523-4
13
8/18/15
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