PI4MSD5V9545B/45C
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4 Channel I2C bus Switch with Interrupt Logic and Reset
Features
Description
1-of-4 bidirectional translating multiplexer
I2C-bus interface logic;
Operating power supply voltage :1.65 V to 5.5 V
Allows voltage level translation between 1.2V,
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Channel selection via I2C bus
Power-up with all multiplexer channels deselected
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
JESD78 which exceeds 100 mA
Packages offered: TSSOP-20L
The PI4MSD5V9545B is a quad 1-of-4 bidirectional
translating switch, controlled via the I2C bus. The
SCL/SDA upstream pair fans out to four SCx/SDx
downstream pairs, or channels.
Any individual SCx/SDx channel or combination of
channels can be selected, determined by the contents of
the programmable control register. Four interrupt inputs,
INT0 to INT3, one for each of the downstream pairs, are
provided. One interrupt output, INT, acts as an AND of
the four interrupt inputs.
An active LOW reset input allows the PI4MSD5V9545B to recover from a situation where one of the
downstream buses is stuck in a LOW state. Pulling the
RESET pin LOW resets the I2C bus state machine and
causes all the channels to be deselected as does the
internal power-on reset function.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum high
voltage which will be passed by the PI4MSD5V9545B.
This allows the use of different bus voltages on each pair,
so that 1.2V,1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional
protection. External pull-up resistors pull the bus up to
the desired voltage level for each channel. All I/O pins
are 5 V tolerant.
The PI4MSD5V9545B and PI4MSD5V9545C are
identical except for the fixed portion of the slave address.
Pin Configuration
TSSOP20
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Pin Description
Pin No
Pin Name
Type
Description
1
A0
Input
address input 0
2
A1
Input
address input 1
3
RESET
Input
active LOW reset pin
4
INT0
Input
active LOW interrupt input 0
5
SD0
I/O
serial data 0
6
SC0
I/O
serial clock 0
7
INT1
Input
active LOW interrupt input 1
8
SD1
I/O
serial data 1
9
SC1
I/O
serial clock 1
10
GND
Ground
supply ground
11
INT2
Input
active LOW interrupt input 2
12
SD2
I/O
serial data 2
13
SC2
I/O
serial clock 2
14
INT3
Input
active LOW interrupt input 3
15
SD3
I/O
serial data 3
16
SC3
I/O
serial clock 3
Output
active LOW interrupt output
17
INT
18
SCL
I/O
serial clock line
19
SDA
I/O
serial data line
20
VCC
Power
Supply Power
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Block Diagram
Figure 1: Block Diagram
Maximum Ratings
Storage Temperature .................................................–55°C to +125°C
Supply Voltage port B .................................................–0.5V to +6.0V
Supply Voltage port A ................................................–0.5V to +6.0V
DC Input Voltage ....................................................... –0.5V to +6.0V
Control Input Voltage (EN)… .................................. –0.5V to +6.0V
Total power dissipation (1).......................................................100mW
Input current(EN,VCCA,VCCB,GND).....................................50mA
ESD: HBM Mode .....................................................................8000V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended operation conditions
Symbol
Parameter
Min
Typ
Max
Unit
VCC
VCCA Positive DC Supply Voltage
1.65
-
5.5
V
VEN
Enable Control Pin Voltage
GND
-
5.5
V
VIO
I/O Pin Voltage
GND
-
5.5
V
Δt /ΔV
Input transition rise or fall time
-
-
10
ns/V
TA
Operating Temperature Range
−40
-
+85
°C
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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DC Electrical Characteristics
Unless otherwise specified, -40°C≤TA≤85°C, 1.1V≤Vcc≤3.6V
Symbol
Parameter
Conditions
VCC
Min
Typ
Max
Unit
5.5
V
Supply
VCC
ICC
Istb
VPOR[1]
Supply Voltage
supply current
standby current
power-on reset voltage
1.65
operating mode;
no load;
VI = VCC or GND;
fSCL = 100 kHz
3.6V to 5.5V
65
100
uA
2.3V to 3.6V
20
50
uA
1.65V to 2.3V
10
30
uA
standby mode; VCC =
3.6 V;
no load; VI = VCC or
GND;
fSCL = 0 kHz
no load; VI = VCC or
GND
3.6V to 5.5V
0.3
1
uA
2.3V to 3.6V
0.1
1
uA
1.65V to 2.3V
0.1
1
uA
3.6V to 5.5V
1.3
1.5
V
Input SCL; input/output SDA
VIL
LOW-level input voltage
1.65V to 5.5V
-0.5
+0.3Vcc
V
VIH
HIGH-level input voltage
1.65V to 2V
0.75Vcc
6
V
2V to 5.5V
0.7Vcc
6
V
IOL
LOW-level output current
VOL = 0.4 V
1.65V to 5.5V
3
-
mA
VOL = 0.6 V
1.65V to 5.5V
6
-
mA
IIL
LOW-level input current
VI = GND
1.65V to 5.5V
-1
+1
uA
IIH
HIGH-level input current
VI = VCC
1.65V to 5.5V
-1
+1
uA
Ci
input capacitance
VI = GND
3.6V to 5.5V
-
12
13
pF
VO = 0.4 V;
IO = 15 mA
4.5 V to 5.5 V
4
9
24
Ω
3V to 3.6V
5
11
31
Ω
VO = 0.4 V;
IO = 10mA
2.3V to 2.7V
7
16
55
Ω
1.65V to 2V
9
20
70
Ω
Pass Gate
Ron
ON-state resistance
5V
4.5 V to 5.5 V
3.6
2.8
3.3V
Vpass
switch output voltage
3V to 3.6V
Vin =VCC;
Iout = -100uA
4.5
2.2
1.6
2.5V
2.3V to 2.7V
V
V
2.8
1.5
1.1
1.8V
V
V
V
2
0.9
V
V
1.65V to 2V
0.54
1.3
V
-1
+1
uA
5
pF
PT0536-3
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IL
leakage current
VI = VCC or GND
1.65V to 5.5V
Cio
input/output capacitance
VI = VCC or GND
1.65V to 5.5V
3
To be continued
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Continued
Symbol
Parameter
Conditions
VCC
Min
Typ
Max
Unit
Select inputs A0, A1,INT0, INT1,INT2,INT3
VIL
LOW-level input voltage
1.65V to 5.5V
-0.5
+0.3Vcc
V
VIH
HIGH-level input voltage
1.65V to 5.5V
0.7Vcc
6
V
IIL
LOW-level input current
1.65V to 5.5V
-1
+1
uA
Ci
input capacitance
5
pF
VI = GND
VI = GND
1.65V to 5.5V
VOL = 0.4 V
1.65V to 5.5V
3
INT output
IOL
LOW-level output current
IOH
HIGH-level output current
3
mA
1.65V to 5.5V
+10
uA
Max
Unit
1.65V to 5.5V
0.3
ns
1.65V to 5.5V
4
us
1.65V to 5.5V
2
Note: VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
AC Electrical characteristics
Tamb = - 40 ºC to +85 ºC; unless otherwise specified.
Symbol
Parameter
tPD[1]
propagation delay
Conditions
from SDA to SDx,
or SCL to SCx
VCC
Min
Typ
INT[2]
tREJ_L
valid time from INTn to
INT signal
delay time from INTn to
INT inactive
LOW-level rejection time
tREJ_H
HIGH-level rejection time
tV_INT
tD_INT
us
1.65V to 5.5V
1
us
1.65V to 5.5V
0.5
us
4
ns
500
ns
RESET
tw(rst)L
LOW-level reset time
trst
reset time
recovery time to START
condition
tREC;STA
SDA clear
ns
0
Note
[1]Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15 pF load capacitance.
[2] Measurements taken with 1 kΩpull-up resistor and 50 pF load.
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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I2C Interface Timing Requirements
STANDARD MODE
I2C BUS
MIN
MAX
FAST MODE
I2C BUS
MIN
MAX
Symbol
Parameter
fscl
I2C clock frequency
0
tLow
I2C clock high time
4.7
1.3
μs
tHigh
I2C clock low time
4
0.6
μs
tSP
I2C spike time
tSU:DAT
I2C serial-data setup time
100
0
50
400
50
UNIT
kHz
ns
250
100
ns
[1]
0 [1]
μs
tHD:DAT
I2C serial-data hold time
tr
I2C input rise time
1000
300
ns
tf
I2C input fall time
300
300
ns
tBUF
I2C bus free time between stop and start
4.7
1.3
μs
tSU:STA
I2C start or repeated start condition setup
4.7
0.6
μs
tHD:STA
I2C start or repeated start condition hold
4
0.6
μs
tSU:STO
I2C stop condition setup
4
0.6
μs
tVD:DAT
tVD:ACK
Cb
0
[2]
Valid-data time (high to low)
SCL low to SDA output low valid
Valid-data time (low to high) [2]
SCL low to SDA output high valid
Valid-data time of ACK condition
ACK signal from SCL low to SDA output low
I2C bus capacitive load
1
1
μs
0.6
0.6
μs
1
400
1
400
μs
pF
Notes:
[1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL
signal), in order to bridge the undefined region of the falling edge of SCL.
[2] Data taken using a 1-kΩ pullup resistor and 50-pF load Notes
Figure 2. Definition of timing on the I2C-bus
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Application
I2C bus master
Figure 3. Typical Application
VCC
VPU1
VPU2
1.8V
1.5V-5.5V
1.2V-5.5V
2.5V
1.8V-5.5V
1.8V-5.5V
3.3V
2.7V-5.5V
2.7V-5.5V
5V
4.5V-5.5V
4.5V-5.5V
Note:
If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required.
If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required.
The interrupt inputs should not be left floating.
Device addressing
Following a START condition, the bus master must output the address of the slave it is accessing. The address of
the PI4MSD5V9545B/45C is shown in Figure 4. To conserve power, no internal pull-up resistors are incorporated on
the hardware selectable address pins and they must be pulled HIGH or LOW.
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Figure 4:Device address
The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while
a logic 0 selects a write operation.
The PI4MSD5V9545B and PI4MSD5V9545C re alternate address versions if needed for larger systems or to
resolve conflicts. The data sheet will reference the PI4MSD5V9545B, but the PI4MSD5V9545C function identically
except for the slave address.
Control register
Following the successful acknowledgement of the slave address, the bus master will send a byte to the
PI4MSD5V9545B/45C, which will be stored in the control register. If multiple bytes are received by the
PI4MSD5V9545B/45C, it will save the last byte received. This register can be written and read via the I2C-bus.
Figure 5: Control register
Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This
register is written after the PI4MSD5V9545B/45C has been addressed. The 4 LSBs of the control byte are used to
determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP
condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the
channel is made active, so that no false conditions are generated at the time of connection.
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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INT3
INT2
INT1
INT0
B3
B2
B1
B0
Command
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
X
0
1
X
channel 0 disabled
channel 0 enabled
channel 1 disabled
channel 1 enabled
channel 2 disabled
channel 2 enabled
X
X
X
X
X
X
X
0
0
0
0
0
1
0
0
0
0
X
channel 3 disabled
channel 3 enabled
no channel selected;
power-up/reset default state
Control register: Write—channel selection; Read—channel status.
Interrupt handling
The PI4MSD5V9545B/45C provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output.
When an interrupt is generated by any device, it will be detected by the PI4MSD5V9545B/45C and the interrupt
output will be driven LOW. The channel does not need to be active for detection of the interrupt. A bit is also set in
the control register.
Bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of the
PI4MSD5V9545B/45C, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the
state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on
any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then
address the PI4MSD5V9545B/45C and read the contents of the control register to determine which channel contains
the device generating the interrupt. The master can then reconfigure the PI4MSD5V9545B/45C to select this channel,
and locate the device generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as generalpurpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC through a pull-up resistor.
INT3
INT2
INT1
X
X
X
INT0
0
B3
D2
B1
B0
X
X
X
X
1
X
no interrupt on channel 1
X
X
X
X
X
1
interrupt on channel 1
0
X
no interrupt on channel 0
interrupt on channel 0
0
X
Command
no interrupt on channel 2
X
X
X
X
X
X
1
interrupt on channel 2
0
no interrupt on channel 3
X
X
X
X
X
1
X
X
interrupt on channel 3
Control register read — interrupt
Remark: Several interrupts can be active at the same time. For example: INT3 = 0,INT2 = 1, INT1 = 1, INT0 =
0, means that there is no interrupt on channel 0 and channel 3, and there is an interrupt on channel 1 and on channel
2.
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting
this signal LOW for a minimum of tw(rst)L, the PI4MSD5V9545B/45C will reset its registers and I2C-bus state
machine and will deselect all channels. The RESET input must be connected to VCC through a pull-up resistor.
Power-on reset
When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4MSD5V9545B/45C in a reset
condition until VCC has reached VPOR. At this point, the reset condition is released and the PI4MSD5V9545B/45C
registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be
deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device.
Voltage translation
The pass gate transistors of the PI4MSD5V9545B/45C are constructed such that the VCC voltage can be used to
limit the maximum voltage that is passed from one I2C-bus to another.
Figure 6:Vpass voltage VS Vcc
Figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the
data specified in Section “DC Electrical characteristics” of this data sheet).
In order for the PI4MSD5V9545B/45C to act as a voltage translator, the Vpass voltage should be equal to, or
lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were
3.3 V and 2.7 V, then Vpass should be equal to or below 2.7 V to clamp the downstream bus voltages effectively.
Looking at Figure 6, we see that Vpass (max) is at 2.7 V when the PI4MSD5V9545B/45C supply voltage is 3.5 V
or lower so the PI4MSD5V9545B/45C supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring
the bus voltages to their appropriate levels
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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I2C BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this time are interpreted as control signals
Figure 7: Bit Transfer
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line
while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the STOP condition (P)
Figure 8. Definition of Start and Stop Conditions
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’
Figure 9. System Configuration
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is
not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the
bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into
account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master
to generate a STOP condition.
Figure 10. Acknowledgment on I2C Bus
Data is transmitted to the PI4MSD5V9545B control register using the write mode shown in bellow
Figure 11. Write Control Register
Data is transmitted to the PI4MSD5V9545B control register using the write mode shown in bellow
Figure 12. Read Control Register
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PI4MSD5V9545B/45C
4 Channel I2C bus Switch
with Interrupt Logic and Reset
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Mechanical Information
TSSOP-20L
Ordering Information
Part No.
Package Code
Package
PI4MSD5V9545BLEX
L
20-Pin,173 mil Wide TSSOP, Tape & Reel
PI4MSD5V9545CLEX
L
20-Pin,173 mil Wide TSSOP, Tape & Reel
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2015-07-0039
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