PI4MSD5V9547
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 Channel I2C bus multiplexer with Reset
Features
Description
1-of-8 bidirectional translating multiplexer
I2C-bus interface logic
Operating power supply voltage from 1.65V to
5.5V
Allows voltage level translation between 1.2V,
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Active LOW reset input
Channel selection via I2C bus
Power-up with one channel on
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
JESD78 which exceeds 100 mA
Packages offered: TSSOP-24L,TQFN-24ZD
The PI4MSD5V9547 is an octal bidirectional
translating multiplexer controlled by the I2C-bus. The
SCL/SDA upstream pair fans out to eight downstream
pairs, or channels.
Only one SCx/SDx channel can be selected at a time,
determined by the contents of the programmable control
register. The device powers up with Channel 0
connected, allowing immediate communication between
the master and downstream devices on that channel.
An active LOW reset input allows the
PI4MSD5V9547 to recover from a situation where one
of the downstream I2C-buses is stuck in a LOW state.
Pulling the RESET pin LOW resets the I2C-bus state
machine and causes all the channels to be deselected as
does the internal Power-On Reset (POR) function.
The pass gates of the switches are constructed such
that the VCC pin can be used to limit the maximum high
voltage which is passed by the PI4MSD5V9547. This
allows the use of different bus voltages on each pair, so
that1.2V, 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired
voltage level for each channel. All I/O pins are 5 V
tolerant.
Pin Configuration
TSSOP
TQFN
2016-06-0003
PT0544-3
1
09/02/16
PI4MSD5V9547
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 Channel I2C bus multiplexer with Reset
Pin Description
Pin No.
(TSSOP,
SOIC)
1
2
Pin No.
(TQFN)
Pin Name
Type
Description
22
23
A0
A1
I
I
address input 0
address input 1
I
active LOW reset input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
Power
serial data 0
serial clock 0
serial data 1
serial clock 1
serial data 2
serial clock 2
serial data 3
serial clock 3
supply ground
serial data 4
serial clock 4
serial data 5
serial clock 5
serial data 6
serial clock 6
serial data 7
serial clock 7
address input 2
serial clock line
serial data line
supply voltage
3
24
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
RESET
SD0
T SC0
SD1
SC1
SD2
SC2
SD3
SC3
GND
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
SCL
SDA
VCC
2016-06-0003
PT0544-3
2
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Block Diagram
Figure 1: Block Diagram
Maximum Ratings
Storage Temperature .................................................–55°C to +125°C
Supply Voltage port B .................................................–0.5V to +6.0V
Supply Voltage port A ................................................–0.5V to +6.0V
DC Input Voltage ....................................................... –0.5V to +6.0V
Control Input Voltage (EN)… .................................. –0.5V to +6.0V
Total power dissipation (1).......................................................100mW
Input current(EN,VCC,GND).....................................50mA
ESD: HBM Mode .....................................................................8000V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended operation conditions
Symbol
Parameter
Min
Typ
Max
Unit
VCC
VCCA Positive DC Supply Voltage
1.65
-
5.5
V
VEN
Enable Control Pin Voltage
GND
-
5.5
V
VIO
I/O Pin Voltage
GND
-
5.5
V
Δt /ΔV
Input transition rise or fall time
-
-
10
ns/V
TA
Operating Temperature Range
−40
-
+85
°C
2016-06-0003
PT0544-3
3
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DC Electrical Characteristics
Unless otherwise specified, -40°C≤TA≤85°C, 1.1V≤Vcc≤3.6V
Symbol
Parameter
Conditions
VCC
Min
Typ
Max
Unit
5.5
V
Supply
VCC
ICC
Istb
VPOR[1]
Supply Voltage
supply current
standby current
power-on reset voltage
1.65
operating mode;
no load;
VI = VCC or GND;
fSCL = 100 kHz
standby mode; VCC = 3.6
V;
no load; VI = VCC or
GND;
fSCL = 0 kHz
no load; VI = VCC or
GND
3.6V to 5.5V
65
100
uA
2.3V to 3.6V
20
50
uA
1.65V to 2.3V
10
30
uA
3.6V to 5.5V
0.3
1
uA
2.3V to 3.6V
0.1
1
uA
1.65V to 2.3V
0.1
1
uA
3.6V to 5.5V
1.3
1.5
V
Input SCL; input/output SDA
VIL
LOW-level input voltage
1.65V to 5.5V
-0.5
+0.3VCC
V
1.65V to 2V
0.75VCC
6
V
2V to 5.5V
0.7VCC
6
V
VOL = 0.4 V
1.65V to 5.5V
3
-
mA
VOL = 0.6 V
1.65V to 5.5V
6
-
mA
VIH
HIGH-level input voltage
IOL
LOW-level output current
IIL
LOW-level input current
VI = GND
1.65V to 5.5V
-1
+1
uA
IIH
HIGH-level input current
VI = VCC
1.65V to 5.5V
-1
+1
uA
Ci
input capacitance
VI = GND
1.65V to 5.5V
-
19
pF
14
Select inputs A0, A1, A2,Reset
VIL
LOW-level input voltage
1.65V to 5.5V
-0.5
+0.3VCC
V
VIH
HIGH-level input voltage
1.65V to 5.5V
0.7VCC
6
V
IIL
LOW-level input current
1.65V to 5.5V
-1
Ci
input capacitance
VI = GND
+1
uA
3
5
pF
4
9
24
Ω
3V to 3.6V
5
11
31
Ω
2.3V to 2.7V
7
16
55
Ω
1.65V to 2V
9
20
70
Ω
VI = GND
1.65V to 5.5V
VO = 0.4 V;
IO = 15 mA
4.5 V to 5.5 V
VO = 0.4 V;
IO = 10mA
Pass Gate
Ron
ON-state resistance
5V
4.5 V to 5.5 V
3.6
2.8
3.3V
Vpass
switch output voltage
3V to 3.6V
Vin =VCC;
Iout = -100uA
4.5
2.2
1.6
2.5V
2.3V to 2.7V
V
V
2.8
1.5
1.1
1.8V
V
V
V
2
0.9
V
V
1.65V to 2V
0.54
1.3
V
-1
+1
uA
5
pF
IL
leakage current
VI = VCC or GND
1.65V to 5.5V
Cio
input/output capacitance
VI = VCC or GND
1.65V to 5.5V
3
Note:
[1] VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
2016-06-0003
PT0544-3
4
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AC Electrical characteristics
Tamb = - 40 ºC to +85 ºC; unless otherwise specified.
Symbol
Parameter
tPD[1]
propagation delay
Conditions
from SDA to SDx,
or SCL to SCx
VCC
Min
Typ
1.65V to 5.5V
Max
Unit
0.3
ns
RESET
tw(rst)L
LOW-level reset time
trst
reset time
recovery time to START
condition
tREC;STA
SDA clear
1.65V to 5.5V
4
ns
1.65V to 5.5V
500
ns
1.65V to 5.5V
0
ns
Note
[1]Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15 pF load capacitance.
I2C Interface Timing Requirements
STANDARD MODE
I2C BUS
MIN
MAX
FAST MODE
I2C BUS
MIN
MAX
Symbol
Parameter
fscl
I2C clock frequency
0
tLow
I2C clock high time
4.7
1.3
μs
tHigh
I2C clock low time
4
0.6
μs
tSP
I2C spike time
tSU:DAT
I2C serial-data setup time
100
0
50
50
250
100
[1]
[1]
ns
ns
μs
I2C serial-data hold time
tr
I2C input rise time
1000
300
ns
tf
I2C input fall time
300
300
ns
tBUF
I2C bus free time between stop and start
4.7
1.3
μs
tSU:STA
I2C start or repeated start condition setup
4.7
0.6
μs
tHD:STA
I2C start or repeated start condition hold
4
0.6
μs
tSU:STO
I2C stop condition setup
4
0.6
μs
tVD:ACK
Cb
[2]
Valid-data time (high to low)
SCL low to SDA output low valid
Valid-data time (low to high) [2]
SCL low to SDA output high valid
Valid-data time of ACK condition
ACK signal from SCL low to SDA output low
I2C bus capacitive load
0
kHz
tHD:DAT
tVD:DAT
0
400
UNIT
1
1
μs
0.6
0.6
μs
1
400
1
400
μs
pF
Notes:
[1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL
signal), in order to bridge the undefined region of the falling edge of SCL.
[2] Data taken using a 1-kΩ pull up resistor and 50-pF load Notes
2016-06-0003
PT0544-3
5
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure 2. Definition of timing on the I2C-bus
Application
Figure 3. Typical Application
Recommended application voltage condition
VCC
VPU1
VPU2
1.8V
1.5V-5.5V
1.2V-5.5V
2.5V
1.8V-5.5V
1.8V-5.5V
3.3V
2.7V-5.5V
2.7V-5.5V
5V
4.5V-5.5V
4.5V-5.5V
2016-06-0003
PT0544-3
6
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Device addressing
Following a START condition the bus master must output the address of the slave it is accessing. The address of
the PI4MSD5V9547 is shown in Figure 4.
The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while
a logic 0 selects a write operation.
Figure 4:Device address
Control register
Following the successful acknowledgement of the slave address, the bus master sends a byte to the
PI4MSD5V9547 which is stored in the Control register. If multiple bytes are received by the PI4MSD5V9547, it saves
the last byte received. This register can be written and read via the I2C-bus.
Figure 5: Control register
Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written
after the PI4MSD5V9547 has been addressed. The 4 LSBs of the control byte are used to determine which channel is
to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on
the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
2016-06-0003
PT0544-3
7
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Control register
D7
D6
D5
D4
B3
B2
B1
B0
Command
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
X
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
no channel selected
channel 0 enabled
channel 1 enabled
channel 2 enabled
channel 3 enabled
channel 4 enabled
channel 5 enabled
channel 6 enabled
channel 7 enabled
channel 0 enabled;
power-up/reset default state
Control register: Write — channel selection; Read — channel status
Power-on reset
When power is applied to VCC, an internal Power-On Reset (POR) holds the PI4MSD5V9547 in a reset condition
until VCC has reached VPOR. At this point, the reset condition is released and the PI4MSD5V9547 registers and I2Cbus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter,
VCC must be lowered below 0.2 V for at least 5 us in order to reset the device.
The Reset input
The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting
this signal LOW for a minimum of tw(rst)L, the PI4MSD5V9547 will reset its register and I2C-bus state machine and
will deselect all channels. The RESET input must be connected to VCC through a pull-up resistor.
2016-06-0003
PT0544-3
8
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Voltage translation
The pass gate transistors of the PI4MSD5V9547 are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C-bus to another.
Figure 6:Vpass voltage VS Vcc
Figure 6 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the
data specified in Section “DC Electrical characteristics” of this data sheet).
In order for the PI4MSD5V9547 to act as a voltage translator, the Vpass voltage should be equal to, or lower than
the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and
2.7 V, then Vpass should be equal to or below 2.7 V to clamp the downstream bus voltages effectively.
Looking at Figure 6, we see that Vpass (max) is at 2.7 V when the PI4MSD5V9547 supply voltage is 3.5 V or
lower so the PI4MSD5V9547 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus
voltages to their appropriate levels
I2C BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this time are interpreted as control signals
Figure 7: Bit Transfer
2016-06-0003
PT0544-3
9
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line
while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the STOP condition (P)
Figure 8. Definition of Start and Stop Conditions
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’
Figure 9. System Configuration
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is
not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the
bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master
must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into
account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master
to generate a STOP condition.
Figure 10. Acknowledgment on I2C Bus
2016-06-0003
PT0544-3
10
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Data is transmitted to the PI4MSD5V9547 control register using the write mode shown in bellow
Figure 11. Write Control Register
Data is transmitted to the PI4MSD5V9547 control register using the write mode shown in bellow
Figure 12. Read Control Register
2016-06-0003
PT0544-3
11
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mechanical Information
TSSOP-24(L)
2016-06-0003
PT0544-3
12
09/02/16
PI4MSD5V9547
8 Channel I2C bus Multiplexer with Reset
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
TQFN-24(ZD)
Ordering Information
Part No.
Package Code
Package
PI4MSD5V9547LE
L
24-Pin,173 mil Wide TSSOP
PI4MSD5V9547LEX
L
24-Pin,173 mil Wide TSSOP, Tape &Reel
PI4MSD5V9547ZDEX
ZD
24-Pin,Thine Fine Pitch Quad Flat NoLoad(TQFN), Tape &Reel
Note:
E = Pb-free and Green
Adding X Suffix= Tape/Reel
Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com
Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply
the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The
company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom.
2016-06-0003
PT0544-3
13
09/02/16
工商网监
湘ICP备2023018690号
