PI5USB2544A, PI5USB2546A
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USB Charging Port Controller and Load Detection Power Switch
Features
Description
Two separate current limiting channels
Supports CDP/DCP Modes per USB Battery Charging
Specification 1.2
Supports Shorted Mode per Chinese Telecommunication
Industry Standard YD/T1591-2009
Supports non-BC1.2 Charging Modes by Automatic
Selection
The PI5USB2544A/2546A series is a USB charging port
controller and power switch with an integrated USB 2.0 highspeed data line (D+/D–) switch. PI5USB2544A/2546A
provides the electrical signatures on D+/D– to support
charging schemes listed under device feature section. This
series is compatible with both popular BC1.2 compliant and
non-BC1.2 compliant devices.
System wake up (from S3) with a mouse/keyboard (both low
speed and full speed) is fully supported in the
PI5USB2544A/2546A.
Additionally,
PI5USB2546A
supports two distinct power management features, namely,
power wake and port power management (PPM) through
/STATUS pin. Power wake allows for power supply control
in S4/S5 charging and PPM manages port power in a multiport application.
The PI5USB2544A/2546A series 73-mΩ power-distribution
switch is intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered. Two
programmable current thresholds provide flexibility for
setting current limits and load detect thresholds
Divider-1A mode
Divider-2A mode
Divider-2.4A mode
DCP-1.2V mode
Supports Sleep-Mode Charging and Mouse/Keyboard
Wake up
Automatic SDP/CDP Switching for Devices that do not
request for the CDP Ports
Load Detection for Power Supply Control in S4/S5
Charging and Port Power Management in all Charge
Modes
Compatible with USB 2.0/3.0 Power Switch requirements
Integrated 73-mΩ (Typ.) High-Side MOSFET
Adjustable Current-Limit up to 3A(Typ.)
Operating Range:4.5V to 5.5V
Max Device Current
Applications
2μA at Device Disabled
270μA at Device Enabled
Device Package: TQFN 3.0x3.0-16L
USB Ports (Host and Hubs)
Notebook and Desktop PCs
Universal Wall Charging Adapters
Pin Configuration (TQFN-16L, ZH)
PI5USB2546A
PI5USB2544A
2015-08-0012
PT0513-3
1
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Pin Description
Pin #
Name
Type
Description
1
IN
P
Input voltage and supply voltage; connect 0.1μF or greater ceramic capacitor from
IN to GND as close to the device as possible
2
DM_OUT
I/O
D- Data line to USB host controller.
3
DP_OUT
I/O
D+ data line to USB host controller.
4
ILIM_SEL
I
5
EN
I
6
CTL1
I
7
CTL2
I
8
CTL3
I
STATUS
O
Active-low open-drain output, asserted in load detection conditions (PI5USB2546A).
NC
--
Connect to GND or leave open (PI5USB2544A).
10
DP_IN
I/O
D+ data line to downstream connector.
11
DM_IN
I/O
D- data line to downstream connector.
12
OUT
P
Power-switch output
13
FAULT
O
Active-low open-drain output, asserted when over-temperature or current limit
conditions
14
GND
G
Ground connection.
15
ILIM_LO
I
External resistor connection used to set the low current-limit threshold and the load
detection current threshold. A resistor to ILIM_LO is optional; see Current-Limit
Settings.
16
ILIM_HI
I
External resistor connection used to set the high current-limit threshold.
NA
Exposed PAD
G
Internally connected to GND. Thermal pad to heat-sink the part to the circuit board.
Logic-level input signal used to control the charging mode, current limit threshold,
and load detection, see the control truth table. Can be tied directly to IN or GND
without pull-up or pull-down resistor.
Logic-level input for turning the power switch and the signal switches on/off, logic
low turns off the signal and power switches and holds OUT in discharger. Can be
tied directly to IN or GND without pull-up or pull-down resistor.
Logic-level inputs used to control the charging mode and signal switches; see the
control truth table. Can be tied directly to IN or GND without pull-up or pull-down
resistor.
9
* I = Input; O = Output; P = Power; G = Ground
PI5USB2544A/2546A series Charging Detection Supports Table
Part Number
Non- BC1.2 Charging Mode
Load Detection
DCP-1.2V
Divider-1A
Divider-2A
Divider-2.4A
PI5USB2544A
√
√
√
√
×
PI5USB2546A
√
√
√
√
√
2015-08-0012
PT0513-3
2
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Maximum Ratings
All Input (except IN to OUT, and DP_IN, DM_IN, DP_OUT, DM_OUT) ..........-0.3V to +6.0V
IN to OUT .................................................................................................................................-6.0V to +6.0V
DP_IN, DM_IN, DP_OUT, DM_OUT ...................................................... -0.3V to IN+0.3 or +5.7V
Input clamp current (DP_IN, DM_IN, DP_OUT, DM_OUT) ............................................... ±20mA
Continuous current in SDP or CDP mode
(DP_IN to DP_OUT or DM_IN to DM_OUT)........................................................................±100mA
Continuous current in BC1.2 DCP mode (DP_IN to DM_IN) ................................................ ±50mA
Continuous output current (OUT).....................................................................................Internally limited
Continuous output sink current (/FAULT, /STATUS) ..................................................................25mA
Continuous output source current (ILIM_LO, ILIM_HI) ..........................................internally limited
ESD: HBM Mode (All pins) ...................................................................................................................2kV
CDM Mode (All pins) ................................................................................................................ 500V
HBM (USB connector pins: DP_IN, DM_IN, OUT to GND)............................................6kV
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Recommended Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
4.5
-
5.5
V
Input Voltage, logic-level EN, CTL1, CTL2, CTL3, ILIM_SEL inputs
0
-
5.5
V
Input Voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT
0
-
VIN
V
Input Voltage, IN
VIN
VIH
High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL
1.8
-
-
V
VIL
Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL
-
-
0.8
V
VIH
High-level input voltage
3.5
-
-
V
VIL
Low-level input voltage
-
-
0.8
V
Continuous current data line inputs, SDP or CDP mode, DP_IN to DP_OUT or
DM_IN to DM_OUT
-
-
±30
mA
Continuous current data line inputs, BC1.2 DCP mode, DP_IN to DM_IN
-
-
±15
mA
Continuous output current, OUT
0
-
2.5
A
Continuous output sink current, /FAULT, /STATUS (PI5USB2546A)
0
-
10
mA
Current-limit set resistor
16.9
-
750
kΩ
TA
Ambient Temperature Range
-40
-
85
ºC
TJ
Operating Virtual Junction Temperature Range
-40
-
125
ºC
IOUT
RILIM_XX
2015-08-0012
PT0513-3
3
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Electrical Characteristics
4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ, RILIM_HI=20kΩ,
RILIM_LO=80.6kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ.
Max
TJ = 25oC, IOUT = 2A
73
84
-40oC ≤ TJ ≤ 85oC, IOUT = 2A
73
105
-40oC ≤ TJ ≤ 125oC, IOUT = 2A
73
120
0.7
1.0
1.60
0.2
0.35
0.5
2.7
4
1.7
3
Unit
Power Switch
RDS(on)
On Resistance(1)
tr
OUT voltage rise time
tf
OUT voltage fall time
ton
OUT voltage turn-on time
toff
OUT voltage turn-off time
VIN = 5V, CL = 1μF, RL = 100Ω
ms
VIN = 5V, CL = 1μF, RL = 100Ω
ms
Reverse leakage current
VOUT = 5.5V, VIN = VEN = 0V,
-40oC ≤ TJ ≤ 85oC, Measure IOUT
RDCHG
OUT discharge resistance
VOUT = 4V, VEN = 0V
400
tDCHG
OUT discharge hold time
Time VOUT< 0.7V
IREV
mΩ
2
μA
500
630
Ω
1.30
2.0
2.9
s
-
1
1.35
1.70
V
-
0.85
1.15
1.45
V
-
-
200
-
mV
-0.5
-
0.5
µA
Discharge
EN, ILIM_SEL, CTL1,CTL2, CTL3, inputs
Input pin rising logic
threshold voltage
Input pin falling logic
threshold voltage
Hysteresis(2)
Input current
(1)
(2)
Pin voltage= 0V to 5.5V
Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account separately
These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product
warranty
2015-08-0012
PT0513-3
4
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Electrical Characteristics
4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ, RILIM_HI=20kΩ,
RILIM_LO=80.6kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. unless otherwise specified.
Symbol
Description
Test Conditions
Min.
Typ.
Max.
Unit
VILIM_SEL= 0 V RILIM_LO=210kΩ
205
240
275
VILIM_SEL= 0 V RILIM_LO=80.6kΩ
VILIM_SEL= 0 V RILIM_LO=22.1kΩ
VILIM_SEL= VIN RILIM_HI=20kΩ
VILIM_SEL= VIN RILIM_HI=16.9kΩ
575
2120
2340
2770
625
2275
2510
2970
680
2430
2685
3170
-
1.5
-
VEN=0V, VOUT=0V, TJ =-40°C to +125°C
-
0.1
2
VCTL1=VCTL2= VIN, VCTL3= 0V VILIM_SEL = 0V
-
165
220
VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = 0V
-
175
230
VCTL1 = VCTL2 = VIN, VCTL3 = 0V, VILIM_SEL = VIN
-
185
240
VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = VIN
-
195
250
VCTL1 = 0V, VCTL2 = VCTL3 = VIN, VILIM_SEL = 0V
-
215
270
VCTL1 = 0V, VCTL2 = VCTL3 = VIN, VILIM_SEL = VIN
-
240
290
-
3.9
4.1
4.3
V
-
-
100
-
mV
ILIM_SEL Current Limit
(2)
IOS
OUT Current-limit
tIOS
Response time to OUT short circuit(1)
VIN = 5.0V, R=0.1Ω, lead length=2”
mA
s
Supply Current
IIN_OFF
IIN_ON
Disabled IN supply current
Enable IN supply current
A
Undervoltage Lockout
VUVLO
IN rising UVLO threshold voltage
(1)
Hysteresis
/FAULT
VOL
Output low voltage
I/FAULT = 1mA
-
-
100
mV
IOFF
Off-state leakage current
V/FAULT = 5.5V
-
-
1
A
TD
Over current /FAULT rising and falling deglitch
5
8.2
12
ms
-
/STATUS (PI5USB2546A)
VOL
Output low voltage
I/STATUS = 1mA
-
-
100
mV
IOFF
Off-state leakage
V/STATUS = 5.5V
-
-
1
A
170
-
20
-
Thermal Shutdown
OTSD
Thermal shutdown threshold
-
(1)
Hysteresis
-
-
°C
Note:
(1) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes of Pericom's product
warranty
(2) Pulse-testing techniques maintain junction temperature close to ambient temperature; current limit value tested at 80% output voltage. Thermal effects must
be taken into account separately.
2015-08-0012
PT0513-3
5
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Electrical Characteristics, High-bandwidth Switch
4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ RILIM_HI=20kΩ,
RILIM_LO=80.6kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. unless otherwise specified.
Symbol
Description
Test Conditions
Min.
Typ.
Max.
Unit
VDP/DM_OUT= 0V, IDP/DM_IN= 30mA
-
2
4
Ω
VDP/DM_OUT= 2.4V, IDP/DM_IN= -15mA
-
3
6
Ω
VDP/DM_OUT= 0V, IDP/DM_IN= 30mA
-
0.05
0.15
Ω
VDP/DM_OUT= 2.4V, IDP/DM_IN= -15mA
VEN=0V, VDP/DM_IN= 0.3V,
Vac= 0.6VPK-PK, f=1MHz
-
0.05
0.15
Ω
-
4.5
-
pF
VDP/DM_IN= 0.3V,Vac= 0.6VPK-PK, f = 1MHz
-
5.4
6.2
pF
VEN = 0V, f = 250MHz
-
33
-
dB
f = 250MHz
VEN = 0V, VDP/DM_IN = 3.6V, VDP/DM_OUT =
0V, measure IDP/DM_OUT
RL =50Ω
-
52
-
dB
-
0.1
1.5
A
-
2.0
-
GHz
-
-
0.25
-
ns
-
-
0.1
0.2
ns
HIGH_BANDWIDTH ANALOG SWITCH
DP/DM switch on resistance
Switch resistance mismatch
between DP/DM channels
OIRR
XTALK
DP/DM switch off-state
capacitance(1)
DP/DM switch on-state
capacitance(2)
Off-state isolation(3)
Off-state cross channel isolation
IOFF
Off-state leakage current
BW
Bandwidth(-3dB)(3)
tpd
tSK
(3)
Propagation delay(3)
Skew between opposite transitions
of the same port(tPHL – tPLH)
Note:
(1) The resistance in series with the parasitic capacitance to GND is typically 250 Ω.
(2) The resistance in series with the parasitic capacitance to GND is typically 150 Ω.
(3) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes
of Pericom's product warranty.
2015-08-0012
PT0513-3
6
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Electrical Characteristics, Charging Controller
4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ RILIM_HI=20kΩ,
RILIM_LO=80.6kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. unless otherwise specified.
Symbol
Description
Test Conditions
Min.
Typ.
Max.
Unit
-
125
200
Ω
1.19
1.25
1.31
V
60
75
94
kΩ
1.9
2.0
2.1
V
2.57
2.7
2.84
V
7.5
10.5
16
kΩ
2.57
2.7
2.84
V
1.9
2.0
2.1
V
7.5
10.5
16
kΩ
2.57
2.7
2.84
V
7.5
10.5
16
kΩ
0.5
0.6
0.7
V
0.25
-
0.4
V
-
50
-
mV
0.8
-
1.5
V
-
100
-
mV
550
650
765
mA
-
50
-
mA
Load detect set time
140
200
275
ms
Load detect reset time
1.9
3
4.2
s
SHORTED MODE (BC1.2 DCP)
DP_IN/DM_IN shorting resistance
VCTL1= VIN; VCTL2= VCTL3= 0V
DCP-1.2V MODE
DP_IN/DM_IN output voltage
DP_IN/DM_IN output impedance
VCTL1= 0V; VCTL2= VCTL3= VIN,
Apply 3V on DP_IN for 0.5s and
measure the D+/D- voltage within the 2s
DIVIDER-1A MODE
DP_IN Divider-1A output voltage
DM_IN Divider-1A output voltage
VCTL1= 0V; VCTL2= VCTL3= VIN,
DP_IN/DM_IN output impedance
DIVIDER-2A MODE
DP_IN Divider-2A output voltage
DM_IN Divider-2A output voltage
VCTL1= 0V; VCTL2= VCTL3= VIN;
IOUT= 1A
DP_IN/DM_IN output impedance
DIVIDER-2.4A MODE
DP_IN/DM_IN output voltage
DP_IN/DM_IN output impedance
VCTL1= 0V; VCTL2= VCTL3= VIN;
IOUT = 1.7A
CHARGING DOWNSTREAM PORT
VDM_SRC
VDAT_REF
VLGC_REF
DP_IN CDP output voltage
DP_IN rising lower window
threshold for VDM_SRC activation
Hysteresis(1)
DP_IN rising upper window
threshold for VDM_SRC de-activation
Hysteresis(1)
LOAD DETECT- NON POWER WAKE
IOUT rising load detect current
ILD
threshold
Hysteresis(1)
tLD_SET
VCTL1= VCTL2= VCTL3= VIN, VIN =0.6V,
-250μA ≤ IDM_IN ≤ 0μA
VCTL1= VCTL2= VCTL3= VIN
VCTL1= VCTL2= VCTL3= VIN
Note:
(1) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes
of Pericom's product warranty.
2015-08-0012
PT0513-3
7
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Electrical Characteristics, Charging Controller
4.5V≤VIN≤5.5V; TJ=-40°C to +125°C; VEN =VIN, VILIM_SEL=VIN, VCTL1= VCTL2= VCTL3=VIN, R/FAULT=R/STATUS=10kΩ RILIM_HI=20kΩ,
RILIM_LO=80.6kΩ, Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND. unless otherwise specified.
Symbol
Description
LOAD DETECT- POWER WAKE
Power wake short circuit current
IOS_PW
limit
IOUT falling power wake reset
current threshold
Reset current hysteresis(1)
Test Conditions
VCTL1= VCTL2= 0V, VCTL3= VIN
Power wake reset time
Min.
Typ.
Max.
Unit
20
55
90
mA
10
45
85
mA
-
5
-
mA
10.7
15
20.6
s
Note:
(1) These parameters are provided for reference only and do not constitute part of Pericom's published device specifications for purposes
of Pericom's product warranty.
2015-08-0012
PT0513-3
8
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Functional Description
PI5USB2546A Block Diagram
IN
ILIM_HI
ILIM_LO
ILIM_SEL
OUT
Current
Limit
Select
Disable+UVLO+
Discharger
Current
Limit
Charger
Pump
OC
UVLO
GND
OTSD
Thermal
Sense
Driver
Load
Detection
8msDeglitch
FAULT
Discharge
EN
8ms-Deglitch
(Falling edge)
DM_OUT
DM_IN
DP_OUT
DP_IN
OC
CTL1
CTL2
Logic
Control
CDP
Detection
DCP
Detection
Divider
Modes
Auto
Detection
Load
Detection
Discharge
STATUS
CTL3
Discharge
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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PI5USB2544A Block Diagram
IN
ILIM_HI
ILIM_LO
ILIM_SEL
OUT
Current
Limit
Select
Disable+UVLO+
Discharger
Current
Limit
Charger
Pump
OC
UVLO
Driver
8msDeglitch
GND
OTSD
Thermal
Sense
FAULT
Discharge
EN
8ms-Deglitch
(Falling edge)
DM_OUT
DM_IN
DP_OUT
DP_IN
OC
CTL1
CTL2
Logic
Control
CDP
Detection
DCP
Detection
Divider
Modes
Auto
Detection
Discharge
CTL3
Discharge
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Details Description
The following overview references various industry standards. It is always recommended to consult the most up-to-date
standard to ensure the most recent and accurate information. Rechargeable portable equipment requires an external power
source to charge its batteries. USB ports are a convenient location for charging because of an available 5V power source.
Universally accepted standards are required to make sure host and client-side devices operate together in a system to ensure
power management requirements are met. Traditionally, host ports following the USB 2.0 specification must provide at least
500mA to downstream client-side devices. Because multiple USB devices can be attached to a single USB port through a buspowered hub, it is the responsibility of the client-side device to negotiate its power allotment from the host to ensure the total
current draw does not exceed 500mA. In general, each USB device is granted 100mA and may request more current in 100mA
unit steps up to 500mA. The host may grant or deny based on the available current. A USB 3.0 host port not only provides
higher data rate than USB 2.0 port but also raises the unit load from 100mA to 150mA. It is also required to provide a minimum
current of 900mA to downstream client-side devices.
Additionally, the success of USB has made the mini-USB connector a popular choice for wall adapter cables. This allows a
portable device to charge from both a wall adapter and USB port with only one connector. As USB charging has gained
popularity, the 500mA minimum defined by USB 2.0 or 900mA for USB 3.0 has become insufficient for many handset and
personal media players which need a higher charging rate. Wall adapters can provide much more current than 500mA/900mA.
Several new standards have been introduced defining protocol handshaking methods that allow host and client devices to
acknowledge and draw additional current beyond the 500mA/900mA minimum defined by USB 2.0/3.0 while still using a
single micro-USB input connector. The PI5USB2546 supports four of the most common USB charging schemes found in
popular hand-held media and cellular devices:
USB Battery Charging Specification BC1.2
Chinese Telecommunications Industry Standard YD/T 1591-2009
Divider-1A, Divider-2A and Divider-2.4A Mode
DCP-1.2V Mode
YD/T 1591-2009 is a subset of BC1.2 spec. supported by vast majority of devices that implement USB charging.
Divider-1A, Divider-2A, Divider-2.4A and DCP-1.2V charging schemes are supported in devices from specific yet popular device
makers.
BC1.2 lists three different port types as listed below:
Standard Downstream Port (SDP)
Charging Downstream Port (CDP)
Dedicated Charging Port (DCP)
BC1.2 defines a charging port as a downstream facing USB port that provides power for charging portable equipment, under
this definition CDP and DCP are defined as charging ports
Table 1 shows the differences between these ports.
Table 1. Operation Modes
Port Type
Support USB 2.0 Communication
SDP (USB 2.0)
SDP (USB 3.0)
CDP
DCP
Yes
Yes
Yes
No
2015-08-0012
Max. allowable current draw by
portable device
0.5A
0.9A
1.5A
1.5A
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Standard Downstream Port (SDP) USB 2.0/USB 3.0
An SDP is a traditional USB port that follows USB 2.0/3.0 protocol and supplies a minimum of 500mA/900mA per port. USB
2.0/3.0 communications is supported, and the host controller must be active to allow charging. PI5USB2544A/2546A supports
SDP mode in system power state S0 when system is completely powered ON and fully operational. For more details on control
pin (CTL1, CTL2, CTL3 and ILIM_SEL) settings to program this state please refer to device truth table.
Charging Downstream Port (CDP)
A CDP is a USB port that follows USB BC1.2 and supplies a minimum of 1.5A per port. It provides power and meets USB 2.0
requirements for device enumeration. USB 2.0 communications is supported and the host controller must be active to allow
charging. What separates a CDP from an SDP is the host-charge handshaking logic that identifies this port as a CDP. A CDP is
identifiable by a compliant BC1.2 client device and allows for additional current draw by the client device.
The CDP hand-shaking process is done in two steps. During step one the portable equipment outputs a nominal 0.6V output on
its D+ line and reads the voltage input on its D- line. The portable device concludes it is connected to an SDP if the voltage is
less than the nominal data detect voltage of 0.3V. The portable device concludes that it is connected to a Charging Port if the Dvoltage is greater than the nominal data detect voltage of 0.3V and optionally less than 0.8V.
The second step is necessary for portable equipment to determine if it is connected to CDP or DCP. The portable device outputs
a nominal 0.6V output on its D- line and reads the voltage input on its D+ line. The portable device concludes it is connected to
a CDP if the data line being read remains less than the nominal data detection voltage of 0.3V. The portable device concludes it
is connected to a DCP if the data line being read is greater than the nominal data detect voltage of 0.3V.
PI5USB2544A/2546A series supports CDP mode in system power state S0 when system is completely powered ON and fully
operational. For more details on control pin (CTL1, CTL2, CTL3 and ILIM_SEL) settings to program this state please refer to
device truth table.
Dedicated Charging Port (DCP)
A DCP only provides power but does not support data connection to an upstream port. As shown in following sections, a DCP
is identified by the electrical characteristics of its data lines. The PI5USB2544A/2546A series emulates DCP in two charging
states, namely DCP Forced and DCP Auto as shown in Figure 4. In DCP Forced state the device will support one of the two
DCP charging schemes, namely Divider-1A or DCP_Shorted. In the DCP Auto state, the device charge detection state machine
is activated to selectively implement charging schemes involved with the Shorted DCP mode, Divider-1A, Divider-2A,
Divider-2.4A and DCP-1.2V modes. Shorted DCP mode complies with BC1.2 and Chinese Telecommunications Industry
Standard YD/T 1591-2009, while the Divider-1A, Divider-2A, Divider-2.4A and DCP-1.2V modes are employed to charge
devices that do not comply with BC1.2 DCP standard.
DCP BC1.2 and YD/T 1591-2009
Both standards define that the D+ and D- data lines should be shorted together with a maximum series impedance of 200 Ω.
This is shown as Figure 1.
VBUS
PI5USB2544A/2546A
2.0V
D- OUT
200Ω
USB
Host/Hub
CDP
Detect
Auto
Detect
D-
USB
Connector
1.2V
D+OUT
2.7V
D+
GND
Figure 1, DCP mode
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Divider-1A, Divider-2A and Divider-2.4A Charging Scheme
There are two charging schemes supported by PI5USB2544A/2546A, Divider-1A, Divider-2A and Divider-2.4A as shown
below. In Divider-1A charging scheme the device applies 2.0V and 2.7V to D+ and D- data line respectively. This is reversed
in Divider-2A mode. Divider-2.4A charging scheme on PI5USB2544A or PI5USB2546A is applying 2.7V on both D+ and D-..
VBUS
D- OUT
PI5USB2544A/2546A
2.7V
USB
Host/Hub
CDP
Detect
D-
Auto
Detect
USB
Connector
1.2V
D+OUT
D+
2.0V
GND
Figure 2a, Divider-1A Charging Scheme
VBUS
PI5USB2544A/2546A
2.0V
D- OUT
USB
Host/Hub
CDP
Detect
D-
Auto
Detect
USB
Connector
1.2V
D+OUT
D+
2.7V
GND
Figure 2b, Divider-2A Charging Scheme
PI5USB2544A/2546A
VBUS
2.7V
D- OUT
USB
Host/Hub
CDP
Detect
Auto
Detect
D-
USB
Connector
1.2V
D+OUT
2.7V
D+
GND
Figure 2c, Divider-2.4A Charging Scheme
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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DCP-1.2V Charging Scheme
DCP-1.2V charging scheme is used by some handheld devices to enable fast charging at 2.0A. PI5USB2544A/2546A series
supports this scheme in the DCP-Auto mode before the device enters BC1.2 shorted mode. To simulate this charging scheme
D+/D- lines are shorted and pulled-up to 1.2V for fixed duration then device moves to DCP shorted mode as defined in BC1.2
spec. This is shown as Figure 3.
VBUS
PI5USB2544A/2546A
2.0V
D- OUT
USB
Host/Hub
CDP
Detect
D-
Auto
Detect
USB
Connector
1.2V
D+OUT
D+
2.7V
GND
Figure 3, DCP-1.2V Charging Scheme
DCP Auto Mode
As mentioned above the PI5USB2544A/2546A integrates an auto-detect state machine that supports all the above DCP
charging schemes. It starts in Divider-1A scheme, however if a BC1.2 or YD/T 1591-2009 compliant device is attached, the
PI5USB2544A/2546A responds by discharging OUT, turning back on the power switch and operating in 1.2Vmode briefly and
then moving to BC1.2 DCP mode. It then stays in that mode until the device releases the data line, in which case it goes back to
Divider-1A scheme. When a Divider-1A compliant device is attached the PI5USB2544A/2546A series will stay in Divider-1A
state.
Also, the PI5USB2544A/2546A series will automatically switch between the Divider-1A and Divider-2A (or Divider-2.4A)
schemes based on charging current drawn by the connected device. Initially the device will set the data lines to Divider-1A
scheme. If charging current of the device >900mA is measured by the PI5USB2544A/2546A series, it switches to Divider-2A
scheme and test to see if the peripheral device will still charge at a high current. If charging current of the device >1.8A is
measured by PI5USB2544A or PI5USB2546A, it will switches to Divider-2.4A charging mode. If it does then it stays in
Divider-2A or Divider-2.4A charging scheme otherwise it will revert to Divider-1A scheme.
PI5USB2544A/2546A
To
USB
2.0
Host
BC1.2 CDP
Controlled by
CTL pins settings
DCP Auto
DBC1.2 DCP
/DCP-1.2V
D+
Divider-1A
/2A /2.4A
Figure 4, DCP_Auto Mode
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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DCP Forced Shorted / DCP Forced Divider-1A
In this mode the device is permanently set to one of the DCP schemes (BC1.2/ YD/T 1591-2009 or Divider-1A) as commanded
by its control pin setting per device truth table.
High-Bandwidth Data Line Switch
The PI5USB2544A/2546A series passes the D+ and D- data lines through the device to enable monitoring and handshaking
while supporting charging operation. A wide bandwidth signal switch is used, allowing data to pass through the device without
corrupting signal integrity. The data line switches are turned on in any of CDP or SDP operating modes.
The EN input also needs to be at logic High for the data line switches to be enabled.
NOTE:
1.
2.
3.
4.
Under CDP mode, the data switches are ON even while CDP handshaking is occurring.
The data line switches are OFF if EN or all CTL pins are held low, or if in DCP mode. They are not automatically
turned off if the power switch (IN to OUT) is in current limit.
The data switches are for USB 2.0 differential pair only. In the case of a USB 3.0 host, the super speed differential
pairs must be routed directly to the USB connector without passing through the PI5USB2544A/2546A series.
Data switches are OFF during OUT (VBUS) discharge
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Device Operation
Please refer to the simplified device state diagram below. Power-on-reset (POR) holds device in initial state while output is held
in discharge mode. Any POR event will take the device back to initial state. After POR clears, device goes to the next state
depending on the CTL1, CTL2, CTL3 and ILIM_SEL lines as shown Figure 5.
DCP_Auto
Reset
Sample
CTL
PinsDisc
CDP
(1111)
DCH
DCP_Short
Divider-1A
DCH/SDP/CDP
DCH
Done
DCP Forced (DCP
Shorted or Divider1A)
DCP_Auto
DCP_Shorted/
Divider-1A
DCH/SDP/CDP
SDP1
(111x/
010x)
Discharge
SDP2
(1110)
DCP Auto (DCP Shorted
/DCP-1.2V
/ Divider-1A/2A/2.4A)
Not SDP1
Not SDP2
or CDP
SDP1
CDP
CDP
(1111)
SDP2
(1110)
SDP2
Note:
1) All shaded boxed are device charging modes.
2) See below table for CTL settings corresponding to flow
line conditions
Device Control Pins
Flow Line Condition CTL1 CTL2 CTL3 ILIM_SEL
DCH(Discharge)
0
0
0
x
CDP
1
1
1
1
SDP2(No Discharge
1
1
1
0
from/to CDP)
SDP1(Discharge
1
1
0
x
from/to any charging
0
1
0
x
state including CDP)
DCP_Short
1
0
0
x
DCP/Divider-1A
1
0
1
x
0
1
1
x
DCP_Auto
0
0
1
x
Figure 5, PI5USB2544A/2546A Charging States
Output Discharge
To allow a charging port to renegotiate current with a portable device, PI5USB2544A/2546A uses the OUT discharge function.
It proceeds by turning off the power switch while discharging OUT, then turning back on the power switch to reassert the OUT
voltage. This discharge function is automatically applied as shown in device state diagram.
2015-08-0012
PT0513-3
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Wake on USB Feature (Mouse/Keyboard Wake Feature)
USB 2.0 Background Information
The PI5USB2544A/2546A data lines interface with USB 2.0 devices. USB 2.0 defines three types of devices according to data
rate. These devices and their characteristics relevant to PI5USB2544A/2546A series Wake on USB operation are shown below:
Low-speed USB devices
1.5 Mb/s
Wired mice and keyboards are examples
No devices that need battery charging
All signaling performed at 2.0V and 0.8V hi/lo logic levels
D- high to signal connect and when placed into suspend
D- high when not transmitting data packets
Full-speed USB devices
12 Mb/s
Wireless mice and keyboards are examples
Legacy phones and music players are examples
Some legacy devices that need battery charging
All signaling performed at 2.0V and 0.8V hi/lo logic levels
D+ high to signal connect and when placed into suspend
D+ high when not transmitting data packets
High-speed USB devices
480 Mb/s
Tablets, phones and music players are examples
Many devices that need battery charging
Connect and suspend signaling performed at 2.0V and 0.8V hi/lo logic levels
Data packet signaling performed a logic levels below 0.8V
D+ high to signal connect and when placed into suspend (same as a full-speed device)
D+ and D- low when not transmitting data packets
Wake On USB
Wake on USB is the ability of a wake configured USB device to wake a computer system from its S3 sleep state back to its S0
working state. Wake on USB requires the data lines to be connected to the system USB host before the system is placed into its
S3 sleep state and remain continuously connected until they are used to wake the system.
The PI5USB2544A/2546A supports low and full speed HID (human interface device like mouse/key board) wake function.
There are two scenarios under which wake on mouse are supported by the PI5USB2544A/2546A series. The specific CTL pin
changes that the PI5USB2544A/2546A will override are shown below. The information is presented as CTL1, CTL2 and
CTL3.The ILIM_SEL pin plays no role
1.
2.
111 (CDP/SDP2) to 011 (DCP-Auto)
110/010 (SDP1) to 011 (DCP-Auto)
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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USB Low-Speed / Full-Speed Device Recognition
PI5USB2544A/2546A series is capable of detecting LS or FS device attachment when PI5USB2544A/2546A is in SDP or CDP
mode. Per USB spec when no device is attached, the D+ and D- lines are near ground level. When a low speed compliant
device is attached to the PI5USB2544A/2546A charging port, D- line will be pulled high in its idle state (mouse/keyboard not
activated). However when a FS device is attached the opposite is true in its idle state, i.e. D+ is pulled high and D- remains at
ground level.
PI5USB2544A/2546A monitors both D+ and D- lines while CTL pin settings are in CDP or SDP mode to detect LS or FS HID
device attachment. To support HID sleep wake, PI5USB2544A/2546A must first determine that it is attached to a LS or FS
device when system is in S0 power state. PI5USB2544A/2546A does this as described above. While supporting a LS HID wake
is straight forward, supporting FS HID requires making a distinction between a FS and a HS device. This is because a high
speed device will always present itself initially as a full speed device (by a 1.5K pull up resistor on D+). The negotiation for
high speed then makes the distinction whereby the 1.5K pull up resistor gets removed.
PI5USB2544A/2546A handles the distinction between a FS and HS device at connect by memorizing if the D+ line goes low
after connect. A HS device after connect will always undergo negotiation for HS which will require the 1.5KΩ resistor pull-up
on D+ to be removed. To memorize a FS device, PI5USB2544A/2546A requires the device to remain connected for at least 11
sec while system is in S0 mode before placing it in sleep or S3 mode. If system is placed in sleep mode earlier than the 11 sec
window, a FS device may not get recognized and hence could fail to wake system from S3. This requirement does not apply for
LS device.
No CTL Pin Timing Requirement after Wake Event and Transition from S3 to S0
There is no CTL pin timing requirement for the PI5USB2544A/2546A when the wake configured USB device wakes the
system from S3 back to S0.
2015-08-0012
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PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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Device Control Pins Truth Table
Device Control Pins Table lists all valid bias combinations for the four control pins CTL1, CTL2, CTL3 and ILIM_SEL pins
and their corresponding charging mode. It is important to note that the Device Control Pins Table purposely omits matching
charging modes of the PI5USB2544A/2546A with global power states (S0-S5) as device is agnostic to system power states.
The PI5USB2544A/2546A monitors its CTL inputs and will transition to whatever charging state it is commanded to go to
(except when LS/FS HID device is detected). For example if sleep charging is desired when system is in standby or hibernate
state then user must set PI5USB2544A/2546A control pins to correspond to DCP_Auto charging mode per below table. When
system is put back to operation mode then set control pins to correspond to SDP or CDP mode and so on.
PI5USB2546A Device Control Pins Truth Table
CTL1
CTL2
CTL3
ILIM_SEL
MODE
0
0
0
0
0
0
0
0
1
0
1
0
Discharge
Discharge
DCP_Auto
0
0
1
1
DCP_Auto
0
0
1
1
0
0
0
1
SDP1
SDP1
Current
Limit Setting
NA
NA
ILIM_HI
IOS_PW &
ILIM_HI(1)
ILIM_LO
ILIM_HI
/STATUS Output
(Active low)
OFF
OFF
OFF
0
1
1
0
DCP_Auto
ILIM_HI
OFF
0
1
1
1
DCP_Auto
ILIM_HI
DCP load present(3)
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
DCP_Shorted
DCP_Shorted
Divider-1A
Divider-1A
SDP1
SDP1
ILIM_LO
ILIM_HI
ILIM_LO
ILIM_HI
ILIM_LO
ILIM_HI
OFF
OFF
OFF
OFF
OFF
OFF
1
1
1
0
SDP2(4)
ILIM_LO
OFF
1
1
1
1
CDP(4)
ILIM_HI
CDP load present(5)
DCP load present(2)
OFF
OFF
Comment
OUT held low
Data lines disconnected
Data lines disconnected and
load detect function active
Data lines connected
Data lines disconnected
Data lines disconnected and
load detect function active
Device forced to stay in
DCP BC1.2 charging mode
Device forced to stay in
Divider-1A charging mode
Data lines connected
Data lines connected and
load detect active
Note:
(1)
(2)
(3)
(4)
(5)
PI5USB2546A: Current limit (IOS) is automatically switched between IOS_PW and the value set by ILIM_HI according to the Load Detect –Power
Wake functionality.
DCP Load present governed by the “Load Detection – Power Wake” limits.
DCP Load present governed by the “Load Detection – Non Power Wake” limits.
No OUT discharge when changing between 1111 and 1110.
CDP Load present governed by the “Load Detection – Non Power Wake” limits and BC1.2 primary detection.
2015-08-0012
PT0513-3
19
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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PI5USB2544A Device Control Pins Truth Table
CTL1
CTL2
CTL3
ILIM_SEL
MODE
0
0
0
0
0
0
0
1
Discharge
Discharge
Current Limit
Setting
NA
NA
0
0
0
0
0
1
x
1
1
1
1
0
1
0
0
1
1
0
x
0
1
0
1
0
DCP_Auto
SDP1
SDP1
DCP_Auto
DCP_Auto
DCP_Shorted
ILIM_HI
ILIM_LO
ILIM_HI
ILIM_HI
ILIM_HI
ILIM_LO
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
DCP_Shorted
Divider-1A
Divider-1A
SDP1
SDP1
SDP2(1)
ILIM_HI
ILIM_LO
ILIM_HI
ILIM_LO
ILIM_HI
ILIM_LO
1
1
1
1
CDP(1)
ILIM_HI
Comment
OUT held low
Data lines disconnected
Data lines connected
Data lines disconnected
Data lines disconnected
Device forced to stay in DCP BC1.2
charging mode
Device forced to stay in Divider-1A
charging mode
Data lines connected
Data lines connected
Note:
(1) No OUT discharge when changing between 1111 and 1110.
Below tables can be used as an aid to program the PI5USB2544A/2546A per system states however not restricted to below
settings only.
PI5USB2546A Control Pin Setting Matched to System Power States
System Global
Power State
S0
S0
S0
S4/S5
S3/S4/S5
S3
S3
S3
Charging Mode
CTL1
CTL2
CTL3
ILIM_SEL
1
1
1
1
0
1
1 or 0
0
Current Limit
Setting
ILIM_HI/ILIM_LO
ILIM_LO
1
1
1
1
ILIM_HI
0
0
1
1
ILIM_HI
0
0
1
0
ILIM_HI
0
1
1
1
ILIM_HI
0
1
1
0
ILIM_HI
0
1
0
1 or 0
ILIM_HI/ILIM_LO
SDP1
SDP2, no discharge to/from CDP
CDP, load detection with ILIM_LO +
25mA thresholds or if a BC1.2 primary
detection occurs
Auto mode, load detection with power
wake thresholds
Auto mode, no load detection
Auto mode, keyboard/mouse wake up,
load detection with ILIM_LO + 25mA
thresholds
Auto mode, keyboard/mouse wake up,
no load detection
SDP1, keyboard/mouse wake up
2015-08-0012
PT0513-3
20
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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PI5USB2544A Control Pin Setting Matched to System Power States
System Global
Power State
S0
S0
S0
S3/S4/S5
S3
S3
CTL1
CTL2
CTL3
ILIM_SEL
SDP1
SDP2, no discharge to/from CDP
1
1
1
1
0
1
1 or 0
0
Current Limit
Setting
ILIM_HI/ILIM_LO
ILIM_LO
CDP
Auto mode
Auto mode, keyboard/mouse wake up,
no load detection
SDP1, keyboard/mouse wake up
1
0
1
0
1
1
1
0
ILIM_HI
ILIM_HI
0
1
1
0
ILIM_HI
0
1
0
1 or 0
ILIM_HI/ILIM_LO
Charging Mode
Load Detect (PI5USB2546A)
PI5USB2546A offer system designers unique power management strategy not available in the industry from similar devices.
There are two power management schemes supported by the PI5USB2546A via the /STATUS pin, they are:
1.
2.
Power Wake (PW)
Port Power Management (PPM)
Either feature may be implemented in a system depending on power savings goals for the system. In general Power Wake
feature is used mainly in mobile systems like a notebook where it is imperative to save battery power when system is in deep
sleep (S4/S5) state. On the other hand Port Power Management feature would be implemented where multiple charging ports
are supported in the same system and system power rating is not capable of supporting high current charging on multiple ports
simultaneously.
Power Wake (PI5USB2546A)
Goal of power wake feature is to save system power when system is in S4/S5 state. In S4/S5 state system is in deep sleep and
typically running of the battery; so every “mW” in system power savings will translate to extending battery life. In this state the
PI5USB2546A will monitor charging current at the OUT pin and provide a mechanism via the /STATUS pin to switch out the
high power DC-DC controller and switch in a low power LDO when charging current requirement is 2s (typ.) to allow the main power supply to turn on. After the discharge
the device will turn back on with current limit set by ILIM_HI (Case 1, Figure 7)
2015-08-0012
PT0513-3
23
8/31/15
PI5USB2544A, PI5USB2546A
USB Charging Port Controller and Load Detection Power Switch
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DC/DC Disconnected/ShutDown LDO Switch-In
Power Block
19V
OU
EN
GN
EN
|||||||||||||||||
Turn HIGH
after 15s
Ilimit set to 55mA when charging
current falls to
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湘ICP备2023018690号
