PI6C10807HE

PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer Features Description • High-speed, low-noise, non-inverting 1-10 buffer The PI6C10807 is a 1.8V, or 2.5V high-speed, low-noise 1-10 non-inverting clock buffer. The key goal in designing the PI6C10807 is to target networking applications that require lowskew, low-jitter, and high-frequency clock distribution. • Maximum Frequency up to 250 MHz • Low output skew < 60ps • Low duty cycle distortion < 200ps Providing output-to-output skew as low as 60ps, the PI6C10807 is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs. • Low propagation delay < 2.0ns • Multiple VDD, GND pins for noise reduction • 1.8V or 2.5V supply voltage • Packages (Pb-free & Green): ▫20-pin, TSSOP (L20) ▫20-pin, SSOP (H20) Block Diagram Pin Configuration BUF_IN 1 20 VDD GND 2 19 CLK9 CLK0 3 18 CLK8 VDD 4 17 GND CLK1 5 16 CLK7 GND 6 15 VDD CLK2 7 14 CLK6 VDD 8 13 GND CLK3 9 12 CLK5 GND 10 11 CLK4 Pin Description Pin Name BUF_IN CLK [0:9] GND VDD 09-0084 1 Description Input Outputs Ground Power PS8862L 05/01/09 PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer 2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Storage Temperature...........................................................–65°C to +150°C VDD Voltage ..........................................................................–0.5V to +3.6V Output Voltage (max. 3.6V) .......................................... –0.5V to VDD+0.5V Input Voltage (max 3.6V) .............................................. –0.5V to VDD+0.5V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.5V DC Characteristics (Over Operating Range: VDD = 2.5V ± 0.2V, TA = -40° to 85°C) Test Conditions1 Parameters Description Min. Typ.2 Max. 2.3 2.5 2.7 VDD Supply Voltage VIH Input HIGH Voltage Logic HIGH level 1.7 3.6 VIL Input LOW Voltage Logic LOW level -0.3 0.7 II Input Current VDD = Max, Vin = VDD or GND Output High Voltage VOH Output LOW Voltage VOL VDD = Min., VIN = VIH or VIL VDD = Min., VIN - VIH or VIL 15 IOH = -1mA 2.0 IOH = -2mA 1.7 IOH = -8mA 1.7 IOL = 1mA 0.1 IOL = 2mA 0.2 IOL = 8mA 0.2 Units V μA V Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 2.5V, +25°C ambient and maximum loading. 2.5V AC Characteristics (Over Operating Range: VDD = 2.5V ± 0.2V, TA = -40° to 85°C) Parameters FIN Input Frequency tR/tF CLKn Rise/Fall Time tSK(P)3. 5 tPLH, tPHL2, 5 tSK(O)3, 5 3, 5 tSK(T) tdc_in 5 tdc_out 5 Test Conditions1 Description Min. Typ Max. Units 250 MHz 1.0 ns 100 200 ps 1.5 2.0 ns 0 20% to 80% Pulse Skew between opposite transitions (tPHL-tPLH) of the same output Vin > VDD CL = 5pF, 125 MHz 1.0 Propagation Delay BUF_IN to CLKn Output to Output Skew between any two outputs of the same device @ same transition 60 Part to Part Skew between two identical outputs of different parts on the same board4 ps CL = 5pF, 125 MHz 300 Duty Cycle In @ Ins edge rate 45 55 Duty Cycle Out 40 57.5 % Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Outputs are measured at VDD/2 09-0084 2 PS8862L 05/01/09 PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer 1.8V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature...........................................................–65°C to +150°C VDD Voltage ..........................................................................–0.5V to +2.5V Output Voltage (max 2.5V) .......................................... –0.5V to VDD+0.5V Input Voltage (max 2.5V) ............................................. –0.5V to VDD+0.5V 1.8V DC Characteristics (Over Operating Range: VDD = 1.8V ± 0.15V, TA = -40° to 85°C) Parameters Test Conditions(1) Description Min. Typ. (2) Max. 1.65 1.8 1.95 VDD Supply Voltage VIH Input HIGH Voltage Logic HIGH level 1.1 2.7 VIL Input LOW Voltage Logic LOW level -0.3 0.35*VDD Input Current(3) II VOH Output High Voltage VOL Output LOW Voltage VDD = Max, Vin = VDD or GND 15 VDD = Min., VIN = VIH or VIL VDD = Min., VIN - VIH or VIL IOH = -2mA 1.35 IOH = -8mA 1.2 IOL = 2mA 0.1 IOL = -8mA 0.2 Units V μA V Notes: 1. For Max. or Min. conditions, use appropriate operating VDD and Ta values. 2. Typical values are at VDD = 1.8V, +25°C ambient and maximum loading. 3. This parameter is determined by device characterization but is not production tested. 1.8V AC Characteristics (Over Operating Range: VDD = 1.8V ± 0.15V, TA = -40° to 85°C) Parameters FIN Input Frequency tR/tF CLKn Rise/Fall Time tSK(P)3. 5 tPLH, tPHL2, 5 tSK(T)3, 5 Part to Part Skew between two identical outputs of different parts on the same board4 tdc_out 5 Typ Max. Units 180 MHz 1.0 ns 100 200 ps 1.5 2.0 ns 20% to 80% Vin > VDD CL = 5pF, 125 MHz 1.0 Propagation Delay BUF_IN to CLKn Output to Output Skew between any two outputs of the same device @ same transition Min. 0 Pulse Skew between opposite transitions (tPHL-tPLH) of the same output tSK(O)3, 5 tdc_in 5 Test Conditions(1) Description 60 ps CL = 5pF, 125 MHz 300 Duty Cycle In @ Ins edge rate 45 55 Duty Cycle Out 40 57.5 % Notes: 1. See test circuit and waveforms 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade.. 5. Outputs are measured at VDD/2 09-0084 3 PS8862L 05/01/09 PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer Power Supply Characteristics Parameters Test Conditions(1) Description IDDQ Quiescent Power Supply Current IDDn Dynamic Power Supply Current per Output IDD_TOT Total Power Supply Current ∆ICC VDD = 2.7V VDD = 1.95V VDD = 2.7V Static Supply Current per inputs @ High Level Typ. (2) Max. 10 VIN = GND or VDD VDD = 1.95V VDD = 2.7V Min. 10 Units μA 1.8 All Outputs Toggling, CL = 5pF, FIN = 125MHz mA 3.5 VDD = 1.95V VIN = VDD or GND, All Outputs Toggling, CL = 5pF, FIN = 125MHz VDD = 2.7V VINx = VDD - 0.6V (3) 500 VDD = 1.95V VINx = VDD - 0.6V (3) 450 48 35 μA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics. 2. Typical values are at VDD = 1.5V, 1.8V or 2.5V, and +25°C ambient. 3. Per TTL driven input (VIN = VDD - 0.6V); all other inputs at VDD or GND. Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. CIN Input Capacitance VIN = 0V 3.0 4 COUT Output Capacitance VOUT = 0V — 6 Note: 1. Units pF This parameter is determined by device characterization but is not production tested. Test Circuits for All Outputs VDD Pulse Generator f = 125MHz 50-Ohm 33-Ohm D.U.T. CL 5pF Definitions: CL = Load capacitance: includes jig and probe capacitance. 09-0084 4 PS8862L 05/01/09 PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer Switching Waveforms Pulse Skew – tSK(P) Propagation Delay VIH Input VDD VDD/2 Input VDD/2 VIL tPLH 0V tPHL VOH Output tPHL tPLH VOH VDD/2 Output VDD/2 VOL tR VOL tF tSK(P) = | tPLH - tPLH | Output Skew – tSK(O) Package Skew – tSK(T) VDD Input VDD VDD/2 Input VDD/2 0V 0V tPHLx tPLHx tPLH1 VOH CLKx VOH VDD/2 Part #1 Output VOL tSK(O) VDD/2 VOL tSK(O) VOH CLKy tSK(T) tSK(T) VOH VDD/2 Part #2 Output VOL tPLHy tPHL1 VDD/2 VOL tPHLy tPLH2 tSK(O) = | tPLHy - tPLHx | or | tPHLy - tPHLx | tSK(T) = | tPLH2 - tPLH1 | 09-0084 tPHL2 5 or | tPHL2 - tPHL1 | PS8862L 05/01/09 PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer Packaging Mechanical: 20-pin, TSSOP (L) DOCUMENT CONTROL NO. PD - 1311 20 REVISION: E DATE: 03/09/05 .169 .177 4.3 4.5 1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 1 .047 1.20 Max .0256 BSC 0.65 .007 .012 0.19 0.30 0.45 0.75 SEATING PLANE .018 .030 .238 .269 6.1 6.7 .002 0.05 .006 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AC DESCRIPTION: 20-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L 09-0084 6 PS8862L 05/01/09 PI6C10807 1.8V/2.5V, 250MHz, 1:10 Networking Clock Buffer Packaging Mechanical: 20-pin, SSOP (H) 1 DATE: 04/10/08 DESCRIPTION: 20-Pin, 209-Mil Wide, SSOP PACKAGE CODE: H20 REVISION: E DOCUMENT CONTROL #: PD-1240 08-0140 Ordering Information(1-3) Ordering Code Package Code Package Type PI6C10807LE L Pb-free & Green, 20-pin 173-mil wide TSSOP PI6C10807HE H Pb-free & Green, 20-pin 209-mil wide SSOP Notes: 1. Thermal Characteristics can be found on the web at www.pericom.com/packaging/ 2. E = Lead-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 09-0084 7 PS8862L 05/01/09