PI6C22409LIEX

PI6C22409 2.5/3.3V 200MHz High-Speed, Low-Jitter, Low-Skew, Zero-Delay Clock Buffer with 9 Outputs Features Description • Phase-Lock Loop Clock Distribution (Zero Input-to-Output Delay) • Internal feedback connection • Distributes one-to-two banks of four outputs w/ one CLKOUT (9 - outputs total) • High-Performance • 30 MHz to 220 MHz operation frequency range • 66MHz, standard drive 15pF load, >66MHz, high drive 30pF load, >66MHz, standard drive 30pF load, >66MHz, high drive time (1) 45 MHz For 3.3V: Measured between 0.8V and 2.0V; @10pF 15pF load, >66MHz, standard drive Period Jitter (Peak) Units 200 30pF load, >66MHz, high drive tPJ Max. 10 15pF load, >66MHz, standard drive tJIT Typ. VDD = 2.5V Measured at VDD/2, 10 pF load Rise Time(1)(4) Fall Time(1)(4) tF Min. Stable power supply, valid clocks presented on CLKOUT pin 100 1 % ns ps ps ps ms Note: 1. See Switching Waveforms 2. All clock output should have the same loading to achieve zero delay between the input and outputs and zero output-to-output skew. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust to input-to-output delay. If input-to-output delay adjustments are needed, the CLKOUT load may be changed to vary the delay between the REF input to the clock outputs. Output-to-output skew includes CLKA1-4 and CLKB1-4. 3. Specifications are guaranteed by design and not production tested. 4. Measured at 100MHz. 5. Measured with 16-Pin SOIC package 13-0019 4 PS9002B 12/12/12 PI6C22409 2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs Switching Waveforms thigh VDD/2 OUTPUT OUTPUT tlow VDD/2 tDC = VDD/2 thigh+ tlow 0V tF tR thigh VDD/2 VDD/2 OUTPUT tSK(O) VDD/2 VDD/2 tSK(D) VDD/2 INPUT VDD/2 OUTPUT t0 0.1µf 0.1µF VDD VDD CLKA,B CLKA,B 0.1µf GND 13-0019 CLOAD VDD 1K 0.1µF GND GND 5 10pF 1K VDD GND PS9002B 12/12/12 PI6C22409 2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs Packaging Mechanical: 16-Pin TSSOP (L) DATE: 05/03/12 Notes: 1. Refer JEDEC MO-153F/AB 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 16-Pin, 173mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1310 REVISION: F 12-0372 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php 13-0019 6 PS9002B 12/12/12 DATE: 06/15 PI6C22409 2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs Packaging Mechanical: 16-Pin SOIC (W) DATE: 06/15/12 DESCRIPTION: 16-Pin, 150mil Wide SOIC PACKAGE CODE: W DOCUMENT CONTROL #: PD-1004 REVISION: F 2012-0398 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information(1,2,3) Ordering Code Package Code Package Type PI6C22409LE L Pb-free & Green, 16-pin TSSOP PI6C22409LIE L Pb-free & Green, 16-pin TSSOP, Industrial temp range PI6C22409WE W Pb-free & Green, 16-pin SOIC PI6C22409WIE W Pb-free & Green, 16-pin SOIC, Industrial temp range Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336  •  www.pericom.com 13-0019 7 PS9002B 12/12/12