PI6C2502WE

PI6C2502 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Phase-Locked Loop Clock Driver Product Features Product Description • High-Performance Phase-Locked-Loop Clock Distribution for Networking, • Synchronous DRAM modules for server/workstation/ PC applications • Allows Clock Input to have Spread Spectrum modulation for EMI reduction • Zero Input-to-Output delay • Low jitter: Cycle-to-Cycle jitter ±100ps max. • On-chip series damping resistor at clock output drivers for low noise and EMI reduction • Operates at 3.3V VCC • Wide range of Clock Frequencies up to 80 MHz • Package (Pb-Free & Green): Plastic 8-pin SOIC Package (W) The PI6C2502 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. Logic Block Diagram Product Pin Configuration CLK_IN Application If a system designer needs more than 16 outputs with the features just described, using two or more zero-delay buffers such as PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-to-device skew introduced can significantly reduce the performance. Pericom recommends the use of a zero-delay buffer and an eighteen output non-zero-delay buffer. As shown in Figure 1, this combination produces a zero-delay buffer with all the signal characteristics of the original zero-delay buffer, but with as many outputs as the non-zero-delay buffer part. For example, when combined with an eighteen output non-zero delay buffer, a system designer can create a seventeen-output zero-delay buffer. AGND CLK_OUT PLL FB_IN FB_OUT AVCC 1 FB_OUT 2 CLK_OUT 3 VCC 4 8-Pin W 8 CLK_IN 7 AVCC 6 GND 5 FB_IN Feedback Reference Clock Signal CLK_OUT 18 Output Non-Zero Delay Buffer V Zero Delay Buffer PI6C2502 17 Figure 1. This Combination Provides Zero-Delay Between the Reference Clocks Signal and 17 Outputs 08-0298 1 PS8382C 11/06/08 PI6C2502 Phase-Locked Loop Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Functions Pin Name Pin Numbe r Type De s cription CLK_IN 8 I Reference Clock input. CLK_IN allows spread spectrum clock input. FB_IN 5 I Feedback input. FB_IN provides the feedback signal to the internal PLL. FB_OUT 2 O Feedback output FB_OUT is dedicated for external feedback. FB_OUT has an embedded series- damping resistor of the same value as the clock outputs CLK_OUT. CLK_OUT 3 O Clock outputs. These outputs provide low- skew copies of CLK_IN. Each output has an embedded series- damping resistor. AVC C 7 Power Analog power supply. AVC C can be also used to bypass the PLL for test purposes. When AVC C is strapped to ground, PLL is bypassed and CLK_IN is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VC C 4 Power Power supply. GND 6 Ground Ground. DC Specifications (Absolute maximum ratings over operating free-air temperature range) Symbol Parame te r VI Input voltage range VO Output voltage range M in. M a x. Units –0.5 VCC +0.5 V IO_DC DC output current 100 mA Power Maximum power dissipation at TA = 55oC in still air 1.0 W TSTG Storage temperature 150 oC –65 Note: Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Parame te r Te s t Conditions ICC VI = VCC or GND; IO = 0(1) CI VI = VCC or GND VCC M in. Typ. 3.6V M ax. Units 10 μA 4 3.3V CO VO =VCC or GND pF 6 Note: 1. Continuous Output Current 08-0298 2 PS8382C 11/06/08 PI6C2502 Phase-Locked Loop Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions Symbol Parame te r M in. M ax. 3.6 VC C Supply voltage 3 .0 VIH High level input voltage 2. 0 VIL Low level input voltage VI Input voltage 0 VC C TA Operating free- air temperature 0 70 Units V 0.8 ºC Electrical Characteristics (Over recommended operating free-air temperature range Pull Up/Down Currents, VCC = 3.0V) Symbol IO H IO L Parame te r Pull- up current Pull- down current Condition M in. M a x. VO U T = 2.4V −18 VO U T = 2.0V − 30 VO U T = 0.8V 25 VO U T = 0.55V 17 Units mA AC Specifications Timing Requirements (Over recommended ranges of supply voltage and operating free-air temperature) Symbol Parame te r M in. M a x. Units FCLK Clock frequency 25 80 MHz DCYI Input clock duty cycle 40 60 % 1 ms Stabilization Time after power up Switching Characteristics (Over recommended ranges of supply voltage and operating free-air temperature, CL=30pF) Parame te r From (Input) To (Output) VC C = 3.3V ±0.3V, 0-70°C M in. Typ. Units M ax. tphase error without jitter CLK_IN↑ at 100MHz and 66MHz FB_IN↑ –150 +150 Jitter, cycle- to- cycle At 100 MHz and 66 MHz CLK_OUT –100 +100 Skew at 100 MHz and 66 MHz CLK_OUT or FB_OUT CLK_OUT or FB_OUT ps Duty cycle 200 45 CLK_OUT or FB_OUT tr, rise- time, 0.4V to 2.0V tf, fall- time, 2.0V to 0.4V 55 % 1.0 ns 1.1 Note: These switching parameters are guaranteed by design. 08-0298 3 PS8382C 11/06/08 PI6C2502 Phase-Locked Loop Clock Driver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Mechanical Information Plastic 8-pin SOIC Package DOCUMENT CONTROL NO. PD - 1001 8 REVISION: F DATE: 03/09/05 .149 .157 3.78 3.99 .0099 .0196 0.25 [Û 0.50 1 .189 .196 4.80 5.00 .0075 .0098 Û 0.19 0.25 0.40 .016 1.27 .050 1 .016 .026 0.406 0.660 .2284 .2440 5.80 6.20 1.35 1.75 .053 .068 SEATING PLANE REF .050 BSC 1.27 .0040 0.10 .0098 0.25 .013 0.330 .020 0.508 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012D/AA DESCRIPTION: 8-Pin, 150-Mil Wide, SOIC PACKAGE CODE: W Ordering Information Orde ring Code Package Name Package Type Ope rating Range PI6C2502WE W8 8- pin 150- mil SOIC, Pb- Free & Green Commercial Notes: 1. Thermal characteristics can be found on the company website at www.pericom.com/packaging/ 2. X = Tape & Reel Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 08-0298 4 PS8382C 11/06/08