PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Features
Description
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The PI6C48543 is a high-performance low-skew LVDS fanout
buffer. PI6C48543 features two selectable differential inputs and
translates to four LVDS outputs. The inputs can also be configured
to single-ended with external resistor bias circuit. The CLK input
accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals,
and PCLK input accepts LVPECL or SSTL or CML signals. The
outputs are synchronized with input clock during asynchronous
assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for
differential to LVDS translations and/or LVDS clock distribution.
Typical clock translation and distribution applications are datacommunications and telecommunications.
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Maximum operation frequency: 800 MHz
4 pair of differential LVDS outputs
Selectable differential CLK and PCLK inputs
CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL
and HCSL input level
PCLK, nPCLK pair supports LVPECL, CML and SSTL
input level
Output Skew: 40ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.2ns (maximum)
3.3V power supply
Pin-to-pin compatible to ICS8543
Operating Temperature: -40oC to 85oC
Packaging (Pb-free & Green):
-20-pin TSSOP (L)
Block Diagram
Pin Diagram
CLK_EN
D
Q
LE
CLK
nCLK
PCLK
nPCLK
0
1
Q1
nQ1
Q2
nQ2
CLK_SEL
OE
08-0247
Q0
nQ0
GND
1
20
Q0
CLK_EN
2
19
nQ0
CLK_SEL
3
18
VCC
Q1
CLK
4
17
nCLK
5
16
nQ1
PCLK
6
15
Q2
nPCLK
7
14
nQ2
OE
8
13
GND
GND
9
12
Q3
VCC
10
11
nQ3
Q3
nQ3
1
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Pin Description
Name
Pin #
Type
1, 9, 13
P
CLK_EN
2
I_PU
Synchronized clock enable. When high, clock outputs follow clock input. When low, Qx
outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 80kΩ pull up.
CLK_
SEL
3
I_PD
Clock select input. When high, selects CLK1 input. When low, selects CLK0 input. LVCMOS/
LVTTL level with 80kΩ pull down.
CLK
4
I_PD
Non-inverting differential clock input
nCLK
5
I_PU
Inverting differential clock input
PCLK
6
I_PD
Non-inverting differential clock input
nPCLK
7
I_PU
Inverting differential clock input
OE
8
I_PU
Output Enable, Controls outputs Q0, nQ0 through Q3, nQ3
VCC
10, 18
P
Connect to 3.3V.
Q3, nQ3
11, 12
O
Differential output pair, LVDS interface level.
Q2, nQ2
14, 15
O
Differential output pair, LVDS interface level.
Q1, nQ1
16, 17
O
Differential output pair, LVDS interface level.
Q0, nQ
19, 20
O
Differential output pair, LVDS interface level.
GND
Description
Connect to Ground
Notes:
1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up
Pin Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
CIN
Input Capacitance
6
R_pullup
Input Pullup Resistance
80
R_pulldown
Input Pulldown Resistance
80
Max.
Units
pF
kΩ
Control Input Function Table
Inputs
Outputs
OE
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
nQ0:nQ3
1
0
0
CLK, nCLK
Diasbled: Low
Diasbled: High
1
0
1
PCLK, nPCLK
Disabled: Low
Disabled: High
1
1
0
CLK, nCLK
Enabled
Enabled
1
1
1
PCLK, nPCLK
Enabled
Enabled
0
x
x
Hi-Z
Hi-Z
Notes:
1.
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below.
08-0247
2
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Figure 1. CLK_EN Timing Diagram
Disabled
Enabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Clock Input Function Table (See Figure 2)
Inputs
CLK or PCLK
Outputs
nCLK
or nPCLK
Q0:Q3
nQ0:nQ3
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
None Inverting
1
0
HIGH
LOW
Differential to Differential
None Inverting
0
Biased; VIN = VCC/2
LOW
HIGH
Single Ended to Differential
None Inverting
1
Biased; VIN = VCC/2
HIGH
LOW
Single Ended to Differential
None Inverting
Biased; VIN =
Vcc/2
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; VIN =
VCC/2
1
LOW
HIGH
Single Ended to Differential
Inverting
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VCC
Supply voltage
Referenced to GND
VIN
Input voltage
Referenced to GND
-0.5
VCC+0.5V
VOUT
Output voltage
Referenced to GND
-0.5
VCC+0.5V
TSTG
Storage temperature
-65
150
4.6
V
oC
Notes:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci
fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
08-0247
3
PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
Operating Conditions
Symbol
VCC
Parameter
Conditions
Power Supply Voltage
TA
Ambient Temperature
ICC
Power Supply Current
Min.
Typ.
Max.
3.135
3.3
3.465
V
85
oC
60
mA
-40
Units
LVCMOS/LVTTL DC Characteristics (TA = -40oC to 85oC, VCC = 3.135V to 3.465V unless otherwise stated below.)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VIH
Input High Voltage
2
3.765
VIL
Input Low Voltage
-0.3
0.8
IIH
Input High
Current
IIL
Input Low
Current
CLK_SEL
VIN = VCC = 3.465V
150
CLK_EN, OE
VIN = VCC = 3.465V
5
CLK_SEL
VIN = 0V, VCC = 3.465V
-5
CLK_EN, OE
VIN = 0V, VCC = 3.465V
-150
Units
V
μA
Differential DC Characteristics (TA = -40oC to 85oC, VCC = 3.135V to 3.465V unless otherwise stated below.)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IIH
Input High
Current
nCLK, nPCLK
VIN = VCC = 3.465V
5
uA
CLK, PCLK
VIN = VCC = 3.465V
150
uA
IIL
Input Low
Current
nCLK, nPCLK
VCC = 3.465V, VIN = 0V
-150
uA
CLK, PCLK
VCC = 3.465V, VIN = 0V
-5
uA
VPP
Peak-to-peak Voltage
0.15
1.3
V
Common Mode Input Voltage(1)
0.5
VCC0.85V
V
VCMR
Notes:
1. For single ended applications, the maximum input voltage for CLK and nCLK is VCC+0.3V
LVPECL DC Characteristics (TA = -40oC to 85oC, VCC = 3.135V to 3.465V unless otherwise stated below.)
Symbol
Parameter
Min.
Typ.
Max.
nCLK, nPCLK
VIN = VCC = 3.465V
5
CLK, PCLK
VIN = VCC = 3.465V
150
nCLK, nPCLK
VCC = 3.465V, VIN = 0V
-150
CLK, PCLK
VCC = 3.465V, VIN = 0V
-5
IIH
Input High
Current
IIL
Input Low
Current
VPP
Peak-to-peak Voltage
VCMR
Conditions
Common Mode Input Voltage;
Note(1)
0.3
1
1.5
VCC
Units
μA
V
Notes:
1. For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC+0.3V.
08-0247
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PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
LVDS DC Characteristics (TA = -40oC to 85oC, VCC = 3.135V to 3.465V unless otherwise stated below.)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
200
280
360
0
40
1.25
1.375
V
5
25
mV
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
IOZ
High Impedance Leakage Current
-10
IOFF
Power OFF Leakage
-20
IOSD
1.125
+10
±1
+20
Differential Output Short Circuit Current
-3.5
-5
IOS
Output Short Circuit Current
-3.5
-5
VOH
Output Voltage High
1.34
1.6
VOL
Output Voltage Low
0.9
Units
mV
μA
mA
V
1.06
AC Characteristics (TA = -40oC to 85oC, VCC = 3.135V to 3.465V)
Symbol
fmax
Parameter
Conditions
Min.
Output Frequency
tPd
Propagation
Tsk(o)
Delay(1)
Output-to-output
f ≤ 800 MHz
1.0
Skew(2)
Part-to-part
tr/tf
Output Rise/Fall time
odc
Output duty cycle
Max.
Units
800
MHz
2.2
ns
40
Skew(3)
Tsk(pp)
Typ.
ps
300
20% - 80%
100
300
48
52
%
Notes:
1. Measured from the differenital input crossing point to the differential output crossing point
2
Skew between outputs with the same supply voltage and equal load conditions. Measured at the differential outputs crossing point.
3. Skew between outputs on different parts operating with the same supply voltage and equal load conditions. Measured at the differential outputs crossing point.
4. All parameters are measured at 500 MHz unless noted otherwise
Applications Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
08-0247
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PS8771B
10/02/08
PI6C48543
3.3V Low Skew 1-to-4, 800MHz,
Differential to LVDS Fanout Buffer
VDD
R1
Single Ended
Clock Input
1K
CLK1
nCLK1
C1
R2
0.1μ
1K
Figure 1: Single-ended Signal Driving Differential Input
Packaging Mechanical: 20-Pin TSSOP (L)
20
.169
.177
4.3
4.5
1
.252
.260
6.4
6.6
.0256
BSC
0.65
.004 0.09
.008 0.20
.047
1.20
Max
.007
.012
0.19
0.30
0.45
0.75
SEATING
PLANE
.018
.030
.238
.269
6.1
6.7
.002 0.05
.006 0.15
Ordering Information
Ordering Code
Package Code
Package Description
PI6C48543LE
L
Pb-free & Green 20-pin 173-mil wide TSSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
08-0247
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PS8771B
10/02/08
