PI6C49021BZDIE

PI6C49021B Low Power High Integration Clock Generator Features Description ÎÎ3.3V supply voltage The new PI6C49021B is a high integration clock generator intended for all kinds of embedded applications and networking application with PCIe interface. The device is the most cost effective way to generate multi-frequencies and multi-outputs clocks from a 25MHz crystal and reference clock. The device can generate 100MHz HCSL clock, single-ended clocks includes 24MHz, 25MHz, 50HMz, 125HMz, and low jitter 25MHz LVPECL clock. ÎÎ25MHz XTAL or reference clock input ÎÎOutput O àà 3 x low power PCIe 2.0 100MHz clock with integrate series termination resistor àà 2 x 66.667MHz LVCMOS clock for CPU àà 1 x 125MHz LVCMOS clock for Gigabit Ethernet àà 2 x 50MHz LVCMOS clock for CPLD àà 3 x 25MHz LVCMOS clock for Ethernet PHY àà 2 x 25MHz low jitter LVPECL Ethernet clock àà 1 x 24MHz LVCMOS for USB PHY ÎÎPackaging (Pb free and Green) BS àà 48-pin TQFN O Block Diagram 25MHz XTAL or clock input X2 PCIE(0-2) T LE X1 3 2 Crystal Oscillator SE_66M(0~1) PLL Clock Synthesis & Control Circuit SE_125M 2 OE_PCIE SE_50M(0~1) OE_PECL 3 E SE_25M(0,2) 2) SE_24M SCLK T SDATA A K All trademarks are property of their respective owners. 2 I 2C Control Circuit 15-0042 PECL_25M(0~1) 1 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator 48 47 46 45 44 43 42 41 40 39 PECL_25M0 PECL_25M0B VDD PECL_25M1 PECL_25M1B VDD VDD PCIE0 PCIE0# VDD PCIE1 PCIE1# Pin Configuration 38 37 GND 1 36 VDD NC 2 35 GND PCIE2 3 34 GND PCIE2# 4 33 SE_125M VDD 5 VDD 6 31 VDD VDD 7 30 GND O 32 GND 8 29 SE_66M1 9 28 VDD SE_50M1 10 27 SE_66M0 GND 11 26 VDD VDD 12 25 SE_24M BS VDD SE_50M0 GND OE_PECL OE_PCIE 23 24 Group Description 5 Power for 66.667MHz PLL 7 Power for 24MHz PLL 31 Power for 125M/50MHz PLL 36 Power for 100MHz PCIe PLL 8 Power for 50MHz outputs 12 Power for 25MHz LVCMOS outputs 21 Power for crystal oscillator 26 Power for 24MHz output 28 Power for 66.667MHz outputs 32 Power for 125MHz output 39, 42 Power for 25MHz differential outputs 43, 46 Power for PCIe clock outputs Pin# Pin Name 1, 6, 11, 24, 30, 34, 35 GND 2 NC 3 PCIE2 Output 4 PCIE2# Output 5, 7, 8, 12, 21, 26, 28, 31, 32, 36, 39, 42, 43, 46 VDD Power 9 SE_50M0 Output 10 SE_50M1 Output 13 SE_25M0 Output 14 SE_25M1 Output T LE O Pin Description VDD 21 22 X2 19 20 X1 NC 17 18 SCLK SDATA 15 16 SE_25M2 SE_25M1 SE_25M0 13 14 Pins 15 SE_25M2 Output 25MHz LVCMOS output 16 SDATA I/O I2C compatible data 17 SCLK Input I2C compatible clock 18 NC 19 X1 Input 20 X2 Output 22 OE_PCIE Input Description Power Ground Do not Connect 100MHz HCSL output 100MHz HCSL output Power supply 50MHz LVCMOS output 50MHz LVCMOS output 25MHz LVCMOS output 25MHz LVCMOS output E All trademarks are property of their respective owners. Type Do not Connect (can be used as RESET# pin, global reset input powers down PLLs plus tri-states outputs and sets the I2C tables to their default state when pulled low.) 15-0042 Crystal input. Connect to 25MHz Fundamental mode crystal or clock. Crystal output. Connect to 25MHz Fundamental mode crystal. Float for clock input. 100MHz HCSL PCIE2 enable pin. Set High to enable. 2 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Pin Name Type Description 23 OE_PECL Input 25MHz LVPECL PECL 25M1 enable pin. Set High to enable. 25 SE_24M Output 24MHz LVCMOS output 27 SE_66M0 Output 66.667MHz LVCMOS output 29 SE_66M1 Output 66.667MHz LVCMOS output 33 SE_125M Output 125MHz LVCMOS output 37 PECL_25M0 Output 25MHz differential output 38 PECL_25M0# Output 25MHz differential output 40 PECL_25M1 Output 25MHz differential output 41 PECL_25M1# Output 25MHz differential output 44 PCIE0 Output 100MHz HCSL output PCIE0# Output 100MHz HCSL output PCIE1 Output 100MHz HCSL output PCIE1# Output 100MHz HCSL output O Pin# 47 48 BS 45 Notes: VDD and GND Pins Layout Guide 1. Small value decoupling caps. (0.1uF, 1uF, and 2.2uF) should be placed close each VDD pin or its via 2. Connect all GND pins to package thermal pad which must be connected to the GND plane for better thermal distribution and signal conducting with reason- O able via count (>8) Selection Table – PCIE2 / PECL_25M1 Output Control PCIE2 Status 1 Enable PCIE2 output (Default) 0 Disable PCIE2 output, Tristate OE_PECL PECL_25M1 Status 1 Enable PECL_25M1 output (Default) 0 Disable PECL_25M1 output, Tristate E T LE OE_PCIE All trademarks are property of their respective owners. 15-0042 3 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Serial Data Interface (SMBus) This part is a slave only device that supports block read and block write protocol using a single 7-bit address and read/write bit as shown below. Read and write block transfers can be stopped after any complete byte teansfer by issuing STOP. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 O How to Write 8 bits 1 8 bits 1 8 bits 1 8 bits 1 Start bit D2H Ack Register offset Ack Byte Count = N Ack Data Byte 0 Ack BS 1 bit … 8 bits 1 1 bit Data Byte N-1 Ack Stop bit Note: 1.Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock) 1 bit M: Send "D2h" 1 bit S: sends Ack 8 bits M: send starting databyte location: N 1 bit 1 bit S: sends Ack M: Start bit Description 7 OE for SE_66M0 6 1 bit 8 bits S: sends # of data bytes that will be sent: X M: Send "D3h" S: sends Ack 1 bit 8 bits M: sends Ack S: sends starting data byte N 1 bit M: sends Ack … 8 bits 1 bit 1 bit … S: sends data byte N+X1 M: Not Acknowledge M: Stop bit T LE Byte 0: Spread Spectrum Control Register Bit 8 bits O M: Start bit 8 bits Power Up Condition Output(s) Affected RW 1 SE_66M0 output RW 0 RW 1 All outputs Notes 0 = disabled 1 = enabled 0 = hardware cntl 1 = software ctrl 4 Reserved R Undefined E Enable hardware or software control of OE bits (see Byte 0-Bit 6 and Bit 5 Functionality table) Software RESET# bit. Enablea or disables all outputs. (see Byte 0-Bit 6 and Bit 5 Functionality table) Type 3 2 Reserved Reserved R R Undefined Undefined Not applicable 1 Reserved R Undefined 0 OE for SE_66M1 RW 1 5 All trademarks are property of their respective owners. 15-0042 4 All outputs SE_66M1 output 0 = disabled 1 = enabled 0 = disabled 1 = enabled www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Byte 0: Bit 6 and Bit 5 Functionality Bit Bit 5 Description 0 X 1 0 1 1 RESET# = "H" will enable all outputs; SMBus can not control each output. Disable all outputs and tri-states the outputs. When pin 18 (RESET#) is set low, force device to power-on reset and set all registers to default values. Enable outputs according to the SMBus default values; SMBus can control each output. When pin 18 (RESET#) is set low, force to power-on reset and set all registers to default values. O Byte 1: Control Register Description Type Power Up CondiOutput(s) Affected tion 7 OE for SE_125M RW 1 SE_125M 6 OE for SE_50M0 RW 1 SE_50M0 5 OE for SE_50M1 RW 1 SE_50M1 4 OE for SE_25M0 RW 1 SE_25M0 3 OE for SE_25M1 2 OE for SE_24M 1, 0 Reserved O BS Bit 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 1 SE_25M1 RW 1 SE_24M Undefined Not Applicable T LE RW Byte 2: Control Register Notes Bit Description Type Power Up CondiOutput(s) Affected tion 7 to 0 Reserved R Undefined Notes Not Applicable E All trademarks are property of their respective owners. 15-0042 5 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Byte 3: Control Register Bit Description Type Power Up Condition Output(s) Affected 7 Reserved RW Undefined Not Applicable 6 OE for PECL_25M0 RW 1 PECL_25M0 5 OE for PECL_25M1 RW 1 PECL_25M1 O OE for SE_25M2 RW 1 SE_25M2 3 OE for PCIE2 RW 1 PCIE2 2 OE for PCIE1 RW 1 PCIE1 1 OE for PCIE0 RW 1 PCIE0 0 Reserved R Undefined Not Applicable BS 4 Notes 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled 0 = disabled 1 = enabled Byte 4 & 5: Control Register Description 7 to 0 Reserved Power Up CondiOutput(s) Affected tion R Undefined Not Applicable Description Type Power Up CondiOutput(s) Affected tion 7 Revivsion ID bit 3 R 0 Not Applicable 6 Revivsion ID bit 2 R 0 Not Applicable 5 4 3 2 1 0 Revivsion ID bit 1 Revivsion ID bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0 R R R R R R 0 1 0 0 1 1 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable 15-0042 Notes E Bit All trademarks are property of their respective owners. Notes T LE Byte 6: Control Register Type O Bit 6 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential ......................................................4.6V All inputs and Output ...................................................-0.5V to VDD +0.5V Ambient Operating Temperature....................................... –40°C to +85°C Storage Temperature........................................................... –65°C to +150°C Juction Temperature.............................................................................. 125°C O Soldering Temperature.......................................................................... 260°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ESD Protection (Input).......................................................... 2000V (HBM) DC Electrical Characteristics BS Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature -40°C to +85°C Symbol Parameter Conditions Min VDD Operating Supply Voltage 3.135 3.465 VIH Input High Voltage 2 VDD+0.3 VIL Input Low Voltage –0.3 0.8 VIH Input High Voltage SCLK,SDATA 0.7VDD VDD VIL Input Low Voltage SCLK,SDATA IDD Operating Supply Current CIN Input Capacitance Max Units V O 0.3VDD 197 All input pins 230 mA 6 pF T LE Electrical Characteristics - Single-Ended Typ Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature -40°C to +85°C Symbol Parameter Conditions FIN Input Clock Frequency FT Frequency Stability 25MHz XTAL ±50 ppm Ferror Frequency Synthesis Error 24MHz, 25MHz, 50MHz, 66.667MHz, 125MHz output 0 ppm 100 400 kHz 1 1.5 ns 1.2 ns 20% to 80% 24MHz, 25MHz, 50MHz, 66.667MHz output 0.6V to 2.7V 125MHz output Output Clock Duty Cycle Measured at VDD/2 24MHz, 25MHz, 50MHz, 66.667MHz output 45 Measured at VDD/2, 125MHz 47 50 50 High-Level Output Voltage IOH = -4mA VDD-0.4 VOH High-Level Output Voltage IOH = -8mA 2.4 VOL Low-Level Output Voltage IOL = 8mA 15-0042 MHz 55 53 0.4 7 Units % VOH All trademarks are property of their respective owners. Max E Output Rise/Fall Time Typ 25 SCLK Frequency tr, tf Min V www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Symbol Parameter Conditions RMS phase jitter 25MHz clock output, Fj=1kHz to 5MHz offset frequency Peak-to-Peak Jitter Min Typ Max Units 3 ps 125MHz clock output ±150 66.667MHz clock output ±150 50MHz clock output 250 O Clock Stabilization Time from Power Up 3 ps 6 ms Max Units Output Frequency 100 MHz Cycle-to-Cycle Jitter 150 Electrical Characteristics - 100MHz Differential HCSL Outputs Symbol TCC/Jitter BS Unless otherwise specified, VDD=3.3V±5%, Ambient Temperature -40°C to +85°C Parameter Conditions Min Typ Using PCIe jitter measurement method 86 JRMS2.0 PCIe 2.0 RMS Phase Jitter PCIe 2.0 Test Method @ 100MHz Output 3.1 JRMS RMS Phase Noise Jitter Phase Noise Jitter Test Method @ 12kHz~20MHz TDC Duty Cycle O Peak-to-Peak Phase Jitter Falling Edge Rate 3,4 TOSKEW Output Skew VOH High-Level Output Voltage VOL Low-Level Output Voltage VCROSS Absolute Crossing Point Voltage2,5,6 VCROSS Delta Variation of VCROSS over all rising clock edges2,5,8 TPERIOD AVG Average Clock Period Accuracy3,9,10 TPERIOD ABS Absolute Period (including jitter and spread spectrum)3,7 45 50 RS=33-Ohm ps % 0.6 4.0 V/ns 0.6 4.0 V/ns 75 ps VT = 50%(measurement threshold) 2 ps 55 T LE Rising Edge Rate 3,4 10 ps 0.65 0.71 0.85 –0.20 0 0.05 0.25 V 0.55 V 140 mV E Notes: –300 2800 ppm 9.847 10.203 ns 1. Measured at the end of an 8-inch trace with a 5pF load. 2. Measurement taken from a single-ended waveform. 3. Measurement taken from a differential waveform. 4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. 5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the falling edge 100M–. 6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, All trademarks are property of their respective owners. 15-0042 8 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator and spread spectrum modulation. 8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–. 9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding PPM considerations. 10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz. The period is measured with a frequency counter with measurement window set at 100 ms or greater. With spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an additional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread. Electrical Characteristics - 25MHz LVPECL outputs Parameter Min Typ Max Unit TPERIOD Cycle Time - 40 - ns TDC Duty Cycle 45 - 55 % tr, tf Rise/Fall Time (20%-80%) 0.3 - 0.6 ns RMS Jitter (12kHz-5 MHz) - - 2 (spur off) ps-RMS Clock Tolerance (25MHz) -50 - +50 ppm Output High Voltage VDD-1.4 VDD-0.9 Output Low Voltage VDD-2.0 VDD-1.7 Peak to Peak Output Voltage Swing 0.6 1.0 O Symbol VOH VOL Vswing V O BS JRMS E T LE All trademarks are property of their respective owners. 15-0042 9 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Application Notes Crystal circuit connection The following diagram shows PI6C49021B crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 27pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit O XTAL_IN C1 27pF SaRonix-eCera FL2500047 BS Crystal�(CL�=�18pF) XTAL_OUT C2 27pF O ASIC X1 X2 Cj Cj = chip in/output cap. (3~5pF) T LE Cj CL= crystal spec. loading cap. Cb = PCB trace/via cap. (2~4pF) Cb Rf C1 Pseudo sine C1,2 = load cap. components Rd Cb Rd = drive level res. (100Ω) C2 Final choose/trim C1=C2=2 *CL - (Cb +Cj) for the target +/-ppm Example: C1=C2=2*(18pF) – (4pF+5pF)=27pF E Recommended Crystal Specification Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf All trademarks are property of their respective owners. 15-0042 10 www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Configuration test load board termination for HCSL Outputs Rs 33Ω 5% PI6C49021B Clock TLA Rs 33Ω 5% Clock# O TLB 2pF 5% 2pF 5% BS Figure 4. Configuration Test Load Board Termination O VDD T LE Zo = 50Ω L = 0 ~ 18 in. 100Ω Zo = 50Ω 150Ω 150Ω All trademarks are property of their respective owners. 15-0042 11 E Figure 5. LVPECL output termination www.pericom.com 03/31/15 PI6C49021B Low Power High Integration Clock Generator Packaging Mechanical: 48-Contact TQFN (ZD) O BS 1 O 12-0458 T LE Notes: 1. All dimensions are in millimeters, angles are in degrees. 2. Refer JEDEC MO-220/VKKD 3. Thermal Pad Soldering Area 4. Depending on the method of lead termination at the edge of the package, pull back maybe present. DATE: 05 3/09/12 4 DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD (ZD48) DOCUMENT CONTROL #: PD-2045 REVISION: E Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php E Ordering Information(1-3) Ordering Code Package Code PI6C49021BZDIE Package Description ZD 48-contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336  •  www.pericom.com All trademarks are property of their respective owners. 15-0042 12 www.pericom.com 03/31/15