PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Features
Description
ÎÎ25MHz crystal or reference clock input
The PI6CFGL401B is an 4-output very low power clock generator for PCIe Gen1-2-3 applications with integrated output terminations providing Zo=100Ω. The device has 4 output enables
for clock management and supports 2 different spread spectrum
levels in addition to spread off. The device also has one 1.8V
LVCMOS REF output.
ÎÎ100MHz low power HCSL or LVDS compatible outputs
ÎÎPCIe 3.0, 2.0 and 1.0 compliant
ÎÎSelectable spread spectrum of -0.25%, -0.5% and no spread
ÎÎProgrammable output amplitude and slew rate
ÎÎCycle-to-cycle jitter (typ.) ~ 30ps
ÎÎSupply voltage of 3.3V+/-10%
Application
ÎÎOutput supply voltage of 1.8V
PCIe Gen1-2-3 clock generator
ÎÎIndustrial ambient operating temperature
ÎÎAvailable in lead-free package:
32-TQFN
Block Diagram
XTAL_IN or Ref CLK
REF1.8
OSC
XTAL_OUT
-
OE(3:0)#
I
4
+
SS Capable PLL
t
+
CLK(3:0)
u
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
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CONTROL
LOGIC
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
VDDO1.8
GND
CLK3
OE3#
CLK3#
CKPWRGD_PD#
GND
SS_EN_tri
Pin Configuration (32-Pin TQFN)
32 31 30 29 28 27 26 25
GNDXTAL 1
XTAL_IN 2
24 OE2#
23 CLK2#
XTAL_OUT 3
22 CLK2
VDDXTAL 4
21 VDDA3.3
VDDREF1.8 5
SADR/REF1.8
20 GNDA
6
19 CLK1#
GNDREF 7
18 CLK1
17 OE1#
VDDO1.8
GND
CLK0#
OE0#
CLK0
SCLK_3.3
SDATA_3.3
9 10 11 12 13 14 15 16
VDDDIG3.3
GNDDIG 8
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
Power Connections
SADR
Address
+ Read/Write Bit
Pin Number
0
1101000
1/0
VDD
GND
1
1101010
1/0
4
1
XTAL Analog
5
7
REF Output
9
8, 30
Digital Power
16, 25
15, 26
DIF outputs
21
20
PLL Analog
Description
Power Management Table
CLKx
CKPWRGD_PD#
SMBus OE bit
0
x
Low
Low
Hi-Z1
1
1
Running
Running
Running
1
0
Low
Low
Low
True O/P
REF1.8
Comp. O/P
Note:
1. REF1.8 is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF1.8 is Low.
CLKx
CKPWRGD_PD#
OE (Pin)
OE (SMBus bit)
0
X
x
Low
Low
1
0
0
Low
Low
1
0
1
Running
Running
1
1
0
Low
Low
1
1
1
Low
Low
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15-0072
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True O/P
Comp. O/P
www.pericom.com 06/05/15
PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Pin Description
Pin#
Pin Name
Type
Description
1
GNDXTAL
Power
GND for XTAL
2
XTAL_IN
Input
Crystal input or Reference Clock input. Nominally 25MHz.
3
XTAL_OUT
Output
Crystal output.
4
VDDXTAL
Power
3.3 Power supply for XTAL.
5
VDDREF1.8
Power
VDD for REF output. nominal 1.8V.
6
SADR/REF1.8
Input/Output
Latch to select SMBus Address/1.8V LVCMOS Ref output.
7
GNDREF
Power
Ground pin for the REF outputs.
8
GNDDIG
Power
Ground pin for digital circuitry.
9
VDDDIG3.3
Power
3.3V digital power (dirty power)
10
SCLK_3.3
Input
Clock pin of SMBus circuitry, 3.3V tolerant.
11
SDATA_3.3
Input/Output
Data pin for SMBus circuitry, 3.3V tolerant.
12
OE0#
Input
13
CLK0
Output
Differential true clock output
14
CLK0#
Output
Differential Complementary clock output
15
GND
Power
Ground pin.
16
VDDO1.8
Power
Power supply for outputs, nominally 1.8V, range 1.05V~3.3V.
17
OE1#
Input
18
CLK1
Output
Differential true clock output
19
CLK1#
Output
Differential Complementary clock output
20
GNDA
Power
Ground pin for the PLL core.
21
VDDA3.3
Power
3.3V power for the PLL core.
22
CLK2
Output
Differential true clock output.
23
CLK2#
Output
Differential Complementary clock output.
24
OE2#
Input
25
VDDO1.8
Power
Power supply for outputs, nominally 1.8V, range 1.05V~3.3V.
26
GND
Power
Ground pin.
27
CLK3
Output
Differential true clock output
28
CLK3#
Output
Differential Complementary clock output
29
OE3#
Input
30
GND
Power
Ground pin.
31
CKPWRGD_
PD#
Input
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal pull-up resistor.
32
SS_EN_tri
Input
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Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply Voltage to Ground Potential.......................................................4.6V
All Inputs and Output......................................................-0.5V toVDD+0.5V
Ambient Operating Temperature............................................ -40 to +85°C
Storage Temperature........................................................... –65°C to +150°C
Junction Temperature........................................................................... 125°C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Soldering Temperature.......................................................................... 260°C
ESD Protection (Input)............................................................2000V(HBM)
Electrical Characteristics–Current Consumption
(TA = -40~85oC; VDD = 3.3V +/- 10%; VDDO = 1.8V +/- 10%, See Test Loads for Loading Conditions)
Symbol
IDDAOP
IDDOP
Parameters
Condition
Operating Supply Current
1
Min.
Type
Max.
Units
VDDA3.3, All outputs active @100MHz
40
mA
Total power consumption, All outputs active
@100MHz
53
mA
IDDSUSP
Suspend Supply Current1
VDDREF1.8, CKPWRGD_PD# = 0, Wake-OnLAN enabled
8
mA
IDDPD
Powerdown Current1,2
CKPWRGD_PD#=0
1.3
mA
Max.
Units
55
%
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Assuming REF is not running in power down state.
Electrical Characteristics–Differential Output Duty Cycle, Jitter, and Skew
Characterisitics
(TA = -40~85oC; VDD = 3.3V +/- 10%; VDDO = 1.8V +/- 10%, See Test Loads for Loading Conditions)
Symbol
Parameters
tDC
Duty Cycle1
tsk3
Skew, Output to Output
VT = 50%
50
ps
tjcyc-cyc
Jitter, Cycle to cycle1
PLL mode
50
ps
1
Condition
Min.
Measured differentially, PLL Mode
45
Type
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform.
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
(TA = -40~85oC; VDD = 3.3V +/- 10%; VDDO = 1.8V +/- 10%, See Test Loads for Loading Conditions)
Symbol
Parameters
VDDX
VDDO
TA
Condition
Min.
Type
Max.
Units
Supply Voltage1
Supply voltage for core, analog
3.0
3.3
3.6
V
Supply Voltage
Supply voltage outputs
1.05
1.8
3.3
V
-40
25
85
°C
1
Ambient Operating
Temperature1
VIH
Input High Voltage1
Single-ended inputs, except SMBus, SS_EN_tri
0.65 VDD
VDD +0.3
V
VIM
Input Mid Voltage
SS_EN_tri
0.4 VDD
0.6 VDD
V
VIL
Input Low Voltage
Single-ended inputs, except SMBus, SS_EN_tri
-0.3
0.35 VDD
V
Single-ended inputs, except SS_EN_tri
0.5 VDD
0.6 VDD
V
Single-ended inputs, except SS_EN_tri
0.4 VDD
0.5 VDD
V
0.2 VDD
V
VT+
VT-
1
1
Schmitt Trigger Postive
Going Threshold Voltage1
Schmitt Trigger Negative
Going Threshold Voltage1
VH
Hysteresis Voltage1
VT+ - VT-
0.05 VDD
VOH
Output High Voltage1
Single-ended outputs, except SMBus. IOH =
-2mA
VDD
-0.45
VOL
Outputt Low Voltage1
Single-ended outputs, except SMBus. IOL =
-2mA
Single-ended inputs, VIN = GND, VIN = VDD
(exclude XTAL_IN pin)
IIN
VIN = 0 V; Inputs with internal pull-up resistors
IINP
VIN = VDD; Inputs with internal pull-down
resistors
fin
Input Frequency1
Lpin
Pin Inductance
Cout
0.45
V
-5
5
uA
-200
200
uA
26
MHz
7
nH
5
pF
6
pF
0.6
1
ms
31.500
33
kHz
3
clocks
300
us
Single-ended inputs
Input Current1
CIN
V
XTAL, or XTAL_IN
23
25
1
Capacitance1
tSTAB
Clock output Stabilization1, 2
f MODIN
Input SS Modulation
Frequency1
tLATOE#
OE# Latency1, 3
tDRVPD
Tdrive_PD#1, 3
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Control Inputs
1.5
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of CKPWRGD_
PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
CLK start after OE# assertion
CLK stop after OE# deassertion
CLK output enable after
CKPWRGD_PD# de-assertion
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions Cont...
Symbol
Parameters
Condition
tF
Fall time1, 2
tR
Rise time
VILSMB
SMBus Input Low Voltage
VIHSMB
SMBus Input High Voltage
VOLSMB
SMBus Output Low Voltage
@ IPULLUP
IPULLUP
SMBus Sink Current
@ VOL
4
VDDSMB
Nominal Bus Voltage
3.3V bus voltage
2.7
tRSMB
SCLK/SDATA Rise Time1
tFSMB
SCLK/SDATA Fall Time1
f MAXSMB
1, 2
Min.
Type
Max.
Units
Control inputs
5
ns
Control inputs
5
ns
0.8
V
3.6
V
0.4
V
1
2.1
1
1
1
1
SMBus Operating
Frequency1, 5
mA
3.6
V
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
Maximum SMBus operating frequency
400
kHz
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance
3. Time from deassertion until outputs are >200 mV
4. The differential input clock must be running for the SMBus to be active
Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs
(TA = -40~85oC; VDD = 3.3V +/- 10%; VDDO = 1.8V +/- 10%, See Test Loads for Loading Conditions)
Symbol
Parameters
trf
Slew rate1, 2, 3
Δtrf
Slew rate matching
Slew rate matching, Scope averaging on
VOH
Voltage High
VOL
Voltage Low1, 7
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Vmax
Max Voltage1
Measurement on single ended signal using
Vmin
Min Voltage1
absolute value. (Scope averaging off)
-300
mV
Vswing
Vswing
Scope averaging off
300
mV
5, 7
Scope averaging off
250
Crossing Voltage (var)1, 6
Scope averaging off
Vcross_abs
Δ-Vcross
1, 2, 4
1, 7
1, 2, 7
Crossing Voltage (abs)
1,
Condition
Min.
Type
Max.
Units
Scope averaging on 1.5V/ns setting
0.7
1.4
1.9
V/ns
Scope averaging on 3.0V/ns setting
1.6
2.9
4
V/ns
20
%
550
850
mV
-150
150
mV
1150
mV
550
mV
140
mV
Note:
1. Guaranteed by design and characterization, not 100% tested in production.
2. Measured from differential waveform
3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.
4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point
where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is
to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7. At default SMBus settings.
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Electrical Characteristics–Phase Jitter Parameters
(TA = -40~85oC; VDD = 3.3V +/- 10%; VDDO = 1.8V +/- 10%, See Test Loads for Loading Conditions)
Symbol
Parameters
Condition
tjphPCIeG11, 2, 3, 5
Min.
PCIe Gen 1
PCIe Gen 2 Low Band
tjphPCIeG21, 2, 5
10kHz < f < 1.5MHz
Phase Jitter, PCI
Express
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
tjphPCIeG31, 2, 4, 5
(PLL BW of 2-4MHz, CDR = 10MHz)
Type
INDUSTRY LIMIT
30
86
0.5
3
2.2
3.1
0.46
1
Units
ps
(p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs.
3. Sample size of at least 100k cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4. Calculated from Intel-supplied Clock Jitter Tool.
5. Applies to all different outputs.
Electrical Characteristics–REF1.8
(TA = -40~85oC; VDD = 3.3V +/- 10%; VDDO = 1.8V +/- 10%, See Test Loads for Loading Conditions)
Symbol
Parameters
Condition
ppm
Long Accuracy
Tperiod
Clock period
trf1
Rise/Fall Slew Rate
VOH = VDD-0.45V, VOL = 0.45V
0.5
2.5
V/ns
tDC
1, 4
Duty Cycle
VT = VDDO/2 V
45
55
%
tDCD
Duty Cycle Distortion1, 5
VT = VDDO/2 V
0
3
%
tjc-c
Jitter, cycle to cycle1, 4
VT = VDDO/2 V
50
ps
tjdBc1k
Noise floor1, 4
1kHz offset
-141
-120
dBc
tjdBc10k
Noise floor1, 4
10kHz offset to Nyquist
-150
-130
dBc
tjphREF
Jitter, phase1, 4
12kHz to 5MHz
0.46
1
1, 2
1, 2
1, 3
Min.
Type
Max.
Units
see Tperiod min-max values
0
ppm
25 MHz output nominal
40
ns
ps
(rms)
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF1.8 is trimmed to 25.00 MHz.
3. Typical value occurs when REF1.8 slew rate is set to default value.
4. When driven by a crystal.
5. When driven by an external oscillator via the XTAL_IN pin. XTALK_OUT should be floating in this case.
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100Ω
Rs
2pF
2pF
Device
REF1.8 Output Test Load
RO
Zo = 50 Ω
22
5pF
REF1.8 Output
Alternate Terminations
R
3.3V
Driving LVDS
R7a
R7b
R8a
R8b
Cc
Rs
Rs
Zo
Cc
Device
LVDS Clock
input
RO
Driving LVDS inputs with the PI6CFGL401B
Value
Component
Receiver has termination
Receiver does not have termination
R7a, R7b
10K Ω
140 Ω
R8a, R8b
5.6K Ω
75 Ω
Cc
0.1 uF
0.1 uF
1.2 volts
1.2 volts
Vcm
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Serial Data Interface (SMBus)
This part is a slave only device that supports blocks read and block write protocol using a single 7-bit address and read/write bit as
shown below.
Read and write block transfers can be stopped after any complete byte transfer by issuing STOP.
Address Assignment
Refer to SMBus Address Selection Table.
Data Protocol
(Write)
1 bit
Start bit
8 bits
1
Slave
Ack
Addr: D4
8 bits
1
8 bits
Register
Ack
offset
1
Byte
Ack
Count=N
8 bits
1
Data
Byte 0
Ack
8 bits
1
1 bit
Data
Ack
Byte N-1
…
Stop bit
(Read)
1 bit
Start
bit
8
bits
1
Slave
Addr: Ack
D4
8 bits
1
Register
Ack
offset
1
8
bits
1
8 bits
Slave
Repeat
Addr: Ack
start
D5
Byte
Count=N
1
Ack
8
bits
8
bits
1
Data
Ack
Byte 0
…
Data
Byte
N-1
1
NOT
Ack
1
bit
Stop
bit
Note:
1.Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
SMBus Table: Output Enable Register
BYTE 0
Bit
Name
Control Function
Type
0
1
Default
7
Reserved
1
6
Reserved
1
5
Reserved
1
4
Reserved
1
3
OE3
Output Enable
RW
Low
Enabled
1
2
OE3
Output Enable
RW
Low
Enabled
1
1
OE2
Output Enable
RW
Low
Enabled
1
0
OE0
Output Enable
RW
Low
Enabled
1
SMBus Table: SS Readback and Vhigh Control Register
BYTE 1
Bit
Name
Control Function
Type
0
7
SSENRB1
SS Enable Readback Bit1
R
6
SSENRB0
SS Enable Readback Bit0
R
00' for SS_EN_tri = 0, '01' for SS_EN_tri = 'M', Latch
'11 for SS_EN_tri = '1'
Latch
5
SSEN_SWCNTRL Enable SW control of SS
RW
SS control locked
4
SSENSW1
SS Enable Software Ctl Bit1
RW1
00' = SS Off, '01' = -0.25% SS,
0
3
SSENSW0
SS Enable Software Ctl Bit0
RW
'10' = Reserved, '11'= -0.5% SS
0
2
Reserved
1
AMPLITUDE 1
0
AMPLITUDE 0
1
1
Default
Values in B1[4:3]
control SS amount.
0
1
Controls Output Amplitude
RW
00 = 0.6V
01 = 0.7V
1
RW
10= 0.8V
11 = 0.9V
0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: CLK Slew Rate Control Register
BYTE 2
Bit
Name
Control Function
7
Reserved
1
6
Reserved
1
5
Reserved
1
4
Reserved
1
3
SLEWRATESEL CLK3
Adjust Slew Rate of CLK3
RW
2.0V/ns
3.0V/ns
1
2
SLEWRATESEL CLK2
Adjust Slew Rate of CLK2
RW
2.0V/ns
3.0V/ns
1
1
SLEWRATESEL CLK1
Adjust Slew Rate of CLK1
RW
2.0V/ns
3.0V/ns
1
0
SLEWRATESEL CLK0
Adjust Slew Rate of CLK0
RW
2.0V/ns
3.0V/ns
1
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15-0072
Type
10
0
1
Default
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
SMBus Table: REF Control Register
BYTE 3
Bit
Name
Control Function
REF 1.8
Slew Rate Control
5
REF 1.8 Power Down
Function
Wake-on-Lan Enable for REF 1.8 RW
REF 1.8 does not run REF 1.8 runs in
in Power Down
Power Down
0
4
REF 1.8 OE
REF 1.8 Output Enable
Low
1
3
Reserved
1
2
Reserved
1
1
Reserved
1
0
Reserved
1
7
6
Type
0
1
Default
RW
00 = 0.9V/ns
01 =1.3V/ns
0
RW
10 = 1.6V/ns
11 = 1.8V/ns
1
RW
Enabled
Byte 4 is reserved and reads back 'hFF'.
SMBus Table: Revision and Vendor ID Register
BYTE 5
Bit
Name
Control Function
Type
0
7
RID3
6
RID2
5
RID1
4
RID0
R
0
3
VID3
R
0
2
VID2
R
0
1
VID1
R
0
0
VID0
R
0
R
R
Revision ID
R
VENDOR ID
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11
1
Default
0
A rev = 0000
0
0
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PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
SMBus Table: Device Type/Device ID
BYTE 6
Bit
Name
Control Function
7
Device Type1
6
Device Type0
5
Device ID5
R
0
4
Device ID4
R
0
3
Device ID3
2
Device ID2
1
Device ID1
R
0
0
Device ID0
R
0
Device Type
Type
0
R
00 = FGV, 01 = DBV,
0
R
10 = DMV, 11= Reserved
0
R
Device ID
R
1
000100 binary or 04 hex
Default
0
1
SMBus Table: Byte Count Register
BYTE 7
Bit
Name
Control Function
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
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15-0072
Type
12
0
1
Default
www.pericom.com 06/05/15
PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Application Notes
Crystal circuit connection
The following diagram shows crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1=
27pF, C2= 27pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
27pF
SaRonix-eCera
FL2500047
Crystal�(CL�=�18pF)
XTAL_OUT
C2
27pF
ASIC
X1
CL= crystal spec. loading cap.
X2
Cj
Cj = chip in/output cap. (3~5pF)
Cj
Cb = PCB trace/via cap. (2~4pF)
Cb
Rf
Pseudo
sine
C1
C1,2 = load cap. components
Rd
Cb
Rd = drive level res. (100Ω)
C2
Final choose/trim C1=C2=2 *CL - (Cb +Cj) for the target +/-ppm
Example: C1=C2=2*(18pF) – (4pF+5pF)=27pF
Recommended Crystal Specification
Pericom recommends:
a) FL2500047, SMD 3.2X2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf
b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
Thermal Characteristics
Symbol
Parameters
Condition
θJA
Thermal Resistance Junction to Ambient
Still air
θJA
Thermal Resistance Junction to Case
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15-0072
13
Min.
Type
Max.
Units
44.7
o
C/W
21.7
o
C/W
www.pericom.com 06/05/15
PI6CFGL401B
4-Output Low Power PCIE Gen 1-2-3 Clock Generator
Packaging Mechanical: 32-Pin TQFN (ZH)
Notes:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area (mesh stencile design is recommended)
DATE: 06/30/11
DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZH32
DOCUMENT CONTROL #: PD-2070
REVISION: B
11-0147
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
Description
PI6CFGL401BZHIE
ZH
32-contact, Thin Quad Flat No-Lead (TQFN)
PI6CFGL401BZHIEX
ZH
32-contact, Thin Quad Flat No-Lead (TQFN), Tape & Reel
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336
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15-0072
14
www.pericom.com 06/05/15
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