PI6CV857LAE

PI6CV857L 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features Product Description • PLL clock distribution optimized for Double Data Rate SDRAM applications. • Distributes one differential clock input pair to ten differential clock output pairs. • Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 • Input PWRDWN: LVCMOS • Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 • External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. • Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers • Packages (Pb-free & Green Available): - Plastic 48-pin TSSOP PI6CV857L PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN) and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CV857L clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). The PI6CV857L is also able to track Spread Spectrum Clocking for reduced EMI. Block Diagram/Pin Configuration GND Y0 Y0 VD D Q Y1 Y1 GND GND Y2 Y2 VD D Q VD D Q CLK CLK VD D Q AV D D AGND GND Y3 Y3 VD D Q Y4 Y4 GND Y0 Y0 Y1 CLK CLK FBIN PLL FBIN Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 PWRDWN AVDD Powerdown and Test Logic Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT 09-0025 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 48-Pin 39 A 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Y5 Y5 VD D Q Y6 Y6 GND GND Y7 Y7 VD D Q PWRDWN FBIN FBIN VD D Q FBOUT FBOUT GND Y8 Y8 VD D Q Y9 Y9 GND PS8543D 08/17/09 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pinout Table Pin Name Pin No. I/O Type CLK CLK 13 14 I Yx 3,5,10,20,22,27,29,39,44,46 Yx 2,6,9,19,23,26,30,40,43,47 FBOUT FBOUT 32 33 Feedback output, and Complement Feedback Output FBIN FBIN 36 35 Feedback Input, and Complement Feedback Input Reference Clock input Clock outputs. Complement Clock outputs. O Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs are disabled to a 3- state. When PWRDWN = 1, all differential clock outputs are enabled and run at the same frequency as CLK. I PWRDWN 37 VDDQ 4,11,12,15,21,28,34,38,45 AVDD 16 AGND 17 GND 1,7,8,18,24,25,31,41,42,48 De s cription Power Supply for I/O. Power Ground Analog /core power supply. AVDD can be used to bypass the PLL for testing purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog/core ground. Provides the ground reference for the analog/core circuitry Ground Function Table Inputs Outputs PLL AVDD PWRDWN CLK CLK Y Y FBOUT FBOUT GND H L H L H L H Bypassed/off GND H H L H L H L Bypassed/off X L L H Z Z Z Z off X L H L Z Z Z Z off 2.5V(nom) H L H L H L H on 2.5V(nom) H H L H L H L on 2.5V(nom) X Z Z Z Z off