PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Features
Description
ÎÎPCIe® 3.0/2.0/1.0 compliant
The PI6LC48H02-01 is a clock generator compliant to PCI Express® 3.0/2.0/1.0 and Ethernet requirements. The device is used
for servers, networking or embedded systems.
àà PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.)
ÎÎLVDS compatible outputs
ÎÎSupply voltage of 3.3V ±10%
The PI6LC48H02-01 provides two differential (HCSL) or LVDS
outputs. Using Pericom's patented Phase Locked Loop (PLL)
techniques, the device takes a 25MHz crystal input and produces
two pairs of differential outputs (HCSL) at 25MHz, 100MHz,
125MHz, 200MHz clock frequencies.
ÎÎ25MHz crystal or clock input frequency
ÎÎHCSL outputs, 0.8V Current mode differential pair
ÎÎJitter 35ps cycle-to-cycle (typ)
ÎÎRMS phase jitter 12kHz ~ 20MHz @ 100MHz - 0.32ps (typ)
ÎÎRMS phase jitter 12kHz ~ 20MHz @ 125MHz - 0.3ps (typ)
ÎÎPower down mode
ÎÎIndustrial temperature range
ÎÎPackaging: (Pb-free and Green): 16-pin TSSOP (L16)
Pin Configuration (16-Pin TSSOP)
Block Diagram
VDD
S0
CLK0
S1:S0
Control
Logic
2
PD#
X1/CLK
CLK1
X1/CLK
25 MHz
crystal or clock X2
Pulling
Capacitors
S1
CLK0
Phase
Lock
Loop
X2
CLK1
Crystal
Driver
OE
GND
RR
PD#
GND
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NC
OE
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1
16
VDDX
2
15
CLK0
3
14
CLK0
4
13
GNDA
5
12
VDDA
6
11
CLK1
7
10
CLK1
8
9
IREF
PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Pin Description
Pin # Pin Name
I/O Type
Description
1
S0
Input
Select pin 0 (Internal pull-up resistor). See Table 1.
2
S1
Input
Select pin 1 (Internal pull-up resistor). See Table 1.
3
PD#
Input
Power down mode. Internla pull-up resistor. See Table 2.
4
X1/CLK
Input
Crystal or clock input. Connect to a 25MHz crystal or single ended clock.
5
X2
Output
Crystal connection. Leave unconnected for clock input.
6
OE
Input
Output enable. Internal pull-up resistor.
7
GND
Power
Ground
8
NC
-
Do not connect
9
IREF
Output
Precision resistor attached to this pin is connected to the internal current reference.
10
CLK1
Output
HCSL compliment clock output
11
CLK1
Output
HCSL clock output
12
VDDA
Power
Connect to a +3.3V source.
13
GNDA
Power
Output and analog circuit ground.
14
CLK0
Output
HCSL compliment clock output
15
CLK0
Output
HCSL clock output
16
VDDX
Power
Connect to a +3.3V source.
Table 1: Output Select Table
S1
S0
CLK(MHz)
0
0
25
0
1
100
1
0
125
1
1
200
Table 2: Power down mode
PD#
Device
0
Power down mode
1
Normal Operation mode, default
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Application Information
Output Structures
Decoupling Capacitors
Decoupling capacitors of 0.01μF should be connected between
each VDD pin and the ground plane and placed as close to the
VDD pin as possible.
IREF =2.3mA
6*IREF
Crystal
Use a 25MHz fundamental mode parallel resonant crystal with
less than 300PPM of error across temperature.
Crystal Capacitors
CL = Crystals's load capacitance in pF
Crystal Capacitors (pF) = (CL - 8) *2
R R=475 Ω
For example, for a crystal with 16pF load caps, the external effective crystal cap would be 16 pF. (16-8)*2=16.
See Output Termination
Sections
Current Source (IREF) Reference Resistor - R R
If board target trace impedance is 50Ω,
then R R = 475Ω providing an IREF of 2.32 mA. The output current (IOH) is 6*IREF.
Output Termination
The PCI Express differential clock outputs of the
PI6LC48H02-01 are open source drivers and require an external
series resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the PCI Express
Layout Guidelines section.
The PI6LC48H02-01 can be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout Guidelines section.
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
PCI Express Layout Guidelines
Common Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, route as non-coupled 50Ω trace.
0.5 max
inch
L2 length, route as non-coupled 50Ω trace.
0.2 max
inch
L3 length, route as non-coupled 50Ω trace.
0.2 max
inch
RS
33
Ω
RT
49.9
Ω
Differential Routing on a Single PCB
Dimension or Value
Unit
L4 length, route as coupled microstrip 100Ω differential trace.
2 min to 16 max
inch
L4 length, route as coupled stripline 100Ω differential trace.
1.8 min to 14.4 max
inch
Differential Routing to a PCI Express connector
Dimension or Value
Unit
L4 length, route as coupled microstrip 100Ω differential trace.
0.25 min to 14 max
inch
L4 length, route as coupled stripline 100Ω differential trace.
0.225 min to 12.6 max
inch
PCI Express Device Routing
L1
L2
RS
L1’
L4
L4’
L2’
RS
RT
PI6LC48H02-01
Output
Clock
L3’
RT
PCI-Express
Load or
Connector
L3
Typical PCI Express (HCSL) Waveform
800 mV
0
tOR
250 ps
400 ps
0.525 V
0.175 V
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15-0125
tOF
0.525 V
0.175 V
4
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Application Information
LVDS Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, route as non-coupled 50Ω trace.
0.5 max
inch
L2 length, route as non-coupled 50Ω trace.
0.2 max
inch
RP
100
Ω
RQ
100
Ω
RT
150
Ω
L3 length, route as 100Ω differential trace.
L3 length, route as 100Ω differential trace.
LVDS Device Routing
L1
L3
RQ
L3’
L1’
RT
PI6LC48H02-01
Clock
Output
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RT
L2’
15-0125
RP
LVDS
Device
Load
L2
5
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . 4.6V
All Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . -40 to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150°C
ESD Protection (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Electrical Specifications
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Unit
-40
+85
°C
+3.0
+3.6
V
DC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C)
Symbol
Parameter
VDD
Supply Voltage
Voltage(1)
Conditions
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
OE, S0, S1, PD#
2.0
VDD +0.3
V
Input Low Voltage(1)
OE, S0, S1, PD#
GND -0.3
0.8
V
IIH
Input High Current
Vin = VDD
-5
5
IIL
Input Low Current
Vin = 0
-20
20
IDD
Operating Supply Current
R L = 50Ω, CL = 2pF
100
115
mA
OE = LOW
58
65
mA
0.07
0.15
mA
VIH
Input High
VIL
IDDOE
µA
IDDPD
Power down Supply Current
PD# = LOW
CIN
Input Capacitance
@ 25MHz
7
pF
COUT
Output Capacitance
@ 25MHz
6
pF
LPIN
Pin Inductance
5
nH
ROUT
Output Resistance
CLK Outputs
3.0
kΩ
Notes:
1. Single edge is monotonic when transitioning through region.
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
HCSL Output AC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C)
Symbol
Parameter
FIN
Input Frequency
FOUT
Output Frequency
VOH
Output High Voltage (1,2)
VOL
Output Low Voltage(1,2)
VCPA
Crossing Point Voltage(1,2)
Absolute
VCN
Crossing Point Voltage
Variation over all edges
JCC
Jitter, Cycle-to-Cycle(1,3)
JPhase
JRMS2.0
Conditions
25
(1,2,4)
(Random)
PCIe 2.0 RMS Jitter
PCIe 3.0 RMS Jitter
tOR
Rise Time
tOF
Typ.
Max.
25
RMS Phase Jitter,
JRMS3.0
Min.
100 MHz HCSL output @ VDD =
3.3V
660
800
-150
0
250
350
Unit
MHz
200
MHz
900
mV
mV
550
mV
140
mV
35
60
ps
100MHz
25MHz Xtal input, 12kHz - 20MHz
0.33
0.5
ps
125MHz
25MHz Xtal input, 12kHz - 20MHz
0.3
0.5
ps
PCIe 2.0 Test Method @ 100MHz
Output
2.03
3.1
ps
PLL L-BW @ 2M & 5M 1st H3
0.51
3
ps
PLL L-BW @ 2M & 4M 1st H3
0.58
3
ps
PLL H-BW @ 2M & 5M 1st H3
0.44
1
ps
PLL H-BW @ 2M & 4M 1st H3
0.38
1
ps
From 0.175V to 0.525V
175
700
ps
Fall Time(1,2)
From 0.525V to 0.175V
175
700
ps
TSKEW
Skew between outputs
At Crossing Point Voltage
50
ps
TDUTY-CYCLE
Duty Cycle
55
%
TOE
Output Enable Time(5)
All outputs
10
μs
TOT
Output Disable Time
All outputs
10
μs
tSTABLE
Stabilization Time
(1,2)
45
(1,3)
(5)
14
From Power-up VDD =3.3V
ms
Notes:
1. RL = 50-Ohm with CL = 2 pF
2. Single-ended waveform
3. Differential waveform
4. Measured at the crossing point
5. CLK pins are tri-stated when OE is LOW
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Thermal Characteristics
Symbol
Parameter
Conditions
θJA
Thermal Resistance Junction to Ambient
Still air
θJC
Thermal Resistance Junction to Case
Min.
Typ.
Max.
Unit
90
°C/W
24
°C/W
Recomended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500091, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
Phase Noise Plot
100MHz
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125MHz
8
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PI6LC48H02-01
Rev B
09/23/2015
PI6LC48H02-01
PCIe® 3.0/2.0/1.0 Clock Generator with 2 HCSL Outputs
Packaging Mechanical: 16-Pin TSSOP (L)
16
.169
.177
1
.193
.201
4.9
5.1
4.3
4.5
.004
.008
.047
max.
1.20
0.45 .018
0.75 .030
SEATING
PLANE
.0256
BSC
0.65
.007
.012
.002
.006
0.09
0.20
.252
BSC
6.4
0.05
0.15
0.19
0.30
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Type
PI6LC48H02-01LIE
L
Pb-free & Green, 16-pin TSSOP
PI6LC48H02-01LIEX
L
Pb-free & Green, 16-pin TSSOP, Tape & Reel
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
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PI6LC48H02-01
Rev B
09/23/2015
