PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Features
Description
ÎÎThree
The PI6LC48P0301A is a 3-output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is
a member of Pericom’s HiFlexTM family of high performance
clock solutions. Using a 25MHz or other fundamental frequency
crystal, the most popular Ethernet frequencies can be generated
based on the settings of 4 frequency select pins.
differential LVPECL output pairs
ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL
single-ended clock input
ÎÎSupports the following output frequencies: 125MHz,
156.25MHz, 312.5MHz, 625MHz
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
The PI6LC48P0301A uses Pericom’s proprietary low phase noise
PLL technology to achieve ultra low phase jitter, so it is ideal for
Ethernet interface in all kind of systems.
(12kHz – 20MHz): 0.26ps (typical)
ÎÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.4ps (max)
ÎÎFull 3.3V or 2.5V supply modes
ÎÎCommercial and industrial ambient operating temperature
ÎÎAvailable in lead-free package: 28-TQFN
Applications
ÎÎNetworking systems
Block Diagram
NA_SEL[0:1]
OEA
CLKA
/A
XTAL_IN
XTAL_OUT
OSC
CLKA#
OEB
PFD
VCO
CLKB0
/B
CLKB0#
Ref_IN
IN_SEL#
CLKB1
M
CLKB1#
PLL_ByPass#
FBN
NB_SEL[0:1]
M_reset
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
PLL_NyPass#
NB_SEL0
NB_SEL1
VDDOB
Pin Configuration
28
27
26
25
M_reset
1
24
CLKB0
VDDOA
2
23
CLKB0#
CLKA
3
22
GND
CLKA#
4
21
CLKB1
OEB
5
20
CLKB1#
GND
6
19
GND
OEA
7
18
IN_SEL#
GND
XTAL_IN
VDDA
10
15
XTAL_OUT
11
12
13
14
GND
16
NA_SEL1
17
9
NA_SEL0
8
GND
VDD
FBN
Ref_IN
Pinout Table
Pin No.
Pin Name
I/O Type
1
M_reset
Input
2
VDDOA
Power
Bank A Output Power Supply
3,
4
CLKA,
CLKA#
Output
Bank A LVPECL Output Clock
5
OEB
Input
6, 9, 14,
19, 22
GND
Ground
7
OEA
Input
Pull-up
8
FBN
Input
Pull-down Feedback Divider Select
10
VDDA
Power
Analog Power Supply
11
VDD
Power
Core Power Supply
12, 13
NA_SEL0,
NA_SEL1
Input
15, 16
XTAL_OUT,
XTAL_IN
Crystal
17
Ref_IN
Input
Pull-down CMOS Reference Clock Input
18
IN_SEL#
Input
Pull-up
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Description
Pull-down
Pull-up
Master Reset. When HIGH, CLKx goes to “low” and CLKx# goes to
“high”; When LOW outputs are enabled.
Bank B Output Enable. When LOW, output is differential low.
Ground
Pull-up
Bank A Output Enable. When LOW, output is differential low.
Bank A Output Divider Select
Crystal Input and Output
When HIGH, Crystal is selected; When LOW, reference input is
selected.
2
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Pin No.
Pin Name
I/O Type
Description
20, 21
CLKB1#,
CLKB1
Output
Bank B LVPECL Output Clock 1
23, 24
CLKB0#,
CLKB0
Output
Bank B LVPECL Output Clock 0
25
VDDOB
Power
Bank B Output Power Supply
26, 27
NB_SEL1,
NB_SEL0
Input
Pull-up
Bank B Output Divider Select
28
PLL_ByPass#
Input
Pull-up
Active Low PLL Bypass
Bank A Frequency Table
Input
FBN
NA_SEL1
NA_SEL0
Feedback
Divider
Bank A
Output
Divider
25
0
0
0
25
1
625
25
0
0
1
25
2
312.5
20
0
0
1
25
2
250
22.5
0
1
0
25
3
187.5
25
0
1
1
25
4
156.25
24
0
1
1
25
4
150
20
0
1
1
25
4
125
19.44
1
0
0
32
1
622.08
19.44
1
0
1
32
2
311.04
15.625
1
0
1
32
2
250
18.75
1
1
0
32
3
200
19.44
1
1
1
32
4
155.52
18.75
1
1
1
32
4
150
15.625
1
1
1
32
4
125
Crystal Frequency
(MHz)
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CLKA/CLKA# Output Frequency
(MHz)
PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Bank B Frequency Table
Input
Crystal Frequency
(MHz)
Bank B
Output
Divider
CLKB0/CLKB0#, CLKB1/CLKB1#
Output Frequency (MHz)
FBN
NB_SEL1
NB_SEL0
Feedback
Divider
25
0
0
0
25
2
312.5
20
0
0
0
25
2
250
25
0
0
1
25
4
156.25
24
0
0
1
25
4
150
20
0
0
1
25
4
125
25
0
1
0
25
5
125
25
0
1
1
25
8
78.125
24
0
1
1
25
8
75
20
0
1
1
25
8
62.5
19.44
1
0
0
32
2
311.04
15.625
1
0
0
32
2
250
19.44
1
0
1
32
4
155.52
18.75
1
0
1
32
4
150
15.625
1
0
1
32
4
125
15.625
1
1
0
32
5
100
19.44
1
1
1
32
8
77.76
18.75
1
1
1
32
8
75
15.625
1
1
1
32
8
62.5
Typical Crystal Requirement
Parameter
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
FBN = 0
19.6
27.2
MHz
FBN = 1
15.313
21.25
MHz
Equivalent Series Resistance
(ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
Frequency
Recomended Crystal Specification
Pericom recommends:
a) FL2500047, SMD 3.2x2.5(4P), 25MHz, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
b) b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Maximum Ratings (Over operating free-air temperature range)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Storage Temperature............................................... -65ºC to+155ºC
Ambient Temperature with Power Applied..........-40ºC to+85ºC
3.3V Analog Supply Voltage.......................................-0.5 to +3.6V
ESD Protection (HBM).......................................................... 2000V
DC Electrical Characteristics
Power Supply DC Characterisitcs, (TA = -40 to 85ºC)
Symbol
Parameter
VDD
Condition
Min
Typ
Max
Units
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO_A
VDDO_B
Output Supply Voltage
3.135
3.3
3.465
V
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
VDDO_A
VDDO_B
Output Supply Voltage
2.375
2.5
2.625
V
IGND
Power Supply Current
150
mA
IDDA
Analog Supply Current
37
mA
Max
Units
V
LVCMOS/LVTTL DC Characterisitcs, (TA = -40 to 85ºC)
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Condition
Min
Typ
VDD = 3.3 V +/- 5%
2
VDD+ 0.3
VDD = 2.5 V +/- 5%
1.7
VDD+ 0.3
VDD = 3.3 V +/- 5%
-0.3
0.8
V
VDD = 2.5 V +/- 5%
-0.3
0.7
V
Ref_IN, FBN, M_reset
VDD = VIN = 3.465V
150
µA
Input High Current OEA, OEB, PLL_Bypass#, IN_SEL#, NA_
SEL[1:0], NB_SEL[1:0]
VDD = VIN = 3.465V
5
µA
Input Low Current
14-0083
Ref_IN, FBN, M_reset
VDD = 3.465V,
VIN = 0V
-5
µA
OEA, OEB, PLL_Bypass#, IN_SEL#, NA_
SEL[1:0], NB_SEL[1:0]
VDD = 3.465V,
VIN = 0V
-150
µA
5
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
LVPECL DC Characterisitcs, (TA = -40 to 85ºC)
Symbol
Parameter
VOH
Output High Voltage(1)
VOL
Output Low Voltage(1)
Condition
Min
Typ
Max
VDD = 3.3V
1.9
2.4
VDD = 2.5V
1.1
1.6
VDD = 3.3V
1.2
1.6
VDD = 2.5V
0.4
0.8
Units
V
V
Note: 1. LVPECL Termination: Source 150ohm to GND and 100ohm across CLK and CLK#.
14-0083
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
AC Electrical Characteristics
LVPECL Termination: Source 150ohm to GND and using 0.01uF ac-coupled to 50ohm to GND
AC Characterisitcs, (TA = -40 to 85ºC)
Symbol
fOUT
Parameter
Output Frequency Range
tsk(b)
Bank Skew(1)
tsk(o)
Output Skew(2,4)
tjit(Ø)
tR / tF
oDC
RMS Phase Jitter,
(Random)(3)
Output Rise/Fall Time
Output Duty Cycle
Condition
Min.
Otuput Divider = ÷1
Typ.
Max
Units
490
680
MHz
Otuput Divider = ÷2
245
340
MHz
Otuput Divider = ÷3
163.33
226.67
MHz
Otuput Divider = ÷4
122.5
170
MHz
Otuput Divider = ÷5
98
136
MHz
Otuput Divider = ÷8
61.25
85
MHz
25
ps
Output @ Same Frequencies
70
ps
Output @ Different Frequencies
200
ps
625MHz,
(1.875MHz - 20MHz)
0.14
625MHz,
(12kHz - 20MHz)
0.32
312.5MHz,
(1.875MHz - 20MHz)
0.15
312.5MHz,
(12kHz - 20MHz)
0.29
156.25MHz,
(1.875MHz - 20MHz)
0.14
156.25MHz,
(12kHz - 20MHz)
0.26
125MHz,
(1.875MHz - 20MHz)
0.17
125MHz,
(12kHz - 20MHz)
0.29
ps
0.4
ps
0.4
ps
ps
0.4
ps
ps
20% to 80%
Measured at the differential cross point
ps
0.4
ps
400
ps
Otuput Divider
= ÷1
47
53
%
Other divider
values
47
53
%
Note:
1. Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
2. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
3. Please refer to the Phase Noise Plots.
4. This parameter is defined in accordance with JEDEC Standard 65.
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Phase Noise Plots
fOUT = 625MHz
fOUT = 312.5MHz
fOUT = 156.25MHz
fOUT = 125MHz
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
LVPECL Test Circuit
ZO = 50Ω
0.01µF
L = 0 ~ 10in
Device
ZO = 50Ω
150Ω
50Ω
0.01µF
50Ω
150Ω
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The PI6LC48P0301A provides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through
vias, and 0.1μF bypass capacitors should be used for each pin. Figure below illustrates this for a generic VDD pin and also shows that
VDDA requires that an additional 10Ω resistor along with a 10μF bypass capacitor be connected to the VDDA pin.
3.3V or 2.5V
VDD
0.1µF
10Ω *
VDDA
0.1µF
10µF
* If VDD is 2.5V, the resistor value will be different, see app note for details
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs:
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. A 1kΩ
resistor can be tied from XTAL_IN to ground for additional protection.
Ref_IN Input:
For applications not requiring the use of the clock, it can be left floating. A 1kΩ resistor tied from the Ref_IN to ground can provide
additional protection.
LVCMOS Control Pins:
All control pins have internal pulldowns/pullups; A 1kΩ resistor tied from internal pulldown control pins to ground, and a 4.7kΩ
tied from internal pullup control pins to power supply can provide additional protection.
Outputs:
LVPECL Outputs:
All unused LVPECL outputs can be left floating.
Crystal Input Interface
The clock generator has been characterized with 18pF parallel resonant crystals. The capacitor values shown in the figure below
were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
22pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
22pF
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram
is shown in the figure below. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS
signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in
half. This can be done in one of the two ways. First, R1 and R2 in parallel should equal the transmission line empedance. For most
50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. By overdriving the
crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal.
VDD
VDD
R1
Rs
Ro
50Ω
0.1µF
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Thermal Information
Symbol
Description
QJA
Junction-to-ambient thermal resistance
QJC
Junction-to-case thermal resistance
14-0083
Condition
Still air
41.68 OC/W
23.78 OC/W
11
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PI6LC48P0301A
Rev. A
06/03/2014
PI6LC48P0301A
3-Output LVPECL Networking Clock Generator
Packaging Mechanical: 28-Contact TQFN (ZH)
Ordering Information
Ordering Code
Packaging Type
Package Description
Operating Temperature
PI6LC48P0301AZHE
ZH
Pb-free & Green, 28-pin TQFN
Commercial
PI6LC48P0301AZHIE
ZH
Pb-free & Green, 28-pin TQFN
Industrial
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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PI6LC48P0301A
Rev. A
06/03/2014
